git.sur5r.net Git - u-boot/blob - drivers/i2c/i2c-cdns.c

   1 /*
   2  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   3  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   4  *
   5  * This file is based on: drivers/i2c/zynq_i2c.c,
   6  * with added driver-model support and code cleanup.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/errno.h>
  15 #include <dm/device.h>
  16 #include <dm/root.h>
  17 #include <i2c.h>
  18 #include <fdtdec.h>
  19 #include <mapmem.h>
  20 #include <wait_bit.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 /* i2c register set */
  25 struct cdns_i2c_regs {
  26         u32 control;
  27         u32 status;
  28         u32 address;
  29         u32 data;
  30         u32 interrupt_status;
  31         u32 transfer_size;
  32         u32 slave_mon_pause;
  33         u32 time_out;
  34         u32 interrupt_mask;
  35         u32 interrupt_enable;
  36         u32 interrupt_disable;
  37 };
  38
  39 /* Control register fields */
  40 #define CDNS_I2C_CONTROL_RW             0x00000001
  41 #define CDNS_I2C_CONTROL_MS             0x00000002
  42 #define CDNS_I2C_CONTROL_NEA            0x00000004
  43 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  44 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  45 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  46 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  47 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  48 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  49 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  50 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  51
  52 /* Status register values */
  53 #define CDNS_I2C_STATUS_RXDV    0x00000020
  54 #define CDNS_I2C_STATUS_TXDV    0x00000040
  55 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  56 #define CDNS_I2C_STATUS_BA      0x00000100
  57
  58 /* Interrupt register fields */
  59 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  60 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  61 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  62 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  63 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  64 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  65 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  66 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  67 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  68
  69 #define CDNS_I2C_FIFO_DEPTH             16
  70 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  71 #define CDNS_I2C_TRANSFER_SIZE          (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  72
  73 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
  74
  75 #ifdef DEBUG
  76 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  77 {
  78         int int_status;
  79         int status;
  80         int_status = readl(&cdns_i2c->interrupt_status);
  81
  82         status = readl(&cdns_i2c->status);
  83         if (int_status || status) {
  84                 debug("Status: ");
  85                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
  86                         debug("COMP ");
  87                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
  88                         debug("DATA ");
  89                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
  90                         debug("NACK ");
  91                 if (int_status & CDNS_I2C_INTERRUPT_TO)
  92                         debug("TO ");
  93                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
  94                         debug("SLVRDY ");
  95                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
  96                         debug("RXOVF ");
  97                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
  98                         debug("TXOVF ");
  99                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
 100                         debug("RXUNF ");
 101                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
 102                         debug("ARBLOST ");
 103                 if (status & CDNS_I2C_STATUS_RXDV)
 104                         debug("RXDV ");
 105                 if (status & CDNS_I2C_STATUS_TXDV)
 106                         debug("TXDV ");
 107                 if (status & CDNS_I2C_STATUS_RXOVF)
 108                         debug("RXOVF ");
 109                 if (status & CDNS_I2C_STATUS_BA)
 110                         debug("BA ");
 111                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 112                 debug("\n");
 113         }
 114 }
 115 #endif
 116
 117 struct i2c_cdns_bus {
 118         int id;
 119         unsigned int input_freq;
 120         struct cdns_i2c_regs __iomem *regs;     /* register base */
 121
 122         int hold_flag;
 123         u32 quirks;
 124 };
 125
 126 struct cdns_i2c_platform_data {
 127         u32 quirks;
 128 };
 129
 130 /* Wait for an interrupt */
 131 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 132 {
 133         int timeout, int_status;
 134
 135         for (timeout = 0; timeout < 100; timeout++) {
 136                 int_status = readl(&cdns_i2c->interrupt_status);
 137                 if (int_status & mask)
 138                         break;
 139                 udelay(100);
 140         }
 141
 142         /* Clear interrupt status flags */
 143         writel(int_status & mask, &cdns_i2c->interrupt_status);
 144
 145         return int_status & mask;
 146 }
 147
 148 #define CDNS_I2C_DIVA_MAX       4
 149 #define CDNS_I2C_DIVB_MAX       64
 150
 151 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 152                 unsigned int *a, unsigned int *b)
 153 {
 154         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 155         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 156         unsigned int last_error, current_error;
 157
 158         /* calculate (divisor_a+1) x (divisor_b+1) */
 159         temp = input_clk / (22 * fscl);
 160
 161         /*
 162          * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
 163          * the fscl input is out of range. Return error.
 164          */
 165         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 166                 return -EINVAL;
 167
 168         last_error = -1;
 169         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 170                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 171
 172                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 173                         continue;
 174                 div_b--;
 175
 176                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 177
 178                 if (actual_fscl > fscl)
 179                         continue;
 180
 181                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 182                                                         (fscl - actual_fscl));
 183
 184                 if (last_error > current_error) {
 185                         calc_div_a = div_a;
 186                         calc_div_b = div_b;
 187                         best_fscl = actual_fscl;
 188                         last_error = current_error;
 189                 }
 190         }
 191
 192         *a = calc_div_a;
 193         *b = calc_div_b;
 194         *f = best_fscl;
 195
 196         return 0;
 197 }
 198
 199 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 200 {
 201         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 202         u32 div_a = 0, div_b = 0;
 203         unsigned long speed_p = speed;
 204         int ret = 0;
 205
 206         if (speed > 400000) {
 207                 debug("%s, failed to set clock speed to %u\n", __func__,
 208                       speed);
 209                 return -EINVAL;
 210         }
 211
 212         ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
 213         if (ret)
 214                 return ret;
 215
 216         debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
 217               __func__, div_a, div_b, bus->input_freq, speed, speed_p);
 218
 219         writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 220                (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 221
 222         /* Enable master mode, ack, and 7-bit addressing */
 223         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 224                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 225
 226         return 0;
 227 }
 228
 229 /* Probe to see if a chip is present. */
 230 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 231                                 uint chip_flags)
 232 {
 233         struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
 234         struct cdns_i2c_regs *regs = i2c_bus->regs;
 235
 236         /* Attempt to read a byte */
 237         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 238                 CDNS_I2C_CONTROL_RW);
 239         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 240         writel(0xFF, &regs->interrupt_status);
 241         writel(chip_addr, &regs->address);
 242         writel(1, &regs->transfer_size);
 243
 244         return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 245                 CDNS_I2C_INTERRUPT_NACK) &
 246                 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 247 }
 248
 249 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 250                                u32 len)
 251 {
 252         u8 *cur_data = data;
 253         struct cdns_i2c_regs *regs = i2c_bus->regs;
 254
 255         /* Set the controller in Master transmit mode and clear FIFO */
 256         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
 257         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 258
 259         /* Check message size against FIFO depth, and set hold bus bit
 260          * if it is greater than FIFO depth
 261          */
 262         if (len > CDNS_I2C_FIFO_DEPTH)
 263                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 264
 265         /* Clear the interrupts in status register */
 266         writel(0xFF, &regs->interrupt_status);
 267
 268         writel(addr, &regs->address);
 269
 270         while (len--) {
 271                 writel(*(cur_data++), &regs->data);
 272                 if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 273                         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
 274                                 /* Release the bus */
 275                                 clrbits_le32(&regs->control,
 276                                              CDNS_I2C_CONTROL_HOLD);
 277                                 return -ETIMEDOUT;
 278                         }
 279                 }
 280         }
 281
 282         /* All done... release the bus */
 283         if (!i2c_bus->hold_flag)
 284                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 285
 286         /* Wait for the address and data to be sent */
 287         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
 288                 return -ETIMEDOUT;
 289         return 0;
 290 }
 291
 292 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
 293 {
 294         return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
 295 }
 296
 297 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 298                               u32 recv_count)
 299 {
 300         u8 *cur_data = data;
 301         struct cdns_i2c_regs *regs = i2c_bus->regs;
 302         int curr_recv_count;
 303         int updatetx, hold_quirk;
 304
 305         /* Check the hardware can handle the requested bytes */
 306         if ((recv_count < 0))
 307                 return -EINVAL;
 308
 309         curr_recv_count = recv_count;
 310
 311         /* Check for the message size against the FIFO depth */
 312         if (recv_count > CDNS_I2C_FIFO_DEPTH)
 313                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 314
 315         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 316                 CDNS_I2C_CONTROL_RW);
 317
 318         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 319                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 320                 writel(curr_recv_count, &regs->transfer_size);
 321         } else {
 322                 writel(recv_count, &regs->transfer_size);
 323         }
 324
 325         /* Start reading data */
 326         writel(addr, &regs->address);
 327
 328         updatetx = recv_count > curr_recv_count;
 329
 330         hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 331
 332         while (recv_count) {
 333                 while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
 334                         if (recv_count < CDNS_I2C_FIFO_DEPTH &&
 335                             !i2c_bus->hold_flag) {
 336                                 clrbits_le32(&regs->control,
 337                                              CDNS_I2C_CONTROL_HOLD);
 338                         }
 339                         *(cur_data)++ = readl(&regs->data);
 340                         recv_count--;
 341                         curr_recv_count--;
 342
 343                         if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
 344                                 break;
 345                 }
 346
 347                 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
 348                         /* wait while fifo is full */
 349                         while (readl(&regs->transfer_size) !=
 350                                      (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 351                                 ;
 352                         /*
 353                          * Check number of bytes to be received against maximum
 354                          * transfer size and update register accordingly.
 355                          */
 356                         if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
 357                             CDNS_I2C_TRANSFER_SIZE) {
 358                                 writel(CDNS_I2C_TRANSFER_SIZE,
 359                                        &regs->transfer_size);
 360                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 361                                         CDNS_I2C_FIFO_DEPTH;
 362                         } else {
 363                                 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
 364                                        &regs->transfer_size);
 365                                 curr_recv_count = recv_count;
 366                         }
 367                 } else if (recv_count && !hold_quirk && !curr_recv_count) {
 368                         writel(addr, &regs->address);
 369                         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 370                                 writel(CDNS_I2C_TRANSFER_SIZE,
 371                                        &regs->transfer_size);
 372                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 373                         } else {
 374                                 writel(recv_count, &regs->transfer_size);
 375                                 curr_recv_count = recv_count;
 376                         }
 377                 }
 378         }
 379
 380         /* Wait for the address and data to be sent */
 381         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
 382                 return -ETIMEDOUT;
 383
 384         return 0;
 385 }
 386
 387 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 388                          int nmsgs)
 389 {
 390         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 391         int ret, count;
 392         bool hold_quirk;
 393
 394         hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 395
 396         if (nmsgs > 1) {
 397                 /*
 398                  * This controller does not give completion interrupt after a
 399                  * master receive message if HOLD bit is set (repeated start),
 400                  * resulting in SW timeout. Hence, if a receive message is
 401                  * followed by any other message, an error is returned
 402                  * indicating that this sequence is not supported.
 403                  */
 404                 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
 405                         if (msg[count].flags & I2C_M_RD) {
 406                                 printf("Can't do repeated start after a receive message\n");
 407                                 return -EOPNOTSUPP;
 408                         }
 409                 }
 410
 411                 i2c_bus->hold_flag = 1;
 412                 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
 413         } else {
 414                 i2c_bus->hold_flag = 0;
 415         }
 416
 417         debug("i2c_xfer: %d messages\n", nmsgs);
 418         for (; nmsgs > 0; nmsgs--, msg++) {
 419                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 420                 if (msg->flags & I2C_M_RD) {
 421                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 422                                                  msg->len);
 423                 } else {
 424                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 425                                                   msg->len);
 426                 }
 427                 if (ret) {
 428                         debug("i2c_write: error sending\n");
 429                         return -EREMOTEIO;
 430                 }
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 437 {
 438         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 439         struct cdns_i2c_platform_data *pdata =
 440                 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
 441
 442         i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
 443         if (!i2c_bus->regs)
 444                 return -ENOMEM;
 445
 446         if (pdata)
 447                 i2c_bus->quirks = pdata->quirks;
 448
 449         i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
 450
 451         return 0;
 452 }
 453
 454 static const struct dm_i2c_ops cdns_i2c_ops = {
 455         .xfer = cdns_i2c_xfer,
 456         .probe_chip = cdns_i2c_probe_chip,
 457         .set_bus_speed = cdns_i2c_set_bus_speed,
 458 };
 459
 460 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
 461         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 462 };
 463
 464 static const struct udevice_id cdns_i2c_of_match[] = {
 465         { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
 466         { .compatible = "cdns,i2c-r1p14" },
 467         { /* end of table */ }
 468 };
 469
 470 U_BOOT_DRIVER(cdns_i2c) = {
 471         .name = "i2c-cdns",
 472         .id = UCLASS_I2C,
 473         .of_match = cdns_i2c_of_match,
 474         .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 475         .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 476         .ops = &cdns_i2c_ops,
 477 };