2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * This file is based on: drivers/i2c/zynq_i2c.c,
6 * with added driver-model support and code cleanup.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/types.h>
14 #include <linux/errno.h>
15 #include <dm/device.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* i2c register set */
24 struct cdns_i2c_regs {
35 u32 interrupt_disable;
38 /* Control register fields */
39 #define CDNS_I2C_CONTROL_RW 0x00000001
40 #define CDNS_I2C_CONTROL_MS 0x00000002
41 #define CDNS_I2C_CONTROL_NEA 0x00000004
42 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
43 #define CDNS_I2C_CONTROL_HOLD 0x00000010
44 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
45 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
47 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
49 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
51 /* Status register values */
52 #define CDNS_I2C_STATUS_RXDV 0x00000020
53 #define CDNS_I2C_STATUS_TXDV 0x00000040
54 #define CDNS_I2C_STATUS_RXOVF 0x00000080
55 #define CDNS_I2C_STATUS_BA 0x00000100
57 /* Interrupt register fields */
58 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
59 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
60 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
61 #define CDNS_I2C_INTERRUPT_TO 0x00000008
62 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
63 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
64 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
65 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
66 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
68 #define CDNS_I2C_FIFO_DEPTH 16
69 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
70 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
73 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
77 int_status = readl(&cdns_i2c->interrupt_status);
79 status = readl(&cdns_i2c->status);
80 if (int_status || status) {
82 if (int_status & CDNS_I2C_INTERRUPT_COMP)
84 if (int_status & CDNS_I2C_INTERRUPT_DATA)
86 if (int_status & CDNS_I2C_INTERRUPT_NACK)
88 if (int_status & CDNS_I2C_INTERRUPT_TO)
90 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
92 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
94 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
96 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
98 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
100 if (status & CDNS_I2C_STATUS_RXDV)
102 if (status & CDNS_I2C_STATUS_TXDV)
104 if (status & CDNS_I2C_STATUS_RXOVF)
106 if (status & CDNS_I2C_STATUS_BA)
108 debug("TS%d ", readl(&cdns_i2c->transfer_size));
114 struct i2c_cdns_bus {
116 unsigned int input_freq;
117 struct cdns_i2c_regs __iomem *regs; /* register base */
123 struct cdns_i2c_platform_data {
127 /* Wait for an interrupt */
128 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
130 int timeout, int_status;
132 for (timeout = 0; timeout < 100; timeout++) {
133 int_status = readl(&cdns_i2c->interrupt_status);
134 if (int_status & mask)
139 /* Clear interrupt status flags */
140 writel(int_status & mask, &cdns_i2c->interrupt_status);
142 return int_status & mask;
145 #define CDNS_I2C_DIVA_MAX 4
146 #define CDNS_I2C_DIVB_MAX 64
148 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
149 unsigned int *a, unsigned int *b)
151 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
152 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
153 unsigned int last_error, current_error;
155 /* calculate (divisor_a+1) x (divisor_b+1) */
156 temp = input_clk / (22 * fscl);
159 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
160 * the fscl input is out of range. Return error.
162 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
166 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
167 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
169 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
173 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
175 if (actual_fscl > fscl)
178 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
179 (fscl - actual_fscl));
181 if (last_error > current_error) {
184 best_fscl = actual_fscl;
185 last_error = current_error;
196 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
198 struct i2c_cdns_bus *bus = dev_get_priv(dev);
199 u32 div_a = 0, div_b = 0;
200 unsigned long speed_p = speed;
203 if (speed > 400000) {
204 debug("%s, failed to set clock speed to %u\n", __func__,
209 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
213 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
214 __func__, div_a, div_b, bus->input_freq, speed, speed_p);
216 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
217 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
219 /* Enable master mode, ack, and 7-bit addressing */
220 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
221 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
226 /* Probe to see if a chip is present. */
227 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
230 struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
231 struct cdns_i2c_regs *regs = i2c_bus->regs;
233 /* Attempt to read a byte */
234 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
235 CDNS_I2C_CONTROL_RW);
236 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
237 writel(0xFF, ®s->interrupt_status);
238 writel(chip_addr, ®s->address);
239 writel(1, ®s->transfer_size);
241 return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
242 CDNS_I2C_INTERRUPT_NACK) &
243 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
246 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
251 struct cdns_i2c_regs *regs = i2c_bus->regs;
253 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
256 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
258 writel(0xFF, ®s->interrupt_status);
259 writel(addr, ®s->address);
262 writel(*(cur_data++), ®s->data);
263 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
264 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
265 /* Release the bus */
266 clrbits_le32(®s->control,
267 CDNS_I2C_CONTROL_HOLD);
273 /* All done... release the bus */
274 if (!i2c_bus->hold_flag)
275 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
277 /* Wait for the address and data to be sent */
278 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
283 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
291 struct cdns_i2c_regs *regs = i2c_bus->regs;
293 /* Check the hardware can handle the requested bytes */
297 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
298 CDNS_I2C_CONTROL_RW);
300 /* Start reading data */
301 writel(addr, ®s->address);
302 writel(len, ®s->transfer_size);
306 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
307 CDNS_I2C_INTERRUPT_DATA);
309 /* Release the bus */
310 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
313 debug("Read %d bytes\n",
314 len - readl(®s->transfer_size));
315 for (; i < len - readl(®s->transfer_size); i++)
316 *(cur_data++) = readl(®s->data);
317 } while (readl(®s->transfer_size) != 0);
318 /* All done... release the bus */
319 if (!i2c_bus->hold_flag)
320 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
323 cdns_i2c_debug_status(regs);
328 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
331 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
335 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
339 * This controller does not give completion interrupt after a
340 * master receive message if HOLD bit is set (repeated start),
341 * resulting in SW timeout. Hence, if a receive message is
342 * followed by any other message, an error is returned
343 * indicating that this sequence is not supported.
345 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
346 if (msg[count].flags & I2C_M_RD) {
347 printf("Can't do repeated start after a receive message\n");
352 i2c_bus->hold_flag = 1;
353 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
355 i2c_bus->hold_flag = 0;
358 debug("i2c_xfer: %d messages\n", nmsgs);
359 for (; nmsgs > 0; nmsgs--, msg++) {
360 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
361 if (msg->flags & I2C_M_RD) {
362 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
365 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
369 debug("i2c_write: error sending\n");
377 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
379 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
380 struct cdns_i2c_platform_data *pdata =
381 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
383 i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
388 i2c_bus->quirks = pdata->quirks;
390 i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
395 static const struct dm_i2c_ops cdns_i2c_ops = {
396 .xfer = cdns_i2c_xfer,
397 .probe_chip = cdns_i2c_probe_chip,
398 .set_bus_speed = cdns_i2c_set_bus_speed,
401 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
402 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
405 static const struct udevice_id cdns_i2c_of_match[] = {
406 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
407 { .compatible = "cdns,i2c-r1p14" },
408 { /* end of table */ }
411 U_BOOT_DRIVER(cdns_i2c) = {
414 .of_match = cdns_i2c_of_match,
415 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
416 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
417 .ops = &cdns_i2c_ops,