1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductors, Inc.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <imx_lpi2c.h>
12 #include <asm/arch/sys_proto.h>
17 #define LPI2C_FIFO_SIZE 4
18 #define LPI2C_NACK_TOUT_MS 1
19 #define LPI2C_TIMEOUT_MS 100
21 static int bus_i2c_init(struct udevice *bus, int speed);
23 /* Weak linked function for overridden by some SoC power function */
24 int __weak init_i2c_power(unsigned i2c_num)
29 static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
31 lpi2c_status_t result = LPI2C_SUCESS;
34 status = readl(®s->msr);
36 if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
42 static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
44 lpi2c_status_t result = LPI2C_SUCESS;
47 status = readl(®s->msr);
48 /* errors to check for */
49 status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
50 LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
53 if (status & LPI2C_MSR_PLTF_MASK)
54 result = LPI2C_PIN_LOW_TIMEOUT_ERR;
55 else if (status & LPI2C_MSR_ALF_MASK)
56 result = LPI2C_ARB_LOST_ERR;
57 else if (status & LPI2C_MSR_NDF_MASK)
58 result = LPI2C_NAK_ERR;
59 else if (status & LPI2C_MSR_FEF_MASK)
60 result = LPI2C_FIFO_ERR;
62 /* clear status flags */
63 writel(0x7f00, ®s->msr);
65 val = readl(®s->mcr);
66 val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
67 writel(val, ®s->mcr);
73 static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
75 lpi2c_status_t result = LPI2C_SUCESS;
77 ulong start_time = get_timer(0);
80 txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr));
81 txcount = LPI2C_FIFO_SIZE - txcount;
82 result = imx_lpci2c_check_clear_error(regs);
84 debug("i2c: wait for tx ready: result 0x%x\n", result);
87 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
88 debug("i2c: wait for tx ready: timeout\n");
96 static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
98 struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
99 lpi2c_status_t result = LPI2C_SUCESS;
106 result = bus_i2c_wait_for_tx_ready(regs);
108 debug("i2c: send wait fot tx ready: %d\n", result);
111 writel(*txbuf++, ®s->mtdr);
117 static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
119 struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
120 lpi2c_status_t result = LPI2C_SUCESS;
122 ulong start_time = get_timer(0);
128 result = bus_i2c_wait_for_tx_ready(regs);
130 debug("i2c: receive wait fot tx ready: %d\n", result);
134 /* clear all status flags */
135 writel(0x7f00, ®s->msr);
136 /* send receive command */
137 val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
138 writel(val, ®s->mtdr);
142 result = imx_lpci2c_check_clear_error(regs);
144 debug("i2c: receive check clear error: %d\n",
148 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
149 debug("i2c: receive mrdr: timeout\n");
152 val = readl(®s->mrdr);
153 } while (val & LPI2C_MRDR_RXEMPTY_MASK);
154 *rxbuf++ = LPI2C_MRDR_DATA(val);
160 static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
162 lpi2c_status_t result;
163 struct imx_lpi2c_reg *regs =
164 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
167 result = imx_lpci2c_check_busy_bus(regs);
169 debug("i2c: start check busy bus: 0x%x\n", result);
171 /* Try to init the lpi2c then check the bus busy again */
172 bus_i2c_init(bus, 100000);
173 result = imx_lpci2c_check_busy_bus(regs);
175 printf("i2c: Error check busy bus: 0x%x\n", result);
179 /* clear all status flags */
180 writel(0x7f00, ®s->msr);
181 /* turn off auto-stop condition */
182 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
183 writel(val, ®s->mcfgr1);
184 /* wait tx fifo ready */
185 result = bus_i2c_wait_for_tx_ready(regs);
187 debug("i2c: start wait for tx ready: 0x%x\n", result);
190 /* issue start command */
191 val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
192 writel(val, ®s->mtdr);
197 static int bus_i2c_stop(struct udevice *bus)
199 lpi2c_status_t result;
200 struct imx_lpi2c_reg *regs =
201 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
205 result = bus_i2c_wait_for_tx_ready(regs);
207 debug("i2c: stop wait for tx ready: 0x%x\n", result);
211 /* send stop command */
212 writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr);
214 start_time = get_timer(0);
216 status = readl(®s->msr);
217 result = imx_lpci2c_check_clear_error(regs);
218 /* stop detect flag */
219 if (status & LPI2C_MSR_SDF_MASK) {
220 /* clear stop flag */
221 status &= LPI2C_MSR_SDF_MASK;
222 writel(status, ®s->msr);
226 if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
227 debug("stop timeout\n");
235 static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
237 lpi2c_status_t result;
239 result = bus_i2c_start(bus, chip, 1);
242 result = bus_i2c_receive(bus, buf, len);
249 static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
251 lpi2c_status_t result;
253 result = bus_i2c_start(bus, chip, 0);
256 result = bus_i2c_send(bus, buf, len);
264 static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
266 struct imx_lpi2c_reg *regs;
268 u32 preescale = 0, best_pre = 0, clkhi = 0;
269 u32 best_clkhi = 0, abs_error = 0, rate;
270 u32 error = 0xffffffff;
275 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
276 clock_rate = imx_get_i2cclk(bus->seq);
280 mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
281 /* disable master mode */
282 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
283 writel(val | LPI2C_MCR_MEN(0), ®s->mcr);
285 for (preescale = 1; (preescale <= 128) &&
286 (error != 0); preescale = 2 * preescale) {
287 for (clkhi = 1; clkhi < 32; clkhi++) {
289 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
291 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
293 abs_error = speed > rate ? speed - rate : rate - speed;
295 if (abs_error < error) {
296 best_pre = preescale;
305 /* Standard, fast, fast mode plus and ultra-fast transfers. */
306 val = LPI2C_MCCR0_CLKHI(best_clkhi);
308 val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
310 val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
311 LPI2C_MCCR0_DATAVD(best_clkhi / 2);
312 writel(val, ®s->mccr0);
314 for (i = 0; i < 8; i++) {
315 if (best_pre == (1 << i)) {
321 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
322 writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1);
325 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
326 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
332 static int bus_i2c_init(struct udevice *bus, int speed)
334 struct imx_lpi2c_reg *regs;
338 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
339 /* reset peripheral */
340 writel(LPI2C_MCR_RST_MASK, ®s->mcr);
341 writel(0x0, ®s->mcr);
342 /* Disable Dozen mode */
343 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr);
344 /* host request disable, active high, external pin */
345 val = readl(®s->mcfgr0);
346 val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
347 LPI2C_MCFGR0_HRSEL_MASK));
348 val |= LPI2C_MCFGR0_HRPOL(0x1);
349 writel(val, ®s->mcfgr0);
350 /* pincfg and ignore ack */
351 val = readl(®s->mcfgr1);
352 val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
353 val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
354 val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
355 writel(val, ®s->mcfgr1);
357 ret = bus_i2c_set_bus_speed(bus, speed);
359 /* enable lpi2c in master mode */
360 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
361 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
363 debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
368 static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
371 lpi2c_status_t result;
373 result = bus_i2c_start(bus, chip, 0);
376 bus_i2c_init(bus, 100000);
380 result = bus_i2c_stop(bus);
382 bus_i2c_init(bus, 100000);
387 static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
389 int ret = 0, ret_stop;
391 for (; nmsgs > 0; nmsgs--, msg++) {
392 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
393 if (msg->flags & I2C_M_RD)
394 ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
396 ret = bus_i2c_write(bus, msg->addr, msg->buf,
404 debug("i2c_write: error sending\n");
406 ret_stop = bus_i2c_stop(bus);
408 debug("i2c_xfer: stop bus error\n");
415 static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
417 return bus_i2c_set_bus_speed(bus, speed);
420 static int imx_lpi2c_probe(struct udevice *bus)
422 struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
426 i2c_bus->driver_data = dev_get_driver_data(bus);
428 addr = devfdt_get_addr(bus);
429 if (addr == FDT_ADDR_T_NONE)
432 i2c_bus->base = addr;
433 i2c_bus->index = bus->seq;
436 /* power up i2c resource */
437 ret = init_i2c_power(bus->seq);
439 debug("init_i2c_power err = %d\n", ret);
443 /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
444 ret = enable_i2c_clk(1, bus->seq);
448 ret = bus_i2c_init(bus, 100000);
452 debug("i2c : controller bus %d at %lu , speed %d: ",
453 bus->seq, i2c_bus->base,
459 static const struct dm_i2c_ops imx_lpi2c_ops = {
460 .xfer = imx_lpi2c_xfer,
461 .probe_chip = imx_lpi2c_probe_chip,
462 .set_bus_speed = imx_lpi2c_set_bus_speed,
465 static const struct udevice_id imx_lpi2c_ids[] = {
466 { .compatible = "fsl,imx7ulp-lpi2c", },
467 { .compatible = "fsl,imx8qm-lpi2c", },
471 U_BOOT_DRIVER(imx_lpi2c) = {
474 .of_match = imx_lpi2c_ids,
475 .probe = imx_lpi2c_probe,
476 .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
477 .ops = &imx_lpi2c_ops,