git.sur5r.net Git - u-boot/blob - drivers/i2c/kona_i2c.c

   1 /*
   2  * Copyright 2013 Broadcom Corporation.
   3  *
   4  * SPDX-License-Identifier:      GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/errno.h>
  10 #include <asm/arch/sysmap.h>
  11 #include <asm/kona-common/clk.h>
  12 #include <i2c.h>
  13
  14 /* Hardware register offsets and field defintions */
  15 #define CS_OFFSET                               0x00000020
  16 #define CS_ACK_SHIFT                            3
  17 #define CS_ACK_MASK                             0x00000008
  18 #define CS_ACK_CMD_GEN_START                    0x00000000
  19 #define CS_ACK_CMD_GEN_RESTART                  0x00000001
  20 #define CS_CMD_SHIFT                            1
  21 #define CS_CMD_CMD_NO_ACTION                    0x00000000
  22 #define CS_CMD_CMD_START_RESTART                0x00000001
  23 #define CS_CMD_CMD_STOP                         0x00000002
  24 #define CS_EN_SHIFT                             0
  25 #define CS_EN_CMD_ENABLE_BSC                    0x00000001
  26
  27 #define TIM_OFFSET                              0x00000024
  28 #define TIM_PRESCALE_SHIFT                      6
  29 #define TIM_P_SHIFT                             3
  30 #define TIM_NO_DIV_SHIFT                        2
  31 #define TIM_DIV_SHIFT                           0
  32
  33 #define DAT_OFFSET                              0x00000028
  34
  35 #define TOUT_OFFSET                             0x0000002c
  36
  37 #define TXFCR_OFFSET                            0x0000003c
  38 #define TXFCR_FIFO_FLUSH_MASK                   0x00000080
  39 #define TXFCR_FIFO_EN_MASK                      0x00000040
  40
  41 #define IER_OFFSET                              0x00000044
  42 #define IER_READ_COMPLETE_INT_MASK              0x00000010
  43 #define IER_I2C_INT_EN_MASK                     0x00000008
  44 #define IER_FIFO_INT_EN_MASK                    0x00000002
  45 #define IER_NOACK_EN_MASK                       0x00000001
  46
  47 #define ISR_OFFSET                              0x00000048
  48 #define ISR_RESERVED_MASK                       0xffffff60
  49 #define ISR_CMDBUSY_MASK                        0x00000080
  50 #define ISR_READ_COMPLETE_MASK                  0x00000010
  51 #define ISR_SES_DONE_MASK                       0x00000008
  52 #define ISR_ERR_MASK                            0x00000004
  53 #define ISR_TXFIFOEMPTY_MASK                    0x00000002
  54 #define ISR_NOACK_MASK                          0x00000001
  55
  56 #define CLKEN_OFFSET                            0x0000004c
  57 #define CLKEN_AUTOSENSE_OFF_MASK                0x00000080
  58 #define CLKEN_M_SHIFT                           4
  59 #define CLKEN_N_SHIFT                           1
  60 #define CLKEN_CLKEN_MASK                        0x00000001
  61
  62 #define FIFO_STATUS_OFFSET                      0x00000054
  63 #define FIFO_STATUS_RXFIFO_EMPTY_MASK           0x00000004
  64 #define FIFO_STATUS_TXFIFO_EMPTY_MASK           0x00000010
  65
  66 #define HSTIM_OFFSET                            0x00000058
  67 #define HSTIM_HS_MODE_MASK                      0x00008000
  68 #define HSTIM_HS_HOLD_SHIFT                     10
  69 #define HSTIM_HS_HIGH_PHASE_SHIFT               5
  70 #define HSTIM_HS_SETUP_SHIFT                    0
  71
  72 #define PADCTL_OFFSET                           0x0000005c
  73 #define PADCTL_PAD_OUT_EN_MASK                  0x00000004
  74
  75 #define RXFCR_OFFSET                            0x00000068
  76 #define RXFCR_NACK_EN_SHIFT                     7
  77 #define RXFCR_READ_COUNT_SHIFT                  0
  78 #define RXFIFORDOUT_OFFSET                      0x0000006c
  79
  80 /* Locally used constants */
  81 #define MAX_RX_FIFO_SIZE                64U     /* bytes */
  82 #define MAX_TX_FIFO_SIZE                64U     /* bytes */
  83
  84 #define I2C_TIMEOUT                     100000  /* usecs */
  85
  86 #define WAIT_INT_CHK                    100     /* usecs */
  87 #if I2C_TIMEOUT % WAIT_INT_CHK
  88 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  89 #endif
  90
  91 /* Operations that can be commanded to the controller */
  92 enum bcm_kona_cmd_t {
  93         BCM_CMD_NOACTION = 0,
  94         BCM_CMD_START,
  95         BCM_CMD_RESTART,
  96         BCM_CMD_STOP,
  97 };
  98
  99 enum bus_speed_index {
 100         BCM_SPD_100K = 0,
 101         BCM_SPD_400K,
 102         BCM_SPD_1MHZ,
 103 };
 104
 105 /* Internal divider settings for standard mode, fast mode and fast mode plus */
 106 struct bus_speed_cfg {
 107         uint8_t time_m;         /* Number of cycles for setup time */
 108         uint8_t time_n;         /* Number of cycles for hold time */
 109         uint8_t prescale;       /* Prescale divider */
 110         uint8_t time_p;         /* Timing coefficient */
 111         uint8_t no_div;         /* Disable clock divider */
 112         uint8_t time_div;       /* Post-prescale divider */
 113 };
 114
 115 static const struct bus_speed_cfg std_cfg_table[] = {
 116         [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
 117         [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
 118         [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
 119 };
 120
 121 struct bcm_kona_i2c_dev {
 122         void *base;
 123         uint speed;
 124         const struct bus_speed_cfg *std_cfg;
 125 };
 126
 127 /* Keep these two defines in sync */
 128 #define DEF_SPD 100000
 129 #define DEF_SPD_ENUM BCM_SPD_100K
 130
 131 #define DEF_DEVICE(num) \
 132 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
 133
 134 static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
 135 #ifdef CONFIG_SYS_I2C_BASE0
 136         DEF_DEVICE(0),
 137 #endif
 138 #ifdef CONFIG_SYS_I2C_BASE1
 139         DEF_DEVICE(1),
 140 #endif
 141 #ifdef CONFIG_SYS_I2C_BASE2
 142         DEF_DEVICE(2),
 143 #endif
 144 #ifdef CONFIG_SYS_I2C_BASE3
 145         DEF_DEVICE(3),
 146 #endif
 147 #ifdef CONFIG_SYS_I2C_BASE4
 148         DEF_DEVICE(4),
 149 #endif
 150 #ifdef CONFIG_SYS_I2C_BASE5
 151         DEF_DEVICE(5),
 152 #endif
 153 };
 154
 155 #define I2C_M_TEN       0x0010  /* ten bit address */
 156 #define I2C_M_RD        0x0001  /* read data */
 157 #define I2C_M_NOSTART   0x4000  /* no restart between msgs */
 158
 159 struct kona_i2c_msg {
 160         uint16_t addr;
 161         uint16_t flags;
 162         uint16_t len;
 163         uint8_t *buf;
 164 };
 165
 166 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
 167                                           enum bcm_kona_cmd_t cmd)
 168 {
 169         debug("%s, %d\n", __func__, cmd);
 170
 171         switch (cmd) {
 172         case BCM_CMD_NOACTION:
 173                 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
 174                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 175                        dev->base + CS_OFFSET);
 176                 break;
 177
 178         case BCM_CMD_START:
 179                 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
 180                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 181                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 182                        dev->base + CS_OFFSET);
 183                 break;
 184
 185         case BCM_CMD_RESTART:
 186                 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
 187                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 188                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 189                        dev->base + CS_OFFSET);
 190                 break;
 191
 192         case BCM_CMD_STOP:
 193                 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
 194                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 195                        dev->base + CS_OFFSET);
 196                 break;
 197
 198         default:
 199                 printf("Unknown command %d\n", cmd);
 200         }
 201 }
 202
 203 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
 204 {
 205         writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
 206                dev->base + CLKEN_OFFSET);
 207 }
 208
 209 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
 210 {
 211         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
 212                dev->base + CLKEN_OFFSET);
 213 }
 214
 215 /* Wait until at least one of the mask bit(s) are set */
 216 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
 217                                           unsigned long time_left,
 218                                           uint32_t mask)
 219 {
 220         uint32_t status;
 221
 222         while (time_left) {
 223                 status = readl(dev->base + ISR_OFFSET);
 224
 225                 if ((status & ~ISR_RESERVED_MASK) == 0) {
 226                         debug("Bogus I2C interrupt 0x%x\n", status);
 227                         continue;
 228                 }
 229
 230                 /* Must flush the TX FIFO when NAK detected */
 231                 if (status & ISR_NOACK_MASK)
 232                         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 233                                dev->base + TXFCR_OFFSET);
 234
 235                 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
 236
 237                 if (status & mask) {
 238                         /* We are done since one of the mask bits are set */
 239                         return time_left;
 240                 }
 241                 udelay(WAIT_INT_CHK);
 242                 time_left -= WAIT_INT_CHK;
 243         }
 244         return 0;
 245 }
 246
 247 /* Send command to I2C bus */
 248 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
 249                                  enum bcm_kona_cmd_t cmd)
 250 {
 251         int rc = 0;
 252         unsigned long time_left = I2C_TIMEOUT;
 253
 254         /* Send the command */
 255         bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
 256
 257         /* Wait for transaction to finish or timeout */
 258         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 259
 260         if (!time_left) {
 261                 printf("controller timed out\n");
 262                 rc = -ETIMEDOUT;
 263         }
 264
 265         /* Clear command */
 266         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 267
 268         return rc;
 269 }
 270
 271 /* Read a single RX FIFO worth of data from the i2c bus */
 272 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
 273                                          uint8_t *buf, unsigned int len,
 274                                          unsigned int last_byte_nak)
 275 {
 276         unsigned long time_left = I2C_TIMEOUT;
 277
 278         /* Start the RX FIFO */
 279         writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
 280                (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
 281
 282         /* Wait for FIFO read to complete */
 283         time_left =
 284             wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
 285
 286         if (!time_left) {
 287                 printf("RX FIFO time out\n");
 288                 return -EREMOTEIO;
 289         }
 290
 291         /* Read data from FIFO */
 292         for (; len > 0; len--, buf++)
 293                 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
 294
 295         return 0;
 296 }
 297
 298 /* Read any amount of data using the RX FIFO from the i2c bus */
 299 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
 300                                   struct kona_i2c_msg *msg)
 301 {
 302         unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
 303         unsigned int last_byte_nak = 0;
 304         unsigned int bytes_read = 0;
 305         int rc;
 306
 307         uint8_t *tmp_buf = msg->buf;
 308
 309         while (bytes_read < msg->len) {
 310                 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
 311                         last_byte_nak = 1;      /* NAK last byte of transfer */
 312                         bytes_to_read = msg->len - bytes_read;
 313                 }
 314
 315                 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
 316                                                    last_byte_nak);
 317                 if (rc < 0)
 318                         return -EREMOTEIO;
 319
 320                 bytes_read += bytes_to_read;
 321                 tmp_buf += bytes_to_read;
 322         }
 323
 324         return 0;
 325 }
 326
 327 /* Write a single byte of data to the i2c bus */
 328 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
 329                                    unsigned int nak_expected)
 330 {
 331         unsigned long time_left = I2C_TIMEOUT;
 332         unsigned int nak_received;
 333
 334         /* Clear pending session done interrupt */
 335         writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
 336
 337         /* Send one byte of data */
 338         writel(data, dev->base + DAT_OFFSET);
 339
 340         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 341
 342         if (!time_left) {
 343                 debug("controller timed out\n");
 344                 return -ETIMEDOUT;
 345         }
 346
 347         nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
 348
 349         if (nak_received ^ nak_expected) {
 350                 debug("unexpected NAK/ACK\n");
 351                 return -EREMOTEIO;
 352         }
 353
 354         return 0;
 355 }
 356
 357 /* Write a single TX FIFO worth of data to the i2c bus */
 358 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
 359                                           uint8_t *buf, unsigned int len)
 360 {
 361         int k;
 362         unsigned long time_left = I2C_TIMEOUT;
 363         unsigned int fifo_status;
 364
 365         /* Write data into FIFO */
 366         for (k = 0; k < len; k++)
 367                 writel(buf[k], (dev->base + DAT_OFFSET));
 368
 369         /* Wait for FIFO to empty */
 370         do {
 371                 time_left =
 372                     wait_for_int_timeout(dev, time_left,
 373                                          (IER_FIFO_INT_EN_MASK |
 374                                           IER_NOACK_EN_MASK));
 375                 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
 376         } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
 377
 378         /* Check if there was a NAK */
 379         if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
 380                 printf("unexpected NAK\n");
 381                 return -EREMOTEIO;
 382         }
 383
 384         /* Check if a timeout occured */
 385         if (!time_left) {
 386                 printf("completion timed out\n");
 387                 return -EREMOTEIO;
 388         }
 389
 390         return 0;
 391 }
 392
 393 /* Write any amount of data using TX FIFO to the i2c bus */
 394 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
 395                                    struct kona_i2c_msg *msg)
 396 {
 397         unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
 398         unsigned int bytes_written = 0;
 399         int rc;
 400
 401         uint8_t *tmp_buf = msg->buf;
 402
 403         while (bytes_written < msg->len) {
 404                 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
 405                         bytes_to_write = msg->len - bytes_written;
 406
 407                 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
 408                                                     bytes_to_write);
 409                 if (rc < 0)
 410                         return -EREMOTEIO;
 411
 412                 bytes_written += bytes_to_write;
 413                 tmp_buf += bytes_to_write;
 414         }
 415
 416         return 0;
 417 }
 418
 419 /* Send i2c address */
 420 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
 421                                 struct kona_i2c_msg *msg)
 422 {
 423         unsigned char addr;
 424
 425         if (msg->flags & I2C_M_TEN) {
 426                 /* First byte is 11110XX0 where XX is upper 2 bits */
 427                 addr = 0xf0 | ((msg->addr & 0x300) >> 7);
 428                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 429                         return -EREMOTEIO;
 430
 431                 /* Second byte is the remaining 8 bits */
 432                 addr = msg->addr & 0xff;
 433                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 434                         return -EREMOTEIO;
 435
 436                 if (msg->flags & I2C_M_RD) {
 437                         /* For read, send restart command */
 438                         if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
 439                                 return -EREMOTEIO;
 440
 441                         /* Then re-send the first byte with the read bit set */
 442                         addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
 443                         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 444                                 return -EREMOTEIO;
 445                 }
 446         } else {
 447                 addr = msg->addr << 1;
 448
 449                 if (msg->flags & I2C_M_RD)
 450                         addr |= 1;
 451
 452                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 453                         return -EREMOTEIO;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
 460 {
 461         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
 462                dev->base + CLKEN_OFFSET);
 463 }
 464
 465 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
 466 {
 467         writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
 468                dev->base + HSTIM_OFFSET);
 469
 470         writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
 471                (dev->std_cfg->time_p << TIM_P_SHIFT) |
 472                (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
 473                (dev->std_cfg->time_div << TIM_DIV_SHIFT),
 474                dev->base + TIM_OFFSET);
 475
 476         writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
 477                (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
 478                CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
 479 }
 480
 481 /* Master transfer function */
 482 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
 483                              struct kona_i2c_msg msgs[], int num)
 484 {
 485         struct kona_i2c_msg *pmsg;
 486         int rc = 0;
 487         int i;
 488
 489         /* Enable pad output */
 490         writel(0, dev->base + PADCTL_OFFSET);
 491
 492         /* Enable internal clocks */
 493         bcm_kona_i2c_enable_clock(dev);
 494
 495         /* Send start command */
 496         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
 497         if (rc < 0) {
 498                 printf("Start command failed rc = %d\n", rc);
 499                 goto xfer_disable_pad;
 500         }
 501
 502         /* Loop through all messages */
 503         for (i = 0; i < num; i++) {
 504                 pmsg = &msgs[i];
 505
 506                 /* Send restart for subsequent messages */
 507                 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
 508                         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
 509                         if (rc < 0) {
 510                                 printf("restart cmd failed rc = %d\n", rc);
 511                                 goto xfer_send_stop;
 512                         }
 513                 }
 514
 515                 /* Send slave address */
 516                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 517                         rc = bcm_kona_i2c_do_addr(dev, pmsg);
 518                         if (rc < 0) {
 519                                 debug("NAK from addr %2.2x msg#%d rc = %d\n",
 520                                       pmsg->addr, i, rc);
 521                                 goto xfer_send_stop;
 522                         }
 523                 }
 524
 525                 /* Perform data transfer */
 526                 if (pmsg->flags & I2C_M_RD) {
 527                         rc = bcm_kona_i2c_read_fifo(dev, pmsg);
 528                         if (rc < 0) {
 529                                 printf("read failure\n");
 530                                 goto xfer_send_stop;
 531                         }
 532                 } else {
 533                         rc = bcm_kona_i2c_write_fifo(dev, pmsg);
 534                         if (rc < 0) {
 535                                 printf("write failure");
 536                                 goto xfer_send_stop;
 537                         }
 538                 }
 539         }
 540
 541         rc = num;
 542
 543 xfer_send_stop:
 544         /* Send a STOP command */
 545         bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
 546
 547 xfer_disable_pad:
 548         /* Disable pad output */
 549         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 550
 551         /* Stop internal clock */
 552         bcm_kona_i2c_disable_clock(dev);
 553
 554         return rc;
 555 }
 556
 557 static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
 558                                           uint speed)
 559 {
 560         switch (speed) {
 561         case 100000:
 562                 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
 563                 break;
 564         case 400000:
 565                 dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
 566                 break;
 567         case 1000000:
 568                 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
 569                 break;
 570         default:
 571                 printf("%d hz bus speed not supported\n", speed);
 572                 return -EINVAL;
 573         }
 574         dev->speed = speed;
 575         return 0;
 576 }
 577
 578 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
 579 {
 580         /* Parse bus speed */
 581         bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
 582
 583         /* Enable internal clocks */
 584         bcm_kona_i2c_enable_clock(dev);
 585
 586         /* Configure internal dividers */
 587         bcm_kona_i2c_config_timing(dev);
 588
 589         /* Disable timeout */
 590         writel(0, dev->base + TOUT_OFFSET);
 591
 592         /* Enable autosense */
 593         bcm_kona_i2c_enable_autosense(dev);
 594
 595         /* Enable TX FIFO */
 596         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 597                dev->base + TXFCR_OFFSET);
 598
 599         /* Mask all interrupts */
 600         writel(0, dev->base + IER_OFFSET);
 601
 602         /* Clear all pending interrupts */
 603         writel(ISR_CMDBUSY_MASK |
 604                ISR_READ_COMPLETE_MASK |
 605                ISR_SES_DONE_MASK |
 606                ISR_ERR_MASK |
 607                ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
 608
 609         /* Enable the controller but leave it idle */
 610         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 611
 612         /* Disable pad output */
 613         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 614 }
 615
 616 /*
 617  * uboot layer
 618  */
 619 struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
 620 {
 621         return &g_i2c_devs[adap->hwadapnr];
 622 }
 623
 624 static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 625 {
 626         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 627
 628         if (clk_bsc_enable(dev->base))
 629                 return;
 630
 631         bcm_kona_i2c_init(dev);
 632 }
 633
 634 static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 635                          int alen, uchar *buffer, int len)
 636 {
 637         /* msg[0] writes the addr, msg[1] reads the data */
 638         struct kona_i2c_msg msg[2];
 639         unsigned char msgbuf0[64];
 640         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 641
 642         msg[0].addr = chip;
 643         msg[0].flags = 0;
 644         msg[0].len = 1;
 645         msg[0].buf = msgbuf0;   /* msgbuf0 contains incrementing reg addr */
 646
 647         msg[1].addr = chip;
 648         msg[1].flags = I2C_M_RD;
 649         /* msg[1].buf dest ptr increments each read */
 650
 651         msgbuf0[0] = (unsigned char)addr;
 652         msg[1].buf = buffer;
 653         msg[1].len = len;
 654         if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
 655                 /* Sending 2 i2c messages */
 656                 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 657                 debug("I2C read: I/O error\n");
 658                 return -EIO;
 659         }
 660         return 0;
 661 }
 662
 663 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 664                           int alen, uchar *buffer, int len)
 665 {
 666         struct kona_i2c_msg msg[1];
 667         unsigned char msgbuf0[64];
 668         unsigned int i;
 669         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 670
 671         msg[0].addr = chip;
 672         msg[0].flags = 0;
 673         msg[0].len = 2;         /* addr byte plus data */
 674         msg[0].buf = msgbuf0;
 675
 676         for (i = 0; i < len; i++) {
 677                 msgbuf0[0] = addr++;
 678                 msgbuf0[1] = buffer[i];
 679                 if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
 680                         kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 681                         debug("I2C write: I/O error\n");
 682                         return -EIO;
 683                 }
 684         }
 685         return 0;
 686 }
 687
 688 static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
 689 {
 690         uchar tmp;
 691
 692         /*
 693          * read addr 0x0 of the given chip.
 694          */
 695         return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
 696 }
 697
 698 static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 699 {
 700         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 701         return bcm_kona_i2c_assign_bus_speed(dev, speed);
 702 }
 703
 704 /*
 705  * Register kona i2c adapters. Keep the order below so
 706  * that the bus number matches the adapter number.
 707  */
 708 #define DEF_ADAPTER(num) \
 709 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
 710                          kona_i2c_read, kona_i2c_write, \
 711                          kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
 712
 713 #ifdef CONFIG_SYS_I2C_BASE0
 714         DEF_ADAPTER(0)
 715 #endif
 716 #ifdef CONFIG_SYS_I2C_BASE1
 717         DEF_ADAPTER(1)
 718 #endif
 719 #ifdef CONFIG_SYS_I2C_BASE2
 720         DEF_ADAPTER(2)
 721 #endif
 722 #ifdef CONFIG_SYS_I2C_BASE3
 723         DEF_ADAPTER(3)
 724 #endif
 725 #ifdef CONFIG_SYS_I2C_BASE4
 726         DEF_ADAPTER(4)
 727 #endif
 728 #ifdef CONFIG_SYS_I2C_BASE5
 729         DEF_ADAPTER(5)
 730 #endif