git.sur5r.net Git - u-boot/blob - drivers/i2c/kona_i2c.c

   1 /*
   2  * Copyright 2013 Broadcom Corporation.
   3  *
   4  * SPDX-License-Identifier:      GPL-2.0+
   5  *
   6  * NOTE: This driver should be converted to driver model before June 2017.
   7  * Please see doc/driver-model/i2c-howto.txt for instructions.
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <linux/errno.h>
  13 #include <asm/arch/sysmap.h>
  14 #include <asm/kona-common/clk.h>
  15 #include <i2c.h>
  16
  17 /* Hardware register offsets and field defintions */
  18 #define CS_OFFSET                               0x00000020
  19 #define CS_ACK_SHIFT                            3
  20 #define CS_ACK_MASK                             0x00000008
  21 #define CS_ACK_CMD_GEN_START                    0x00000000
  22 #define CS_ACK_CMD_GEN_RESTART                  0x00000001
  23 #define CS_CMD_SHIFT                            1
  24 #define CS_CMD_CMD_NO_ACTION                    0x00000000
  25 #define CS_CMD_CMD_START_RESTART                0x00000001
  26 #define CS_CMD_CMD_STOP                         0x00000002
  27 #define CS_EN_SHIFT                             0
  28 #define CS_EN_CMD_ENABLE_BSC                    0x00000001
  29
  30 #define TIM_OFFSET                              0x00000024
  31 #define TIM_PRESCALE_SHIFT                      6
  32 #define TIM_P_SHIFT                             3
  33 #define TIM_NO_DIV_SHIFT                        2
  34 #define TIM_DIV_SHIFT                           0
  35
  36 #define DAT_OFFSET                              0x00000028
  37
  38 #define TOUT_OFFSET                             0x0000002c
  39
  40 #define TXFCR_OFFSET                            0x0000003c
  41 #define TXFCR_FIFO_FLUSH_MASK                   0x00000080
  42 #define TXFCR_FIFO_EN_MASK                      0x00000040
  43
  44 #define IER_OFFSET                              0x00000044
  45 #define IER_READ_COMPLETE_INT_MASK              0x00000010
  46 #define IER_I2C_INT_EN_MASK                     0x00000008
  47 #define IER_FIFO_INT_EN_MASK                    0x00000002
  48 #define IER_NOACK_EN_MASK                       0x00000001
  49
  50 #define ISR_OFFSET                              0x00000048
  51 #define ISR_RESERVED_MASK                       0xffffff60
  52 #define ISR_CMDBUSY_MASK                        0x00000080
  53 #define ISR_READ_COMPLETE_MASK                  0x00000010
  54 #define ISR_SES_DONE_MASK                       0x00000008
  55 #define ISR_ERR_MASK                            0x00000004
  56 #define ISR_TXFIFOEMPTY_MASK                    0x00000002
  57 #define ISR_NOACK_MASK                          0x00000001
  58
  59 #define CLKEN_OFFSET                            0x0000004c
  60 #define CLKEN_AUTOSENSE_OFF_MASK                0x00000080
  61 #define CLKEN_M_SHIFT                           4
  62 #define CLKEN_N_SHIFT                           1
  63 #define CLKEN_CLKEN_MASK                        0x00000001
  64
  65 #define FIFO_STATUS_OFFSET                      0x00000054
  66 #define FIFO_STATUS_RXFIFO_EMPTY_MASK           0x00000004
  67 #define FIFO_STATUS_TXFIFO_EMPTY_MASK           0x00000010
  68
  69 #define HSTIM_OFFSET                            0x00000058
  70 #define HSTIM_HS_MODE_MASK                      0x00008000
  71 #define HSTIM_HS_HOLD_SHIFT                     10
  72 #define HSTIM_HS_HIGH_PHASE_SHIFT               5
  73 #define HSTIM_HS_SETUP_SHIFT                    0
  74
  75 #define PADCTL_OFFSET                           0x0000005c
  76 #define PADCTL_PAD_OUT_EN_MASK                  0x00000004
  77
  78 #define RXFCR_OFFSET                            0x00000068
  79 #define RXFCR_NACK_EN_SHIFT                     7
  80 #define RXFCR_READ_COUNT_SHIFT                  0
  81 #define RXFIFORDOUT_OFFSET                      0x0000006c
  82
  83 /* Locally used constants */
  84 #define MAX_RX_FIFO_SIZE                64U     /* bytes */
  85 #define MAX_TX_FIFO_SIZE                64U     /* bytes */
  86
  87 #define I2C_TIMEOUT                     100000  /* usecs */
  88
  89 #define WAIT_INT_CHK                    100     /* usecs */
  90 #if I2C_TIMEOUT % WAIT_INT_CHK
  91 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  92 #endif
  93
  94 /* Operations that can be commanded to the controller */
  95 enum bcm_kona_cmd_t {
  96         BCM_CMD_NOACTION = 0,
  97         BCM_CMD_START,
  98         BCM_CMD_RESTART,
  99         BCM_CMD_STOP,
 100 };
 101
 102 enum bus_speed_index {
 103         BCM_SPD_100K = 0,
 104         BCM_SPD_400K,
 105         BCM_SPD_1MHZ,
 106 };
 107
 108 /* Internal divider settings for standard mode, fast mode and fast mode plus */
 109 struct bus_speed_cfg {
 110         uint8_t time_m;         /* Number of cycles for setup time */
 111         uint8_t time_n;         /* Number of cycles for hold time */
 112         uint8_t prescale;       /* Prescale divider */
 113         uint8_t time_p;         /* Timing coefficient */
 114         uint8_t no_div;         /* Disable clock divider */
 115         uint8_t time_div;       /* Post-prescale divider */
 116 };
 117
 118 static const struct bus_speed_cfg std_cfg_table[] = {
 119         [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
 120         [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
 121         [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
 122 };
 123
 124 struct bcm_kona_i2c_dev {
 125         void *base;
 126         uint speed;
 127         const struct bus_speed_cfg *std_cfg;
 128 };
 129
 130 /* Keep these two defines in sync */
 131 #define DEF_SPD 100000
 132 #define DEF_SPD_ENUM BCM_SPD_100K
 133
 134 #define DEF_DEVICE(num) \
 135 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
 136
 137 static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
 138 #ifdef CONFIG_SYS_I2C_BASE0
 139         DEF_DEVICE(0),
 140 #endif
 141 #ifdef CONFIG_SYS_I2C_BASE1
 142         DEF_DEVICE(1),
 143 #endif
 144 #ifdef CONFIG_SYS_I2C_BASE2
 145         DEF_DEVICE(2),
 146 #endif
 147 #ifdef CONFIG_SYS_I2C_BASE3
 148         DEF_DEVICE(3),
 149 #endif
 150 #ifdef CONFIG_SYS_I2C_BASE4
 151         DEF_DEVICE(4),
 152 #endif
 153 #ifdef CONFIG_SYS_I2C_BASE5
 154         DEF_DEVICE(5),
 155 #endif
 156 };
 157
 158 #define I2C_M_TEN       0x0010  /* ten bit address */
 159 #define I2C_M_RD        0x0001  /* read data */
 160 #define I2C_M_NOSTART   0x4000  /* no restart between msgs */
 161
 162 struct kona_i2c_msg {
 163         uint16_t addr;
 164         uint16_t flags;
 165         uint16_t len;
 166         uint8_t *buf;
 167 };
 168
 169 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
 170                                           enum bcm_kona_cmd_t cmd)
 171 {
 172         debug("%s, %d\n", __func__, cmd);
 173
 174         switch (cmd) {
 175         case BCM_CMD_NOACTION:
 176                 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
 177                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 178                        dev->base + CS_OFFSET);
 179                 break;
 180
 181         case BCM_CMD_START:
 182                 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
 183                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 184                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 185                        dev->base + CS_OFFSET);
 186                 break;
 187
 188         case BCM_CMD_RESTART:
 189                 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
 190                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 191                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 192                        dev->base + CS_OFFSET);
 193                 break;
 194
 195         case BCM_CMD_STOP:
 196                 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
 197                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 198                        dev->base + CS_OFFSET);
 199                 break;
 200
 201         default:
 202                 printf("Unknown command %d\n", cmd);
 203         }
 204 }
 205
 206 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
 207 {
 208         writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
 209                dev->base + CLKEN_OFFSET);
 210 }
 211
 212 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
 213 {
 214         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
 215                dev->base + CLKEN_OFFSET);
 216 }
 217
 218 /* Wait until at least one of the mask bit(s) are set */
 219 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
 220                                           unsigned long time_left,
 221                                           uint32_t mask)
 222 {
 223         uint32_t status;
 224
 225         while (time_left) {
 226                 status = readl(dev->base + ISR_OFFSET);
 227
 228                 if ((status & ~ISR_RESERVED_MASK) == 0) {
 229                         debug("Bogus I2C interrupt 0x%x\n", status);
 230                         continue;
 231                 }
 232
 233                 /* Must flush the TX FIFO when NAK detected */
 234                 if (status & ISR_NOACK_MASK)
 235                         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 236                                dev->base + TXFCR_OFFSET);
 237
 238                 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
 239
 240                 if (status & mask) {
 241                         /* We are done since one of the mask bits are set */
 242                         return time_left;
 243                 }
 244                 udelay(WAIT_INT_CHK);
 245                 time_left -= WAIT_INT_CHK;
 246         }
 247         return 0;
 248 }
 249
 250 /* Send command to I2C bus */
 251 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
 252                                  enum bcm_kona_cmd_t cmd)
 253 {
 254         int rc = 0;
 255         unsigned long time_left = I2C_TIMEOUT;
 256
 257         /* Send the command */
 258         bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
 259
 260         /* Wait for transaction to finish or timeout */
 261         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 262
 263         if (!time_left) {
 264                 printf("controller timed out\n");
 265                 rc = -ETIMEDOUT;
 266         }
 267
 268         /* Clear command */
 269         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 270
 271         return rc;
 272 }
 273
 274 /* Read a single RX FIFO worth of data from the i2c bus */
 275 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
 276                                          uint8_t *buf, unsigned int len,
 277                                          unsigned int last_byte_nak)
 278 {
 279         unsigned long time_left = I2C_TIMEOUT;
 280
 281         /* Start the RX FIFO */
 282         writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
 283                (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
 284
 285         /* Wait for FIFO read to complete */
 286         time_left =
 287             wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
 288
 289         if (!time_left) {
 290                 printf("RX FIFO time out\n");
 291                 return -EREMOTEIO;
 292         }
 293
 294         /* Read data from FIFO */
 295         for (; len > 0; len--, buf++)
 296                 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
 297
 298         return 0;
 299 }
 300
 301 /* Read any amount of data using the RX FIFO from the i2c bus */
 302 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
 303                                   struct kona_i2c_msg *msg)
 304 {
 305         unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
 306         unsigned int last_byte_nak = 0;
 307         unsigned int bytes_read = 0;
 308         int rc;
 309
 310         uint8_t *tmp_buf = msg->buf;
 311
 312         while (bytes_read < msg->len) {
 313                 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
 314                         last_byte_nak = 1;      /* NAK last byte of transfer */
 315                         bytes_to_read = msg->len - bytes_read;
 316                 }
 317
 318                 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
 319                                                    last_byte_nak);
 320                 if (rc < 0)
 321                         return -EREMOTEIO;
 322
 323                 bytes_read += bytes_to_read;
 324                 tmp_buf += bytes_to_read;
 325         }
 326
 327         return 0;
 328 }
 329
 330 /* Write a single byte of data to the i2c bus */
 331 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
 332                                    unsigned int nak_expected)
 333 {
 334         unsigned long time_left = I2C_TIMEOUT;
 335         unsigned int nak_received;
 336
 337         /* Clear pending session done interrupt */
 338         writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
 339
 340         /* Send one byte of data */
 341         writel(data, dev->base + DAT_OFFSET);
 342
 343         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 344
 345         if (!time_left) {
 346                 debug("controller timed out\n");
 347                 return -ETIMEDOUT;
 348         }
 349
 350         nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
 351
 352         if (nak_received ^ nak_expected) {
 353                 debug("unexpected NAK/ACK\n");
 354                 return -EREMOTEIO;
 355         }
 356
 357         return 0;
 358 }
 359
 360 /* Write a single TX FIFO worth of data to the i2c bus */
 361 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
 362                                           uint8_t *buf, unsigned int len)
 363 {
 364         int k;
 365         unsigned long time_left = I2C_TIMEOUT;
 366         unsigned int fifo_status;
 367
 368         /* Write data into FIFO */
 369         for (k = 0; k < len; k++)
 370                 writel(buf[k], (dev->base + DAT_OFFSET));
 371
 372         /* Wait for FIFO to empty */
 373         do {
 374                 time_left =
 375                     wait_for_int_timeout(dev, time_left,
 376                                          (IER_FIFO_INT_EN_MASK |
 377                                           IER_NOACK_EN_MASK));
 378                 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
 379         } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
 380
 381         /* Check if there was a NAK */
 382         if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
 383                 printf("unexpected NAK\n");
 384                 return -EREMOTEIO;
 385         }
 386
 387         /* Check if a timeout occurred */
 388         if (!time_left) {
 389                 printf("completion timed out\n");
 390                 return -EREMOTEIO;
 391         }
 392
 393         return 0;
 394 }
 395
 396 /* Write any amount of data using TX FIFO to the i2c bus */
 397 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
 398                                    struct kona_i2c_msg *msg)
 399 {
 400         unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
 401         unsigned int bytes_written = 0;
 402         int rc;
 403
 404         uint8_t *tmp_buf = msg->buf;
 405
 406         while (bytes_written < msg->len) {
 407                 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
 408                         bytes_to_write = msg->len - bytes_written;
 409
 410                 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
 411                                                     bytes_to_write);
 412                 if (rc < 0)
 413                         return -EREMOTEIO;
 414
 415                 bytes_written += bytes_to_write;
 416                 tmp_buf += bytes_to_write;
 417         }
 418
 419         return 0;
 420 }
 421
 422 /* Send i2c address */
 423 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
 424                                 struct kona_i2c_msg *msg)
 425 {
 426         unsigned char addr;
 427
 428         if (msg->flags & I2C_M_TEN) {
 429                 /* First byte is 11110XX0 where XX is upper 2 bits */
 430                 addr = 0xf0 | ((msg->addr & 0x300) >> 7);
 431                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 432                         return -EREMOTEIO;
 433
 434                 /* Second byte is the remaining 8 bits */
 435                 addr = msg->addr & 0xff;
 436                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 437                         return -EREMOTEIO;
 438
 439                 if (msg->flags & I2C_M_RD) {
 440                         /* For read, send restart command */
 441                         if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
 442                                 return -EREMOTEIO;
 443
 444                         /* Then re-send the first byte with the read bit set */
 445                         addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
 446                         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 447                                 return -EREMOTEIO;
 448                 }
 449         } else {
 450                 addr = msg->addr << 1;
 451
 452                 if (msg->flags & I2C_M_RD)
 453                         addr |= 1;
 454
 455                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 456                         return -EREMOTEIO;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
 463 {
 464         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
 465                dev->base + CLKEN_OFFSET);
 466 }
 467
 468 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
 469 {
 470         writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
 471                dev->base + HSTIM_OFFSET);
 472
 473         writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
 474                (dev->std_cfg->time_p << TIM_P_SHIFT) |
 475                (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
 476                (dev->std_cfg->time_div << TIM_DIV_SHIFT),
 477                dev->base + TIM_OFFSET);
 478
 479         writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
 480                (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
 481                CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
 482 }
 483
 484 /* Master transfer function */
 485 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
 486                              struct kona_i2c_msg msgs[], int num)
 487 {
 488         struct kona_i2c_msg *pmsg;
 489         int rc = 0;
 490         int i;
 491
 492         /* Enable pad output */
 493         writel(0, dev->base + PADCTL_OFFSET);
 494
 495         /* Enable internal clocks */
 496         bcm_kona_i2c_enable_clock(dev);
 497
 498         /* Send start command */
 499         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
 500         if (rc < 0) {
 501                 printf("Start command failed rc = %d\n", rc);
 502                 goto xfer_disable_pad;
 503         }
 504
 505         /* Loop through all messages */
 506         for (i = 0; i < num; i++) {
 507                 pmsg = &msgs[i];
 508
 509                 /* Send restart for subsequent messages */
 510                 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
 511                         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
 512                         if (rc < 0) {
 513                                 printf("restart cmd failed rc = %d\n", rc);
 514                                 goto xfer_send_stop;
 515                         }
 516                 }
 517
 518                 /* Send slave address */
 519                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 520                         rc = bcm_kona_i2c_do_addr(dev, pmsg);
 521                         if (rc < 0) {
 522                                 debug("NAK from addr %2.2x msg#%d rc = %d\n",
 523                                       pmsg->addr, i, rc);
 524                                 goto xfer_send_stop;
 525                         }
 526                 }
 527
 528                 /* Perform data transfer */
 529                 if (pmsg->flags & I2C_M_RD) {
 530                         rc = bcm_kona_i2c_read_fifo(dev, pmsg);
 531                         if (rc < 0) {
 532                                 printf("read failure\n");
 533                                 goto xfer_send_stop;
 534                         }
 535                 } else {
 536                         rc = bcm_kona_i2c_write_fifo(dev, pmsg);
 537                         if (rc < 0) {
 538                                 printf("write failure");
 539                                 goto xfer_send_stop;
 540                         }
 541                 }
 542         }
 543
 544         rc = num;
 545
 546 xfer_send_stop:
 547         /* Send a STOP command */
 548         bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
 549
 550 xfer_disable_pad:
 551         /* Disable pad output */
 552         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 553
 554         /* Stop internal clock */
 555         bcm_kona_i2c_disable_clock(dev);
 556
 557         return rc;
 558 }
 559
 560 static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
 561                                           uint speed)
 562 {
 563         switch (speed) {
 564         case 100000:
 565                 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
 566                 break;
 567         case 400000:
 568                 dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
 569                 break;
 570         case 1000000:
 571                 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
 572                 break;
 573         default:
 574                 printf("%d hz bus speed not supported\n", speed);
 575                 return -EINVAL;
 576         }
 577         dev->speed = speed;
 578         return 0;
 579 }
 580
 581 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
 582 {
 583         /* Parse bus speed */
 584         bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
 585
 586         /* Enable internal clocks */
 587         bcm_kona_i2c_enable_clock(dev);
 588
 589         /* Configure internal dividers */
 590         bcm_kona_i2c_config_timing(dev);
 591
 592         /* Disable timeout */
 593         writel(0, dev->base + TOUT_OFFSET);
 594
 595         /* Enable autosense */
 596         bcm_kona_i2c_enable_autosense(dev);
 597
 598         /* Enable TX FIFO */
 599         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 600                dev->base + TXFCR_OFFSET);
 601
 602         /* Mask all interrupts */
 603         writel(0, dev->base + IER_OFFSET);
 604
 605         /* Clear all pending interrupts */
 606         writel(ISR_CMDBUSY_MASK |
 607                ISR_READ_COMPLETE_MASK |
 608                ISR_SES_DONE_MASK |
 609                ISR_ERR_MASK |
 610                ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
 611
 612         /* Enable the controller but leave it idle */
 613         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 614
 615         /* Disable pad output */
 616         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 617 }
 618
 619 /*
 620  * uboot layer
 621  */
 622 struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
 623 {
 624         return &g_i2c_devs[adap->hwadapnr];
 625 }
 626
 627 static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 628 {
 629         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 630
 631         if (clk_bsc_enable(dev->base))
 632                 return;
 633
 634         bcm_kona_i2c_init(dev);
 635 }
 636
 637 static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 638                          int alen, uchar *buffer, int len)
 639 {
 640         /* msg[0] writes the addr, msg[1] reads the data */
 641         struct kona_i2c_msg msg[2];
 642         unsigned char msgbuf0[64];
 643         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 644
 645         msg[0].addr = chip;
 646         msg[0].flags = 0;
 647         msg[0].len = 1;
 648         msg[0].buf = msgbuf0;   /* msgbuf0 contains incrementing reg addr */
 649
 650         msg[1].addr = chip;
 651         msg[1].flags = I2C_M_RD;
 652         /* msg[1].buf dest ptr increments each read */
 653
 654         msgbuf0[0] = (unsigned char)addr;
 655         msg[1].buf = buffer;
 656         msg[1].len = len;
 657         if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
 658                 /* Sending 2 i2c messages */
 659                 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 660                 debug("I2C read: I/O error\n");
 661                 return -EIO;
 662         }
 663         return 0;
 664 }
 665
 666 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 667                           int alen, uchar *buffer, int len)
 668 {
 669         struct kona_i2c_msg msg[1];
 670         unsigned char msgbuf0[64];
 671         unsigned int i;
 672         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 673
 674         msg[0].addr = chip;
 675         msg[0].flags = 0;
 676         msg[0].len = 2;         /* addr byte plus data */
 677         msg[0].buf = msgbuf0;
 678
 679         for (i = 0; i < len; i++) {
 680                 msgbuf0[0] = addr++;
 681                 msgbuf0[1] = buffer[i];
 682                 if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
 683                         kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 684                         debug("I2C write: I/O error\n");
 685                         return -EIO;
 686                 }
 687         }
 688         return 0;
 689 }
 690
 691 static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
 692 {
 693         uchar tmp;
 694
 695         /*
 696          * read addr 0x0 of the given chip.
 697          */
 698         return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
 699 }
 700
 701 static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 702 {
 703         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 704         return bcm_kona_i2c_assign_bus_speed(dev, speed);
 705 }
 706
 707 /*
 708  * Register kona i2c adapters. Keep the order below so
 709  * that the bus number matches the adapter number.
 710  */
 711 #define DEF_ADAPTER(num) \
 712 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
 713                          kona_i2c_read, kona_i2c_write, \
 714                          kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
 715
 716 #ifdef CONFIG_SYS_I2C_BASE0
 717         DEF_ADAPTER(0)
 718 #endif
 719 #ifdef CONFIG_SYS_I2C_BASE1
 720         DEF_ADAPTER(1)
 721 #endif
 722 #ifdef CONFIG_SYS_I2C_BASE2
 723         DEF_ADAPTER(2)
 724 #endif
 725 #ifdef CONFIG_SYS_I2C_BASE3
 726         DEF_ADAPTER(3)
 727 #endif
 728 #ifdef CONFIG_SYS_I2C_BASE4
 729         DEF_ADAPTER(4)
 730 #endif
 731 #ifdef CONFIG_SYS_I2C_BASE5
 732         DEF_ADAPTER(5)
 733 #endif