2 * Driver for the TWSI (i2c) controller found on the Marvell
3 * orion5x and kirkwood SoC families.
5 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
6 * Copyright (c) 2010 Albert Aribaud.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
15 #include <linux/compat.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
28 #if defined(CONFIG_ORION5X)
29 #include <asm/arch/orion5x.h>
30 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
31 #include <asm/arch/soc.h>
32 #elif defined(CONFIG_ARCH_SUNXI)
33 #include <asm/arch/i2c.h>
35 #error Driver mvtwsi not supported by SoC or board
37 #endif /* CONFIG_DM_I2C */
40 * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
43 #if defined(CONFIG_DM_I2C) && defined(CONFIG_ARCH_SUNXI)
44 #include <asm/arch/i2c.h>
48 * TWSI register structure
51 #ifdef CONFIG_ARCH_SUNXI
53 struct mvtwsi_registers {
65 struct mvtwsi_registers {
70 u32 status; /* When reading */
71 u32 baudrate; /* When writing */
81 struct mvtwsi_i2c_dev {
82 /* TWSI Register base for the device */
83 struct mvtwsi_registers *base;
84 /* Number of the device (determined from cell-index property) */
86 /* The I2C slave address for the device */
88 /* The configured I2C speed in Hz */
90 /* The current length of a clock period (depending on speed) */
93 #endif /* CONFIG_DM_I2C */
96 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
99 enum mvtwsi_ctrl_register_fields {
100 /* Acknowledge bit */
101 MVTWSI_CONTROL_ACK = 0x00000004,
103 MVTWSI_CONTROL_IFLG = 0x00000008,
105 MVTWSI_CONTROL_STOP = 0x00000010,
107 MVTWSI_CONTROL_START = 0x00000020,
109 MVTWSI_CONTROL_TWSIEN = 0x00000040,
110 /* Interrupt enable */
111 MVTWSI_CONTROL_INTEN = 0x00000080,
115 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
116 * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
119 #ifdef CONFIG_SUNXI_GEN_SUN6I
120 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
122 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
126 * enum mvstwsi_status_values - Possible values of I2C controller's status
129 * Only those statuses expected in normal master operation on
130 * non-10-bit-address devices are specified.
132 * Every status that's unexpected during normal operation (bus errors,
133 * arbitration losses, missing ACKs...) is passed back to the caller as an error
136 enum mvstwsi_status_values {
137 /* START condition transmitted */
138 MVTWSI_STATUS_START = 0x08,
139 /* Repeated START condition transmitted */
140 MVTWSI_STATUS_REPEATED_START = 0x10,
141 /* Address + write bit transmitted, ACK received */
142 MVTWSI_STATUS_ADDR_W_ACK = 0x18,
143 /* Data transmitted, ACK received */
144 MVTWSI_STATUS_DATA_W_ACK = 0x28,
145 /* Address + read bit transmitted, ACK received */
146 MVTWSI_STATUS_ADDR_R_ACK = 0x40,
147 /* Address + read bit transmitted, ACK not received */
148 MVTWSI_STATUS_ADDR_R_NAK = 0x48,
149 /* Data received, ACK transmitted */
150 MVTWSI_STATUS_DATA_R_ACK = 0x50,
151 /* Data received, ACK not transmitted */
152 MVTWSI_STATUS_DATA_R_NAK = 0x58,
153 /* No relevant status */
154 MVTWSI_STATUS_IDLE = 0xF8,
158 * enum mvstwsi_ack_flags - Determine whether a read byte should be
159 * acknowledged or not.
161 enum mvtwsi_ack_flags {
162 /* Send NAK after received byte */
164 /* Send ACK after received byte */
169 * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
171 * @speed: The speed in Hz to calculate the clock cycle duration for.
172 * @return The duration of a clock cycle in ns.
174 inline uint calc_tick(uint speed)
176 /* One tick = the duration of a period at the specified speed in ns (we
177 * add 100 ns to be on the safe side) */
178 return (1000000000u / speed) + 100;
181 #ifndef CONFIG_DM_I2C
184 * twsi_get_base() - Get controller register base for specified adapter
186 * @adap: Adapter to get the register base for.
187 * @return Register base for the specified adapter.
189 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
191 switch (adap->hwadapnr) {
192 #ifdef CONFIG_I2C_MVTWSI_BASE0
194 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
196 #ifdef CONFIG_I2C_MVTWSI_BASE1
198 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
200 #ifdef CONFIG_I2C_MVTWSI_BASE2
202 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
204 #ifdef CONFIG_I2C_MVTWSI_BASE3
206 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
208 #ifdef CONFIG_I2C_MVTWSI_BASE4
210 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
212 #ifdef CONFIG_I2C_MVTWSI_BASE5
214 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
217 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
226 * enum mvtwsi_error_class - types of I2C errors
228 enum mvtwsi_error_class {
229 /* The controller returned a different status than expected */
230 MVTWSI_ERROR_WRONG_STATUS = 0x01,
231 /* The controller timed out */
232 MVTWSI_ERROR_TIMEOUT = 0x02,
236 * mvtwsi_error() - Build I2C return code from error information
238 * For debugging purposes, this function packs some information of an occurred
239 * error into a return code. These error codes are returned from I2C API
240 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
242 * @ec: The error class of the error (enum mvtwsi_error_class).
243 * @lc: The last value of the control register.
244 * @ls: The last value of the status register.
245 * @es: The expected value of the status register.
246 * @return The generated error code.
248 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
250 return ((ec << 24) & 0xFF000000)
251 | ((lc << 16) & 0x00FF0000)
252 | ((ls << 8) & 0x0000FF00)
257 * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
259 * @return Zero if status is as expected, or a non-zero code if either a time
260 * out occurred, or the status was not the expected one.
262 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
269 control = readl(&twsi->control);
270 if (control & MVTWSI_CONTROL_IFLG) {
271 status = readl(&twsi->status);
272 if (status == expected_status)
276 MVTWSI_ERROR_WRONG_STATUS,
277 control, status, expected_status);
279 ndelay(tick); /* One clock cycle */
281 status = readl(&twsi->status);
282 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
287 * twsi_start() - Assert a START condition on the bus.
289 * This function is used in both single I2C transactions and inside
290 * back-to-back transactions (repeated starts).
292 * @twsi: The MVTWSI register structure to use.
293 * @expected_status: The I2C bus status expected to be asserted after the
294 * operation completion.
295 * @tick: The duration of a clock cycle at the current I2C speed.
296 * @return Zero if status is as expected, or a non-zero code if either a time
297 * out occurred or the status was not the expected one.
299 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
303 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
304 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
305 /* Wait for controller to process START */
306 return twsi_wait(twsi, expected_status, tick);
310 * twsi_send() - Send a byte on the I2C bus.
312 * The byte may be part of an address byte or data.
314 * @twsi: The MVTWSI register structure to use.
315 * @byte: The byte to send.
316 * @expected_status: The I2C bus status expected to be asserted after the
317 * operation completion.
318 * @tick: The duration of a clock cycle at the current I2C speed.
319 * @return Zero if status is as expected, or a non-zero code if either a time
320 * out occurred or the status was not the expected one.
322 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
323 int expected_status, uint tick)
325 /* Write byte to data register for sending */
326 writel(byte, &twsi->data);
327 /* Clear any pending interrupt -- that will cause sending */
328 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
330 /* Wait for controller to receive byte, and check ACK */
331 return twsi_wait(twsi, expected_status, tick);
335 * twsi_recv() - Receive a byte on the I2C bus.
337 * The static variable mvtwsi_control_flags controls whether we ack or nak.
339 * @twsi: The MVTWSI register structure to use.
340 * @byte: The byte to send.
341 * @ack_flag: Flag that determines whether the received byte should
342 * be acknowledged by the controller or not (sent ACK/NAK).
343 * @tick: The duration of a clock cycle at the current I2C speed.
344 * @return Zero if status is as expected, or a non-zero code if either a time
345 * out occurred or the status was not the expected one.
347 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
350 int expected_status, status, control;
352 /* Compute expected status based on passed ACK flag */
353 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
354 MVTWSI_STATUS_DATA_R_NAK;
355 /* Acknowledge *previous state*, and launch receive */
356 control = MVTWSI_CONTROL_TWSIEN;
357 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
358 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
359 /* Wait for controller to receive byte, and assert ACK or NAK */
360 status = twsi_wait(twsi, expected_status, tick);
361 /* If we did receive the expected byte, store it */
363 *byte = readl(&twsi->data);
368 * twsi_stop() - Assert a STOP condition on the bus.
370 * This function is also used to force the bus back to idle state (SDA =
373 * @twsi: The MVTWSI register structure to use.
374 * @tick: The duration of a clock cycle at the current I2C speed.
375 * @return Zero if the operation succeeded, or a non-zero code if a time out
378 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
380 int control, stop_status;
385 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
386 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
387 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
389 stop_status = readl(&twsi->status);
390 if (stop_status == MVTWSI_STATUS_IDLE)
392 ndelay(tick); /* One clock cycle */
394 control = readl(&twsi->control);
395 if (stop_status != MVTWSI_STATUS_IDLE)
396 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
397 control, status, MVTWSI_STATUS_IDLE);
402 * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
404 * @n: Parameter 'n' for the frequency calculation algorithm.
405 * @m: Parameter 'm' for the frequency calculation algorithm.
406 * @return The I2C frequency corresponding to the passed m and n parameters.
408 static uint twsi_calc_freq(const int n, const int m)
410 #ifdef CONFIG_ARCH_SUNXI
411 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
413 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
418 * twsi_reset() - Reset the I2C controller.
420 * Resetting the controller also resets the baud rate and slave address, hence
421 * they must be re-established after the reset.
423 * @twsi: The MVTWSI register structure to use.
425 static void twsi_reset(struct mvtwsi_registers *twsi)
427 /* Reset controller */
428 writel(0, &twsi->soft_reset);
429 /* Wait 2 ms -- this is what the Marvell LSP does */
434 * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
436 * This function sets baud rate to the highest possible value that does not
437 * exceed the requested rate.
439 * @twsi: The MVTWSI register structure to use.
440 * @requested_speed: The desired frequency the controller should run at
442 * @return The actual frequency the controller was configured to.
444 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
445 uint requested_speed)
447 uint tmp_speed, highest_speed, n, m;
448 uint baud = 0x44; /* Baud rate after controller reset */
451 /* Successively try m, n combinations, and use the combination
452 * resulting in the largest speed that's not above the requested
454 for (n = 0; n < 8; n++) {
455 for (m = 0; m < 16; m++) {
456 tmp_speed = twsi_calc_freq(n, m);
457 if ((tmp_speed <= requested_speed) &&
458 (tmp_speed > highest_speed)) {
459 highest_speed = tmp_speed;
464 writel(baud, &twsi->baudrate);
466 /* Wait for controller for one tick */
468 ndelay(calc_tick(highest_speed));
472 return highest_speed;
476 * __twsi_i2c_init() - Initialize the I2C controller.
478 * @twsi: The MVTWSI register structure to use.
479 * @speed: The initial frequency the controller should run at
481 * @slaveadd: The I2C address to be set for the I2C master.
482 * @actual_speed: A output parameter that receives the actual frequency
483 * in Hz the controller was set to by the function.
484 * @return Zero if the operation succeeded, or a non-zero code if a time out
487 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
488 int slaveadd, uint *actual_speed)
492 /* Reset controller */
495 tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
497 *actual_speed = tmp_speed;
498 /* Set slave address; even though we don't use it */
499 writel(slaveadd, &twsi->slave_address);
500 writel(0, &twsi->xtnd_slave_addr);
501 /* Assert STOP, but don't care for the result */
503 (void) twsi_stop(twsi, calc_tick(*actual_speed));
505 (void) twsi_stop(twsi, 10000);
510 * i2c_begin() - Start a I2C transaction.
512 * Begin a I2C transaction with a given expected start status and chip address.
513 * A START is asserted, and the address byte is sent to the I2C controller. The
514 * expected address status will be derived from the direction bit (bit 0) of
517 * @twsi: The MVTWSI register structure to use.
518 * @expected_start_status: The I2C status the controller is expected to
519 * assert after the address byte was sent.
520 * @addr: The address byte to be sent.
521 * @tick: The duration of a clock cycle at the current
523 * @return Zero if the operation succeeded, or a non-zero code if a time out or
524 * unexpected I2C status occurred.
526 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
529 int status, expected_addr_status;
531 /* Compute the expected address status from the direction bit in
532 * the address byte */
533 if (addr & 1) /* Reading */
534 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
536 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
538 status = twsi_start(twsi, expected_start_status, tick);
539 /* Send out the address if the start went well */
541 status = twsi_send(twsi, addr, expected_addr_status, tick);
542 /* Return 0, or the status of the first failure */
547 * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
549 * This function begins a I2C read transaction, does a dummy read and NAKs; if
550 * the procedure succeeds, the chip is considered to be present.
552 * @twsi: The MVTWSI register structure to use.
553 * @chip: The chip address to probe.
554 * @tick: The duration of a clock cycle at the current I2C speed.
555 * @return Zero if the operation succeeded, or a non-zero code if a time out or
556 * unexpected I2C status occurred.
558 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
565 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
566 /* Dummy read was accepted: receive byte, but NAK it. */
568 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
569 /* Stop transaction */
570 twsi_stop(twsi, tick);
571 /* Return 0, or the status of the first failure */
576 * __twsi_i2c_read() - Read data from a I2C chip.
578 * This function begins a I2C write transaction, and transmits the address
579 * bytes; then begins a I2C read transaction, and receives the data bytes.
581 * NOTE: Some devices want a stop right before the second start, while some
582 * will choke if it is there. Since deciding this is not yet supported in
583 * higher level APIs, we need to make a decision here, and for the moment that
584 * will be a repeated start without a preceding stop.
586 * @twsi: The MVTWSI register structure to use.
587 * @chip: The chip address to read from.
588 * @addr: The address bytes to send.
589 * @alen: The length of the address bytes in bytes.
590 * @data: The buffer to receive the data read from the chip (has to have
591 * a size of at least 'length' bytes).
592 * @length: The amount of data to be read from the chip in bytes.
593 * @tick: The duration of a clock cycle at the current I2C speed.
594 * @return Zero if the operation succeeded, or a non-zero code if a time out or
595 * unexpected I2C status occurred.
597 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
598 u8 *addr, int alen, uchar *data, int length,
603 int expected_start = MVTWSI_STATUS_START;
606 /* Begin i2c write to send the address bytes */
607 status = i2c_begin(twsi, expected_start, (chip << 1), tick);
608 /* Send address bytes */
609 while ((status == 0) && alen--)
610 status = twsi_send(twsi, addr[alen],
611 MVTWSI_STATUS_DATA_W_ACK, tick);
612 /* Send repeated STARTs after the initial START */
613 expected_start = MVTWSI_STATUS_REPEATED_START;
615 /* Begin i2c read to receive data bytes */
617 status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
618 /* Receive actual data bytes; set NAK if we if we have nothing more to
620 while ((status == 0) && length--)
621 status = twsi_recv(twsi, data++,
623 MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
624 /* Stop transaction */
625 stop_status = twsi_stop(twsi, tick);
626 /* Return 0, or the status of the first failure */
627 return status != 0 ? status : stop_status;
631 * __twsi_i2c_write() - Send data to a I2C chip.
633 * This function begins a I2C write transaction, and transmits the address
634 * bytes; then begins a new I2C write transaction, and sends the data bytes.
636 * @twsi: The MVTWSI register structure to use.
637 * @chip: The chip address to read from.
638 * @addr: The address bytes to send.
639 * @alen: The length of the address bytes in bytes.
640 * @data: The buffer containing the data to be sent to the chip.
641 * @length: The length of data to be sent to the chip in bytes.
642 * @tick: The duration of a clock cycle at the current I2C speed.
643 * @return Zero if the operation succeeded, or a non-zero code if a time out or
644 * unexpected I2C status occurred.
646 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
647 u8 *addr, int alen, uchar *data, int length,
650 int status, stop_status;
652 /* Begin i2c write to send first the address bytes, then the
654 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
655 /* Send address bytes */
656 while ((status == 0) && (alen-- > 0))
657 status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK,
659 /* Send data bytes */
660 while ((status == 0) && (length-- > 0))
661 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
663 /* Stop transaction */
664 stop_status = twsi_stop(twsi, tick);
665 /* Return 0, or the status of the first failure */
666 return status != 0 ? status : stop_status;
669 #ifndef CONFIG_DM_I2C
670 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
673 struct mvtwsi_registers *twsi = twsi_get_base(adap);
674 __twsi_i2c_init(twsi, speed, slaveadd, NULL);
677 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
678 uint requested_speed)
680 struct mvtwsi_registers *twsi = twsi_get_base(adap);
681 __twsi_i2c_set_bus_speed(twsi, requested_speed);
685 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
687 struct mvtwsi_registers *twsi = twsi_get_base(adap);
688 return __twsi_i2c_probe_chip(twsi, chip, 10000);
691 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
692 int alen, uchar *data, int length)
694 struct mvtwsi_registers *twsi = twsi_get_base(adap);
697 addr_bytes[0] = (addr >> 0) & 0xFF;
698 addr_bytes[1] = (addr >> 8) & 0xFF;
699 addr_bytes[2] = (addr >> 16) & 0xFF;
700 addr_bytes[3] = (addr >> 24) & 0xFF;
702 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
706 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
707 int alen, uchar *data, int length)
709 struct mvtwsi_registers *twsi = twsi_get_base(adap);
712 addr_bytes[0] = (addr >> 0) & 0xFF;
713 addr_bytes[1] = (addr >> 8) & 0xFF;
714 addr_bytes[2] = (addr >> 16) & 0xFF;
715 addr_bytes[3] = (addr >> 24) & 0xFF;
717 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
721 #ifdef CONFIG_I2C_MVTWSI_BASE0
722 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
723 twsi_i2c_read, twsi_i2c_write,
724 twsi_i2c_set_bus_speed,
725 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
727 #ifdef CONFIG_I2C_MVTWSI_BASE1
728 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
729 twsi_i2c_read, twsi_i2c_write,
730 twsi_i2c_set_bus_speed,
731 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
734 #ifdef CONFIG_I2C_MVTWSI_BASE2
735 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
736 twsi_i2c_read, twsi_i2c_write,
737 twsi_i2c_set_bus_speed,
738 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
741 #ifdef CONFIG_I2C_MVTWSI_BASE3
742 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
743 twsi_i2c_read, twsi_i2c_write,
744 twsi_i2c_set_bus_speed,
745 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
748 #ifdef CONFIG_I2C_MVTWSI_BASE4
749 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
750 twsi_i2c_read, twsi_i2c_write,
751 twsi_i2c_set_bus_speed,
752 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
755 #ifdef CONFIG_I2C_MVTWSI_BASE5
756 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
757 twsi_i2c_read, twsi_i2c_write,
758 twsi_i2c_set_bus_speed,
759 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
762 #else /* CONFIG_DM_I2C */
764 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
767 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
768 return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
771 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
773 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
775 dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
776 dev->tick = calc_tick(dev->speed);
781 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
783 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
785 dev->base = devfdt_get_addr_ptr(bus);
790 dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
792 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
793 "u-boot,i2c-slave-addr", 0x0);
794 dev->speed = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
795 "clock-frequency", 100000);
799 static int mvtwsi_i2c_probe(struct udevice *bus)
801 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
804 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
805 dev->speed = actual_speed;
806 dev->tick = calc_tick(dev->speed);
810 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
812 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
813 struct i2c_msg *dmsg, *omsg, dummy;
815 memset(&dummy, 0, sizeof(struct i2c_msg));
817 /* We expect either two messages (one with an offset and one with the
818 * actual data) or one message (just data or offset/data combined) */
819 if (nmsgs > 2 || nmsgs == 0) {
820 debug("%s: Only one or two messages are supported.", __func__);
824 omsg = nmsgs == 1 ? &dummy : msg;
825 dmsg = nmsgs == 1 ? msg : msg + 1;
827 if (dmsg->flags & I2C_M_RD)
828 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
829 omsg->len, dmsg->buf, dmsg->len,
832 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
833 omsg->len, dmsg->buf, dmsg->len,
837 static const struct dm_i2c_ops mvtwsi_i2c_ops = {
838 .xfer = mvtwsi_i2c_xfer,
839 .probe_chip = mvtwsi_i2c_probe_chip,
840 .set_bus_speed = mvtwsi_i2c_set_bus_speed,
843 static const struct udevice_id mvtwsi_i2c_ids[] = {
844 { .compatible = "marvell,mv64xxx-i2c", },
845 { .compatible = "marvell,mv78230-i2c", },
846 { .compatible = "allwinner,sun6i-a31-i2c", },
850 U_BOOT_DRIVER(i2c_mvtwsi) = {
851 .name = "i2c_mvtwsi",
853 .of_match = mvtwsi_i2c_ids,
854 .probe = mvtwsi_i2c_probe,
855 .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
856 .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
857 .ops = &mvtwsi_i2c_ops,
859 #endif /* CONFIG_DM_I2C */