1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for the TWSI (i2c) controller found on the Marvell
4 * orion5x and kirkwood SoC families.
6 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
7 * Copyright (c) 2010 Albert Aribaud.
12 #include <linux/errno.h>
14 #include <linux/compat.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
27 #if defined(CONFIG_ORION5X)
28 #include <asm/arch/orion5x.h>
29 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
30 #include <asm/arch/soc.h>
31 #elif defined(CONFIG_ARCH_SUNXI)
32 #include <asm/arch/i2c.h>
34 #error Driver mvtwsi not supported by SoC or board
36 #endif /* CONFIG_DM_I2C */
39 * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
42 #if defined(CONFIG_DM_I2C) && defined(CONFIG_ARCH_SUNXI)
43 #include <asm/arch/i2c.h>
47 * TWSI register structure
50 #ifdef CONFIG_ARCH_SUNXI
52 struct mvtwsi_registers {
64 struct mvtwsi_registers {
69 u32 status; /* When reading */
70 u32 baudrate; /* When writing */
80 struct mvtwsi_i2c_dev {
81 /* TWSI Register base for the device */
82 struct mvtwsi_registers *base;
83 /* Number of the device (determined from cell-index property) */
85 /* The I2C slave address for the device */
87 /* The configured I2C speed in Hz */
89 /* The current length of a clock period (depending on speed) */
92 #endif /* CONFIG_DM_I2C */
95 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
98 enum mvtwsi_ctrl_register_fields {
100 MVTWSI_CONTROL_ACK = 0x00000004,
102 MVTWSI_CONTROL_IFLG = 0x00000008,
104 MVTWSI_CONTROL_STOP = 0x00000010,
106 MVTWSI_CONTROL_START = 0x00000020,
108 MVTWSI_CONTROL_TWSIEN = 0x00000040,
109 /* Interrupt enable */
110 MVTWSI_CONTROL_INTEN = 0x00000080,
114 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
115 * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
118 #ifdef CONFIG_SUNXI_GEN_SUN6I
119 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
121 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
125 * enum mvstwsi_status_values - Possible values of I2C controller's status
128 * Only those statuses expected in normal master operation on
129 * non-10-bit-address devices are specified.
131 * Every status that's unexpected during normal operation (bus errors,
132 * arbitration losses, missing ACKs...) is passed back to the caller as an error
135 enum mvstwsi_status_values {
136 /* START condition transmitted */
137 MVTWSI_STATUS_START = 0x08,
138 /* Repeated START condition transmitted */
139 MVTWSI_STATUS_REPEATED_START = 0x10,
140 /* Address + write bit transmitted, ACK received */
141 MVTWSI_STATUS_ADDR_W_ACK = 0x18,
142 /* Data transmitted, ACK received */
143 MVTWSI_STATUS_DATA_W_ACK = 0x28,
144 /* Address + read bit transmitted, ACK received */
145 MVTWSI_STATUS_ADDR_R_ACK = 0x40,
146 /* Address + read bit transmitted, ACK not received */
147 MVTWSI_STATUS_ADDR_R_NAK = 0x48,
148 /* Data received, ACK transmitted */
149 MVTWSI_STATUS_DATA_R_ACK = 0x50,
150 /* Data received, ACK not transmitted */
151 MVTWSI_STATUS_DATA_R_NAK = 0x58,
152 /* No relevant status */
153 MVTWSI_STATUS_IDLE = 0xF8,
157 * enum mvstwsi_ack_flags - Determine whether a read byte should be
158 * acknowledged or not.
160 enum mvtwsi_ack_flags {
161 /* Send NAK after received byte */
163 /* Send ACK after received byte */
168 * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
170 * @speed: The speed in Hz to calculate the clock cycle duration for.
171 * @return The duration of a clock cycle in ns.
173 inline uint calc_tick(uint speed)
175 /* One tick = the duration of a period at the specified speed in ns (we
176 * add 100 ns to be on the safe side) */
177 return (1000000000u / speed) + 100;
180 #ifndef CONFIG_DM_I2C
183 * twsi_get_base() - Get controller register base for specified adapter
185 * @adap: Adapter to get the register base for.
186 * @return Register base for the specified adapter.
188 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
190 switch (adap->hwadapnr) {
191 #ifdef CONFIG_I2C_MVTWSI_BASE0
193 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
195 #ifdef CONFIG_I2C_MVTWSI_BASE1
197 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
199 #ifdef CONFIG_I2C_MVTWSI_BASE2
201 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
203 #ifdef CONFIG_I2C_MVTWSI_BASE3
205 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
207 #ifdef CONFIG_I2C_MVTWSI_BASE4
209 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
211 #ifdef CONFIG_I2C_MVTWSI_BASE5
213 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
216 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
225 * enum mvtwsi_error_class - types of I2C errors
227 enum mvtwsi_error_class {
228 /* The controller returned a different status than expected */
229 MVTWSI_ERROR_WRONG_STATUS = 0x01,
230 /* The controller timed out */
231 MVTWSI_ERROR_TIMEOUT = 0x02,
235 * mvtwsi_error() - Build I2C return code from error information
237 * For debugging purposes, this function packs some information of an occurred
238 * error into a return code. These error codes are returned from I2C API
239 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
241 * @ec: The error class of the error (enum mvtwsi_error_class).
242 * @lc: The last value of the control register.
243 * @ls: The last value of the status register.
244 * @es: The expected value of the status register.
245 * @return The generated error code.
247 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
249 return ((ec << 24) & 0xFF000000)
250 | ((lc << 16) & 0x00FF0000)
251 | ((ls << 8) & 0x0000FF00)
256 * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
258 * @return Zero if status is as expected, or a non-zero code if either a time
259 * out occurred, or the status was not the expected one.
261 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
268 control = readl(&twsi->control);
269 if (control & MVTWSI_CONTROL_IFLG) {
270 status = readl(&twsi->status);
271 if (status == expected_status)
275 MVTWSI_ERROR_WRONG_STATUS,
276 control, status, expected_status);
278 ndelay(tick); /* One clock cycle */
280 status = readl(&twsi->status);
281 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
286 * twsi_start() - Assert a START condition on the bus.
288 * This function is used in both single I2C transactions and inside
289 * back-to-back transactions (repeated starts).
291 * @twsi: The MVTWSI register structure to use.
292 * @expected_status: The I2C bus status expected to be asserted after the
293 * operation completion.
294 * @tick: The duration of a clock cycle at the current I2C speed.
295 * @return Zero if status is as expected, or a non-zero code if either a time
296 * out occurred or the status was not the expected one.
298 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
302 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
303 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
304 /* Wait for controller to process START */
305 return twsi_wait(twsi, expected_status, tick);
309 * twsi_send() - Send a byte on the I2C bus.
311 * The byte may be part of an address byte or data.
313 * @twsi: The MVTWSI register structure to use.
314 * @byte: The byte to send.
315 * @expected_status: The I2C bus status expected to be asserted after the
316 * operation completion.
317 * @tick: The duration of a clock cycle at the current I2C speed.
318 * @return Zero if status is as expected, or a non-zero code if either a time
319 * out occurred or the status was not the expected one.
321 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
322 int expected_status, uint tick)
324 /* Write byte to data register for sending */
325 writel(byte, &twsi->data);
326 /* Clear any pending interrupt -- that will cause sending */
327 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
329 /* Wait for controller to receive byte, and check ACK */
330 return twsi_wait(twsi, expected_status, tick);
334 * twsi_recv() - Receive a byte on the I2C bus.
336 * The static variable mvtwsi_control_flags controls whether we ack or nak.
338 * @twsi: The MVTWSI register structure to use.
339 * @byte: The byte to send.
340 * @ack_flag: Flag that determines whether the received byte should
341 * be acknowledged by the controller or not (sent ACK/NAK).
342 * @tick: The duration of a clock cycle at the current I2C speed.
343 * @return Zero if status is as expected, or a non-zero code if either a time
344 * out occurred or the status was not the expected one.
346 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
349 int expected_status, status, control;
351 /* Compute expected status based on passed ACK flag */
352 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
353 MVTWSI_STATUS_DATA_R_NAK;
354 /* Acknowledge *previous state*, and launch receive */
355 control = MVTWSI_CONTROL_TWSIEN;
356 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
357 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
358 /* Wait for controller to receive byte, and assert ACK or NAK */
359 status = twsi_wait(twsi, expected_status, tick);
360 /* If we did receive the expected byte, store it */
362 *byte = readl(&twsi->data);
367 * twsi_stop() - Assert a STOP condition on the bus.
369 * This function is also used to force the bus back to idle state (SDA =
372 * @twsi: The MVTWSI register structure to use.
373 * @tick: The duration of a clock cycle at the current I2C speed.
374 * @return Zero if the operation succeeded, or a non-zero code if a time out
377 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
379 int control, stop_status;
384 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
385 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
386 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
388 stop_status = readl(&twsi->status);
389 if (stop_status == MVTWSI_STATUS_IDLE)
391 ndelay(tick); /* One clock cycle */
393 control = readl(&twsi->control);
394 if (stop_status != MVTWSI_STATUS_IDLE)
395 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
396 control, status, MVTWSI_STATUS_IDLE);
401 * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
403 * @n: Parameter 'n' for the frequency calculation algorithm.
404 * @m: Parameter 'm' for the frequency calculation algorithm.
405 * @return The I2C frequency corresponding to the passed m and n parameters.
407 static uint twsi_calc_freq(const int n, const int m)
409 #ifdef CONFIG_ARCH_SUNXI
410 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
412 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
417 * twsi_reset() - Reset the I2C controller.
419 * Resetting the controller also resets the baud rate and slave address, hence
420 * they must be re-established after the reset.
422 * @twsi: The MVTWSI register structure to use.
424 static void twsi_reset(struct mvtwsi_registers *twsi)
426 /* Reset controller */
427 writel(0, &twsi->soft_reset);
428 /* Wait 2 ms -- this is what the Marvell LSP does */
433 * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
435 * This function sets baud rate to the highest possible value that does not
436 * exceed the requested rate.
438 * @twsi: The MVTWSI register structure to use.
439 * @requested_speed: The desired frequency the controller should run at
441 * @return The actual frequency the controller was configured to.
443 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
444 uint requested_speed)
446 uint tmp_speed, highest_speed, n, m;
447 uint baud = 0x44; /* Baud rate after controller reset */
450 /* Successively try m, n combinations, and use the combination
451 * resulting in the largest speed that's not above the requested
453 for (n = 0; n < 8; n++) {
454 for (m = 0; m < 16; m++) {
455 tmp_speed = twsi_calc_freq(n, m);
456 if ((tmp_speed <= requested_speed) &&
457 (tmp_speed > highest_speed)) {
458 highest_speed = tmp_speed;
463 writel(baud, &twsi->baudrate);
465 /* Wait for controller for one tick */
467 ndelay(calc_tick(highest_speed));
471 return highest_speed;
475 * __twsi_i2c_init() - Initialize the I2C controller.
477 * @twsi: The MVTWSI register structure to use.
478 * @speed: The initial frequency the controller should run at
480 * @slaveadd: The I2C address to be set for the I2C master.
481 * @actual_speed: A output parameter that receives the actual frequency
482 * in Hz the controller was set to by the function.
483 * @return Zero if the operation succeeded, or a non-zero code if a time out
486 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
487 int slaveadd, uint *actual_speed)
491 /* Reset controller */
494 tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
496 *actual_speed = tmp_speed;
497 /* Set slave address; even though we don't use it */
498 writel(slaveadd, &twsi->slave_address);
499 writel(0, &twsi->xtnd_slave_addr);
500 /* Assert STOP, but don't care for the result */
502 (void) twsi_stop(twsi, calc_tick(*actual_speed));
504 (void) twsi_stop(twsi, 10000);
509 * i2c_begin() - Start a I2C transaction.
511 * Begin a I2C transaction with a given expected start status and chip address.
512 * A START is asserted, and the address byte is sent to the I2C controller. The
513 * expected address status will be derived from the direction bit (bit 0) of
516 * @twsi: The MVTWSI register structure to use.
517 * @expected_start_status: The I2C status the controller is expected to
518 * assert after the address byte was sent.
519 * @addr: The address byte to be sent.
520 * @tick: The duration of a clock cycle at the current
522 * @return Zero if the operation succeeded, or a non-zero code if a time out or
523 * unexpected I2C status occurred.
525 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
528 int status, expected_addr_status;
530 /* Compute the expected address status from the direction bit in
531 * the address byte */
532 if (addr & 1) /* Reading */
533 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
535 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
537 status = twsi_start(twsi, expected_start_status, tick);
538 /* Send out the address if the start went well */
540 status = twsi_send(twsi, addr, expected_addr_status, tick);
541 /* Return 0, or the status of the first failure */
546 * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
548 * This function begins a I2C read transaction, does a dummy read and NAKs; if
549 * the procedure succeeds, the chip is considered to be present.
551 * @twsi: The MVTWSI register structure to use.
552 * @chip: The chip address to probe.
553 * @tick: The duration of a clock cycle at the current I2C speed.
554 * @return Zero if the operation succeeded, or a non-zero code if a time out or
555 * unexpected I2C status occurred.
557 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
564 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
565 /* Dummy read was accepted: receive byte, but NAK it. */
567 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
568 /* Stop transaction */
569 twsi_stop(twsi, tick);
570 /* Return 0, or the status of the first failure */
575 * __twsi_i2c_read() - Read data from a I2C chip.
577 * This function begins a I2C write transaction, and transmits the address
578 * bytes; then begins a I2C read transaction, and receives the data bytes.
580 * NOTE: Some devices want a stop right before the second start, while some
581 * will choke if it is there. Since deciding this is not yet supported in
582 * higher level APIs, we need to make a decision here, and for the moment that
583 * will be a repeated start without a preceding stop.
585 * @twsi: The MVTWSI register structure to use.
586 * @chip: The chip address to read from.
587 * @addr: The address bytes to send.
588 * @alen: The length of the address bytes in bytes.
589 * @data: The buffer to receive the data read from the chip (has to have
590 * a size of at least 'length' bytes).
591 * @length: The amount of data to be read from the chip in bytes.
592 * @tick: The duration of a clock cycle at the current I2C speed.
593 * @return Zero if the operation succeeded, or a non-zero code if a time out or
594 * unexpected I2C status occurred.
596 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
597 u8 *addr, int alen, uchar *data, int length,
602 int expected_start = MVTWSI_STATUS_START;
605 /* Begin i2c write to send the address bytes */
606 status = i2c_begin(twsi, expected_start, (chip << 1), tick);
607 /* Send address bytes */
608 while ((status == 0) && alen--)
609 status = twsi_send(twsi, addr[alen],
610 MVTWSI_STATUS_DATA_W_ACK, tick);
611 /* Send repeated STARTs after the initial START */
612 expected_start = MVTWSI_STATUS_REPEATED_START;
614 /* Begin i2c read to receive data bytes */
616 status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
617 /* Receive actual data bytes; set NAK if we if we have nothing more to
619 while ((status == 0) && length--)
620 status = twsi_recv(twsi, data++,
622 MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
623 /* Stop transaction */
624 stop_status = twsi_stop(twsi, tick);
625 /* Return 0, or the status of the first failure */
626 return status != 0 ? status : stop_status;
630 * __twsi_i2c_write() - Send data to a I2C chip.
632 * This function begins a I2C write transaction, and transmits the address
633 * bytes; then begins a new I2C write transaction, and sends the data bytes.
635 * @twsi: The MVTWSI register structure to use.
636 * @chip: The chip address to read from.
637 * @addr: The address bytes to send.
638 * @alen: The length of the address bytes in bytes.
639 * @data: The buffer containing the data to be sent to the chip.
640 * @length: The length of data to be sent to the chip in bytes.
641 * @tick: The duration of a clock cycle at the current I2C speed.
642 * @return Zero if the operation succeeded, or a non-zero code if a time out or
643 * unexpected I2C status occurred.
645 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
646 u8 *addr, int alen, uchar *data, int length,
649 int status, stop_status;
651 /* Begin i2c write to send first the address bytes, then the
653 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
654 /* Send address bytes */
655 while ((status == 0) && (alen-- > 0))
656 status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK,
658 /* Send data bytes */
659 while ((status == 0) && (length-- > 0))
660 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
662 /* Stop transaction */
663 stop_status = twsi_stop(twsi, tick);
664 /* Return 0, or the status of the first failure */
665 return status != 0 ? status : stop_status;
668 #ifndef CONFIG_DM_I2C
669 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
672 struct mvtwsi_registers *twsi = twsi_get_base(adap);
673 __twsi_i2c_init(twsi, speed, slaveadd, NULL);
676 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
677 uint requested_speed)
679 struct mvtwsi_registers *twsi = twsi_get_base(adap);
680 __twsi_i2c_set_bus_speed(twsi, requested_speed);
684 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
686 struct mvtwsi_registers *twsi = twsi_get_base(adap);
687 return __twsi_i2c_probe_chip(twsi, chip, 10000);
690 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
691 int alen, uchar *data, int length)
693 struct mvtwsi_registers *twsi = twsi_get_base(adap);
696 addr_bytes[0] = (addr >> 0) & 0xFF;
697 addr_bytes[1] = (addr >> 8) & 0xFF;
698 addr_bytes[2] = (addr >> 16) & 0xFF;
699 addr_bytes[3] = (addr >> 24) & 0xFF;
701 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
705 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
706 int alen, uchar *data, int length)
708 struct mvtwsi_registers *twsi = twsi_get_base(adap);
711 addr_bytes[0] = (addr >> 0) & 0xFF;
712 addr_bytes[1] = (addr >> 8) & 0xFF;
713 addr_bytes[2] = (addr >> 16) & 0xFF;
714 addr_bytes[3] = (addr >> 24) & 0xFF;
716 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
720 #ifdef CONFIG_I2C_MVTWSI_BASE0
721 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
722 twsi_i2c_read, twsi_i2c_write,
723 twsi_i2c_set_bus_speed,
724 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
726 #ifdef CONFIG_I2C_MVTWSI_BASE1
727 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
728 twsi_i2c_read, twsi_i2c_write,
729 twsi_i2c_set_bus_speed,
730 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
733 #ifdef CONFIG_I2C_MVTWSI_BASE2
734 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
735 twsi_i2c_read, twsi_i2c_write,
736 twsi_i2c_set_bus_speed,
737 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
740 #ifdef CONFIG_I2C_MVTWSI_BASE3
741 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
742 twsi_i2c_read, twsi_i2c_write,
743 twsi_i2c_set_bus_speed,
744 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
747 #ifdef CONFIG_I2C_MVTWSI_BASE4
748 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
749 twsi_i2c_read, twsi_i2c_write,
750 twsi_i2c_set_bus_speed,
751 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
754 #ifdef CONFIG_I2C_MVTWSI_BASE5
755 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
756 twsi_i2c_read, twsi_i2c_write,
757 twsi_i2c_set_bus_speed,
758 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
761 #else /* CONFIG_DM_I2C */
763 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
766 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
767 return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
770 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
772 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
774 dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
775 dev->tick = calc_tick(dev->speed);
780 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
782 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
784 dev->base = devfdt_get_addr_ptr(bus);
789 dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
791 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
792 "u-boot,i2c-slave-addr", 0x0);
793 dev->speed = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
794 "clock-frequency", 100000);
798 static int mvtwsi_i2c_probe(struct udevice *bus)
800 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
803 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
804 dev->speed = actual_speed;
805 dev->tick = calc_tick(dev->speed);
809 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
811 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
812 struct i2c_msg *dmsg, *omsg, dummy;
814 memset(&dummy, 0, sizeof(struct i2c_msg));
816 /* We expect either two messages (one with an offset and one with the
817 * actual data) or one message (just data or offset/data combined) */
818 if (nmsgs > 2 || nmsgs == 0) {
819 debug("%s: Only one or two messages are supported.", __func__);
823 omsg = nmsgs == 1 ? &dummy : msg;
824 dmsg = nmsgs == 1 ? msg : msg + 1;
826 if (dmsg->flags & I2C_M_RD)
827 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
828 omsg->len, dmsg->buf, dmsg->len,
831 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
832 omsg->len, dmsg->buf, dmsg->len,
836 static const struct dm_i2c_ops mvtwsi_i2c_ops = {
837 .xfer = mvtwsi_i2c_xfer,
838 .probe_chip = mvtwsi_i2c_probe_chip,
839 .set_bus_speed = mvtwsi_i2c_set_bus_speed,
842 static const struct udevice_id mvtwsi_i2c_ids[] = {
843 { .compatible = "marvell,mv64xxx-i2c", },
844 { .compatible = "marvell,mv78230-i2c", },
845 { .compatible = "allwinner,sun6i-a31-i2c", },
849 U_BOOT_DRIVER(i2c_mvtwsi) = {
850 .name = "i2c_mvtwsi",
852 .of_match = mvtwsi_i2c_ids,
853 .probe = mvtwsi_i2c_probe,
854 .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
855 .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
856 .ops = &mvtwsi_i2c_ops,
858 #endif /* CONFIG_DM_I2C */