2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
43 #define I2CR_IIEN (1 << 6)
44 #define I2CR_MSTA (1 << 5)
45 #define I2CR_MTX (1 << 4)
46 #define I2CR_TX_NO_AK (1 << 3)
47 #define I2CR_RSTA (1 << 2)
49 #define I2SR_ICF (1 << 7)
50 #define I2SR_IBB (1 << 5)
51 #define I2SR_IAL (1 << 4)
52 #define I2SR_IIF (1 << 1)
53 #define I2SR_RX_NO_AK (1 << 0)
56 #define I2CR_IEN (0 << 7)
57 #define I2CR_IDIS (1 << 7)
58 #define I2SR_IIF_CLEAR (1 << 1)
60 #define I2CR_IEN (1 << 7)
61 #define I2CR_IDIS (0 << 7)
62 #define I2SR_IIF_CLEAR (0 << 1)
65 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
66 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
70 static u16 i2c_clk_div[60][2] = {
71 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
72 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
73 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
74 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
75 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
76 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
77 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
78 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
79 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
80 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
81 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
82 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
83 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
84 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
85 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
88 static u16 i2c_clk_div[50][2] = {
89 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
90 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
91 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
92 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
93 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
94 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
95 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
96 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
97 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
98 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
99 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
100 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
101 { 3072, 0x1E }, { 3840, 0x1F }
106 * Calculate and set proper clock divider
108 static uint8_t i2c_imx_get_clk(unsigned int rate)
110 unsigned int i2c_clk_rate;
114 #if defined(CONFIG_MX31)
115 struct clock_control_regs *sc_regs =
116 (struct clock_control_regs *)CCM_BASE;
118 /* start the required I2C clock */
119 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
123 /* Divider value calculation */
124 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
125 div = (i2c_clk_rate + rate - 1) / rate;
126 if (div < i2c_clk_div[0][0])
128 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
129 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
131 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
134 /* Store divider value */
141 static int bus_i2c_set_bus_speed(void *base, int speed)
143 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
144 u8 clk_idx = i2c_imx_get_clk(speed);
145 u8 idx = i2c_clk_div[clk_idx][1];
147 /* Store divider value */
148 writeb(idx, &i2c_regs->ifdr);
151 writeb(I2CR_IDIS, &i2c_regs->i2cr);
152 writeb(0, &i2c_regs->i2sr);
159 static unsigned int bus_i2c_get_bus_speed(void *base)
161 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
162 u8 clk_idx = readb(&i2c_regs->ifdr);
165 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
168 return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
171 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
172 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
173 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
175 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
179 ulong start_time = get_timer(0);
181 sr = readb(&i2c_regs->i2sr);
184 writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
186 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
188 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
189 __func__, sr, readb(&i2c_regs->i2cr), state);
192 if ((sr & (state >> 8)) == (unsigned char)state)
195 elapsed = get_timer(start_time);
196 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
199 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
200 sr, readb(&i2c_regs->i2cr), state);
204 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
208 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
209 writeb(byte, &i2c_regs->i2dr);
210 ret = wait_for_sr_state(i2c_regs, ST_IIF);
213 if (ret & I2SR_RX_NO_AK)
219 * Stop I2C transaction
221 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
224 unsigned int temp = readb(&i2c_regs->i2cr);
226 temp &= ~(I2CR_MSTA | I2CR_MTX);
227 writeb(temp, &i2c_regs->i2cr);
228 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
230 printf("%s:trigger stop failed\n", __func__);
234 * Send start signal, chip address and
235 * write register address
237 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
238 uchar chip, uint addr, int alen)
243 /* Enable I2C controller */
245 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
247 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
249 writeb(I2CR_IEN, &i2c_regs->i2cr);
250 /* Wait for controller to be stable */
253 if (readb(&i2c_regs->iadr) == (chip << 1))
254 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
255 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
256 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
260 /* Start I2C transaction */
261 temp = readb(&i2c_regs->i2cr);
263 writeb(temp, &i2c_regs->i2cr);
265 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
269 temp |= I2CR_MTX | I2CR_TX_NO_AK;
270 writeb(temp, &i2c_regs->i2cr);
272 /* write slave address */
273 ret = tx_byte(i2c_regs, chip << 1);
278 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
285 static int i2c_idle_bus(void *base);
287 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
288 uchar chip, uint addr, int alen)
292 for (retry = 0; retry < 3; retry++) {
293 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
296 i2c_imx_stop(i2c_regs);
300 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
302 if (ret != -ERESTART)
303 /* Disable controller */
304 writeb(I2CR_IDIS, &i2c_regs->i2cr);
306 if (i2c_idle_bus(i2c_regs) < 0)
309 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
314 * Read data from I2C device
316 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
322 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
324 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
328 temp = readb(&i2c_regs->i2cr);
330 writeb(temp, &i2c_regs->i2cr);
332 ret = tx_byte(i2c_regs, (chip << 1) | 1);
334 i2c_imx_stop(i2c_regs);
338 /* setup bus to read data */
339 temp = readb(&i2c_regs->i2cr);
340 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
342 temp |= I2CR_TX_NO_AK;
343 writeb(temp, &i2c_regs->i2cr);
344 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
345 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
348 for (i = 0; i < len; i++) {
349 ret = wait_for_sr_state(i2c_regs, ST_IIF);
351 i2c_imx_stop(i2c_regs);
356 * It must generate STOP before read I2DR to prevent
357 * controller from generating another clock cycle
359 if (i == (len - 1)) {
360 i2c_imx_stop(i2c_regs);
361 } else if (i == (len - 2)) {
362 temp = readb(&i2c_regs->i2cr);
363 temp |= I2CR_TX_NO_AK;
364 writeb(temp, &i2c_regs->i2cr);
366 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
367 buf[i] = readb(&i2c_regs->i2dr);
369 i2c_imx_stop(i2c_regs);
374 * Write data to I2C device
376 int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
377 const uchar *buf, int len)
381 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
383 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
387 for (i = 0; i < len; i++) {
388 ret = tx_byte(i2c_regs, buf[i]);
392 i2c_imx_stop(i2c_regs);
399 int (*idle_bus_fn)(void *p);
403 unsigned curr_i2c_bus;
404 struct i2c_parms i2c_data[3];
408 * For SPL boot some boards need i2c before SDRAM is initialized so force
409 * variables to live in SRAM
411 static struct sram_data __attribute__((section(".data"))) srdata;
415 #ifdef CONFIG_SYS_I2C_BASE
416 #ifdef CONFIG_I2C_MULTI_BUS
417 void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
421 return (void *)CONFIG_SYS_I2C_BASE;
422 #elif defined(CONFIG_I2C_MULTI_BUS)
423 return srdata.i2c_data[srdata.curr_i2c_bus].base;
425 return srdata.i2c_data[0].base;
429 static struct i2c_parms *i2c_get_parms(void *base)
432 struct i2c_parms *p = srdata.i2c_data;
433 while (i < ARRAY_SIZE(srdata.i2c_data)) {
439 printf("Invalid I2C base: %p\n", base);
443 static int i2c_idle_bus(void *base)
445 struct i2c_parms *p = i2c_get_parms(base);
446 if (p && p->idle_bus_fn)
447 return p->idle_bus_fn(p->idle_bus_data);
451 #ifdef CONFIG_I2C_MULTI_BUS
452 unsigned int i2c_get_bus_num(void)
454 return srdata.curr_i2c_bus;
457 int i2c_set_bus_num(unsigned bus_idx)
459 if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
461 if (!srdata.i2c_data[bus_idx].base)
463 srdata.curr_i2c_bus = bus_idx;
468 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
470 return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
473 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
475 return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
479 * Test if a chip at a given address responds (probe the chip)
481 int i2c_probe(uchar chip)
483 return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
486 void bus_i2c_init(void *base, int speed, int unused,
487 int (*idle_bus_fn)(void *p), void *idle_bus_data)
490 struct i2c_parms *p = srdata.i2c_data;
494 if (!p->base || (p->base == base)) {
497 p->idle_bus_fn = idle_bus_fn;
498 p->idle_bus_data = idle_bus_data;
504 if (i >= ARRAY_SIZE(srdata.i2c_data))
507 bus_i2c_set_bus_speed(base, speed);
513 void i2c_init(int speed, int unused)
515 bus_i2c_init(get_base(), speed, unused, NULL, NULL);
521 int i2c_set_bus_speed(unsigned int speed)
523 return bus_i2c_set_bus_speed(get_base(), speed);
529 unsigned int i2c_get_bus_speed(void)
531 return bus_i2c_get_bus_speed(get_base());