2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/errno.h>
49 #define I2CR_IEN (1 << 7)
50 #define I2CR_IIEN (1 << 6)
51 #define I2CR_MSTA (1 << 5)
52 #define I2CR_MTX (1 << 4)
53 #define I2CR_TX_NO_AK (1 << 3)
54 #define I2CR_RSTA (1 << 2)
56 #define I2SR_ICF (1 << 7)
57 #define I2SR_IBB (1 << 5)
58 #define I2SR_IAL (1 << 4)
59 #define I2SR_IIF (1 << 1)
60 #define I2SR_RX_NO_AK (1 << 0)
62 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
63 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
66 static u16 i2c_clk_div[50][2] = {
67 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
68 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
69 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
70 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
71 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
72 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
73 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
74 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
75 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
76 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
77 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
78 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
79 { 3072, 0x1E }, { 3840, 0x1F }
83 * Calculate and set proper clock divider
85 static uint8_t i2c_imx_get_clk(unsigned int rate)
87 unsigned int i2c_clk_rate;
91 #if defined(CONFIG_MX31)
92 struct clock_control_regs *sc_regs =
93 (struct clock_control_regs *)CCM_BASE;
95 /* start the required I2C clock */
96 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
100 /* Divider value calculation */
101 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
102 div = (i2c_clk_rate + rate - 1) / rate;
103 if (div < i2c_clk_div[0][0])
105 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
106 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
108 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
111 /* Store divider value */
118 static int bus_i2c_set_bus_speed(void *base, int speed)
120 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
121 u8 clk_idx = i2c_imx_get_clk(speed);
122 u8 idx = i2c_clk_div[clk_idx][1];
124 /* Store divider value */
125 writeb(idx, &i2c_regs->ifdr);
128 writeb(0, &i2c_regs->i2cr);
129 writeb(0, &i2c_regs->i2sr);
136 static unsigned int bus_i2c_get_bus_speed(void *base)
138 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
139 u8 clk_idx = readb(&i2c_regs->ifdr);
142 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
145 return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
148 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
149 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
150 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
152 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
156 ulong start_time = get_timer(0);
158 sr = readb(&i2c_regs->i2sr);
160 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
161 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
162 __func__, sr, readb(&i2c_regs->i2cr), state);
165 if ((sr & (state >> 8)) == (unsigned char)state)
168 elapsed = get_timer(start_time);
169 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
172 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
173 sr, readb(&i2c_regs->i2cr), state);
177 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
181 writeb(0, &i2c_regs->i2sr);
182 writeb(byte, &i2c_regs->i2dr);
183 ret = wait_for_sr_state(i2c_regs, ST_IIF);
186 if (ret & I2SR_RX_NO_AK)
192 * Stop I2C transaction
194 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
197 unsigned int temp = readb(&i2c_regs->i2cr);
199 temp &= ~(I2CR_MSTA | I2CR_MTX);
200 writeb(temp, &i2c_regs->i2cr);
201 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
203 printf("%s:trigger stop failed\n", __func__);
207 * Send start signal, chip address and
208 * write register address
210 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
211 uchar chip, uint addr, int alen)
216 /* Enable I2C controller */
217 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
218 writeb(I2CR_IEN, &i2c_regs->i2cr);
219 /* Wait for controller to be stable */
222 if (readb(&i2c_regs->iadr) == (chip << 1))
223 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
224 writeb(0, &i2c_regs->i2sr);
225 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
229 /* Start I2C transaction */
230 temp = readb(&i2c_regs->i2cr);
232 writeb(temp, &i2c_regs->i2cr);
234 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
238 temp |= I2CR_MTX | I2CR_TX_NO_AK;
239 writeb(temp, &i2c_regs->i2cr);
241 /* write slave address */
242 ret = tx_byte(i2c_regs, chip << 1);
247 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
254 static int i2c_idle_bus(void *base);
256 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
257 uchar chip, uint addr, int alen)
261 for (retry = 0; retry < 3; retry++) {
262 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
265 i2c_imx_stop(i2c_regs);
269 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
271 if (ret != -ERESTART)
272 writeb(0, &i2c_regs->i2cr); /* Disable controller */
274 if (i2c_idle_bus(i2c_regs) < 0)
277 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
282 * Read data from I2C device
284 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
290 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
292 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
296 temp = readb(&i2c_regs->i2cr);
298 writeb(temp, &i2c_regs->i2cr);
300 ret = tx_byte(i2c_regs, (chip << 1) | 1);
302 i2c_imx_stop(i2c_regs);
306 /* setup bus to read data */
307 temp = readb(&i2c_regs->i2cr);
308 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
310 temp |= I2CR_TX_NO_AK;
311 writeb(temp, &i2c_regs->i2cr);
312 writeb(0, &i2c_regs->i2sr);
313 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
316 for (i = 0; i < len; i++) {
317 ret = wait_for_sr_state(i2c_regs, ST_IIF);
319 i2c_imx_stop(i2c_regs);
324 * It must generate STOP before read I2DR to prevent
325 * controller from generating another clock cycle
327 if (i == (len - 1)) {
328 i2c_imx_stop(i2c_regs);
329 } else if (i == (len - 2)) {
330 temp = readb(&i2c_regs->i2cr);
331 temp |= I2CR_TX_NO_AK;
332 writeb(temp, &i2c_regs->i2cr);
334 writeb(0, &i2c_regs->i2sr);
335 buf[i] = readb(&i2c_regs->i2dr);
337 i2c_imx_stop(i2c_regs);
342 * Write data to I2C device
344 int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
345 const uchar *buf, int len)
349 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
351 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
355 for (i = 0; i < len; i++) {
356 ret = tx_byte(i2c_regs, buf[i]);
360 i2c_imx_stop(i2c_regs);
367 int (*idle_bus_fn)(void *p);
371 unsigned curr_i2c_bus;
372 struct i2c_parms i2c_data[3];
376 * For SPL boot some boards need i2c before SDRAM is initialized so force
377 * variables to live in SRAM
379 static struct sram_data __attribute__((section(".data"))) srdata;
383 #ifdef CONFIG_SYS_I2C_BASE
384 #ifdef CONFIG_I2C_MULTI_BUS
385 void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
389 return (void *)CONFIG_SYS_I2C_BASE;
390 #elif defined(CONFIG_I2C_MULTI_BUS)
391 return srdata.i2c_data[srdata.curr_i2c_bus].base;
393 return srdata.i2c_data[0].base;
397 static struct i2c_parms *i2c_get_parms(void *base)
400 struct i2c_parms *p = srdata.i2c_data;
401 while (i < ARRAY_SIZE(srdata.i2c_data)) {
407 printf("Invalid I2C base: %p\n", base);
411 static int i2c_idle_bus(void *base)
413 struct i2c_parms *p = i2c_get_parms(base);
414 if (p && p->idle_bus_fn)
415 return p->idle_bus_fn(p->idle_bus_data);
419 #ifdef CONFIG_I2C_MULTI_BUS
420 unsigned int i2c_get_bus_num(void)
422 return srdata.curr_i2c_bus;
425 int i2c_set_bus_num(unsigned bus_idx)
427 if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
429 if (!srdata.i2c_data[bus_idx].base)
431 srdata.curr_i2c_bus = bus_idx;
436 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
438 return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
441 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
443 return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
447 * Test if a chip at a given address responds (probe the chip)
449 int i2c_probe(uchar chip)
451 return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
454 void bus_i2c_init(void *base, int speed, int unused,
455 int (*idle_bus_fn)(void *p), void *idle_bus_data)
458 struct i2c_parms *p = srdata.i2c_data;
462 if (!p->base || (p->base == base)) {
465 p->idle_bus_fn = idle_bus_fn;
466 p->idle_bus_data = idle_bus_data;
472 if (i >= ARRAY_SIZE(srdata.i2c_data))
475 bus_i2c_set_bus_speed(base, speed);
481 void i2c_init(int speed, int unused)
483 bus_i2c_init(get_base(), speed, unused, NULL, NULL);
489 int i2c_set_bus_speed(unsigned int speed)
491 return bus_i2c_set_bus_speed(get_base(), speed);
497 unsigned int i2c_get_bus_speed(void)
499 return bus_i2c_get_bus_speed(get_base());