2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #if defined(CONFIG_HARD_I2C)
38 #include <asm/arch/clock.h>
39 #include <asm/arch/imx-regs.h>
49 #define I2CR_IEN (1 << 7)
50 #define I2CR_IIEN (1 << 6)
51 #define I2CR_MSTA (1 << 5)
52 #define I2CR_MTX (1 << 4)
53 #define I2CR_TX_NO_AK (1 << 3)
54 #define I2CR_RSTA (1 << 2)
56 #define I2SR_ICF (1 << 7)
57 #define I2SR_IBB (1 << 5)
58 #define I2SR_IIF (1 << 1)
59 #define I2SR_RX_NO_AK (1 << 0)
61 #if defined(CONFIG_SYS_I2C_MX31_PORT1)
62 #define I2C_BASE 0x43f80000
63 #define I2C_CLK_OFFSET 26
64 #elif defined (CONFIG_SYS_I2C_MX31_PORT2)
65 #define I2C_BASE 0x43f98000
66 #define I2C_CLK_OFFSET 28
67 #elif defined (CONFIG_SYS_I2C_MX31_PORT3)
68 #define I2C_BASE 0x43f84000
69 #define I2C_CLK_OFFSET 30
70 #elif defined(CONFIG_SYS_I2C_MX53_PORT1)
71 #define I2C_BASE I2C1_BASE_ADDR
72 #elif defined(CONFIG_SYS_I2C_MX53_PORT2)
73 #define I2C_BASE I2C2_BASE_ADDR
74 #elif defined(CONFIG_SYS_I2C_MX35_PORT1)
75 #define I2C_BASE I2C_BASE_ADDR
77 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
80 #define I2C_MAX_TIMEOUT 10000
82 static u16 i2c_clk_div[50][2] = {
83 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
84 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
85 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
86 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
87 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
88 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
89 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
90 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
91 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
92 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
93 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
94 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
95 { 3072, 0x1E }, { 3840, 0x1F }
101 * Calculate and set proper clock divider
103 static void i2c_imx_set_clk(unsigned int rate)
105 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
106 unsigned int i2c_clk_rate;
110 #if defined(CONFIG_MX31)
111 struct clock_control_regs *sc_regs =
112 (struct clock_control_regs *)CCM_BASE;
114 /* start the required I2C clock */
115 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
119 /* Divider value calculation */
120 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
121 div = (i2c_clk_rate + rate - 1) / rate;
122 if (div < i2c_clk_div[0][0])
124 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
125 i = ARRAY_SIZE(i2c_clk_div) - 1;
127 for (i = 0; i2c_clk_div[i][0] < div; i++)
130 /* Store divider value */
131 clk_idx = i2c_clk_div[i][1];
132 writeb(clk_idx, &i2c_regs->ifdr);
136 * Reset I2C Controller
140 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
142 writeb(0, &i2c_regs->i2cr); /* Reset module */
143 writeb(0, &i2c_regs->i2sr);
149 void i2c_init(int speed, int unused)
151 i2c_imx_set_clk(speed);
156 * Wait for bus to be busy (or free if for_busy = 0)
158 * for_busy = 1: Wait for IBB to be asserted
159 * for_busy = 0: Wait for IBB to be de-asserted
161 int i2c_imx_bus_busy(int for_busy)
163 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
166 int timeout = I2C_MAX_TIMEOUT;
169 temp = readb(&i2c_regs->i2sr);
171 if (for_busy && (temp & I2SR_IBB))
173 if (!for_busy && !(temp & I2SR_IBB))
183 * Wait for transaction to complete
185 int i2c_imx_trx_complete(void)
187 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
188 int timeout = I2C_MAX_TIMEOUT;
191 if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
192 writeb(0, &i2c_regs->i2sr);
203 * Check if the transaction was ACKed
205 int i2c_imx_acked(void)
207 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
209 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
213 * Start the controller
215 int i2c_imx_start(void)
217 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
218 unsigned int temp = 0;
221 writeb(clk_idx, &i2c_regs->ifdr);
223 /* Enable I2C controller */
224 writeb(0, &i2c_regs->i2sr);
225 writeb(I2CR_IEN, &i2c_regs->i2cr);
227 /* Wait controller to be stable */
230 /* Start I2C transaction */
231 temp = readb(&i2c_regs->i2cr);
233 writeb(temp, &i2c_regs->i2cr);
235 result = i2c_imx_bus_busy(1);
239 temp |= I2CR_MTX | I2CR_TX_NO_AK;
240 writeb(temp, &i2c_regs->i2cr);
246 * Stop the controller
248 void i2c_imx_stop(void)
250 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
251 unsigned int temp = 0;
253 /* Stop I2C transaction */
254 temp = readb(&i2c_regs->i2cr);
255 temp |= ~(I2CR_MSTA | I2CR_MTX);
256 writeb(temp, &i2c_regs->i2cr);
260 /* Disable I2C controller */
261 writeb(0, &i2c_regs->i2cr);
265 * Set chip address and access mode
267 * read = 1: READ access
268 * read = 0: WRITE access
270 int i2c_imx_set_chip_addr(uchar chip, int read)
272 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
275 writeb((chip << 1) | read, &i2c_regs->i2dr);
277 ret = i2c_imx_trx_complete();
281 ret = i2c_imx_acked();
289 * Write register address
291 int i2c_imx_set_reg_addr(uint addr, int alen)
293 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
297 for (i = 0; i < (8 * alen); i += 8) {
298 writeb((addr >> i) & 0xff, &i2c_regs->i2dr);
300 ret = i2c_imx_trx_complete();
304 ret = i2c_imx_acked();
313 * Try if a chip add given address responds (probe the chip)
315 int i2c_probe(uchar chip)
319 ret = i2c_imx_start();
323 ret = i2c_imx_set_chip_addr(chip, 0);
333 * Read data from I2C device
335 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
337 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
342 ret = i2c_imx_start();
346 /* write slave address */
347 ret = i2c_imx_set_chip_addr(chip, 0);
351 ret = i2c_imx_set_reg_addr(addr, alen);
355 temp = readb(&i2c_regs->i2cr);
357 writeb(temp, &i2c_regs->i2cr);
359 ret = i2c_imx_set_chip_addr(chip, 1);
363 /* setup bus to read data */
364 temp = readb(&i2c_regs->i2cr);
365 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
367 temp |= I2CR_TX_NO_AK;
368 writeb(temp, &i2c_regs->i2cr);
369 readb(&i2c_regs->i2dr);
372 for (i = 0; i < len; i++) {
373 ret = i2c_imx_trx_complete();
378 * It must generate STOP before read I2DR to prevent
379 * controller from generating another clock cycle
381 if (i == (len - 1)) {
382 temp = readb(&i2c_regs->i2cr);
383 temp &= ~(I2CR_MSTA | I2CR_MTX);
384 writeb(temp, &i2c_regs->i2cr);
386 } else if (i == (len - 2)) {
387 temp = readb(&i2c_regs->i2cr);
388 temp |= I2CR_TX_NO_AK;
389 writeb(temp, &i2c_regs->i2cr);
392 buf[i] = readb(&i2c_regs->i2dr);
401 * Write data to I2C device
403 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
405 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
409 ret = i2c_imx_start();
413 /* write slave address */
414 ret = i2c_imx_set_chip_addr(chip, 0);
418 ret = i2c_imx_set_reg_addr(addr, alen);
422 for (i = 0; i < len; i++) {
423 writeb(buf[i], &i2c_regs->i2dr);
425 ret = i2c_imx_trx_complete();
429 ret = i2c_imx_acked();
438 #endif /* CONFIG_HARD_I2C */