2 * i2c driver for Freescale mx31
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #if defined(CONFIG_HARD_I2C)
30 #if defined(CONFIG_MX31)
31 #include <asm/arch/mx31.h>
32 #include <asm/arch/mx31-regs.h>
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/clock.h>
44 #define I2CR_IEN (1 << 7)
45 #define I2CR_IIEN (1 << 6)
46 #define I2CR_MSTA (1 << 5)
47 #define I2CR_MTX (1 << 4)
48 #define I2CR_TX_NO_AK (1 << 3)
49 #define I2CR_RSTA (1 << 2)
51 #define I2SR_ICF (1 << 7)
52 #define I2SR_IBB (1 << 5)
53 #define I2SR_IIF (1 << 1)
54 #define I2SR_RX_NO_AK (1 << 0)
56 #if defined(CONFIG_SYS_I2C_MX31_PORT1)
57 #define I2C_BASE 0x43f80000
58 #define I2C_CLK_OFFSET 26
59 #elif defined (CONFIG_SYS_I2C_MX31_PORT2)
60 #define I2C_BASE 0x43f98000
61 #define I2C_CLK_OFFSET 28
62 #elif defined (CONFIG_SYS_I2C_MX31_PORT3)
63 #define I2C_BASE 0x43f84000
64 #define I2C_CLK_OFFSET 30
65 #elif defined(CONFIG_SYS_I2C_MX53_PORT1)
66 #define I2C_BASE I2C1_BASE_ADDR
67 #elif defined(CONFIG_SYS_I2C_MX53_PORT2)
68 #define I2C_BASE I2C2_BASE_ADDR
69 #elif defined(CONFIG_SYS_I2C_MX35_PORT1)
70 #define I2C_BASE I2C_BASE_ADDR
72 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
75 #define I2C_MAX_TIMEOUT 10000
76 #define I2C_MAX_RETRIES 3
78 static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
79 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
80 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
82 static inline void i2c_reset(void)
84 writew(0, I2C_BASE + I2CR); /* Reset module */
85 writew(0, I2C_BASE + I2SR);
86 writew(I2CR_IEN, I2C_BASE + I2CR);
89 void i2c_init(int speed, int unused)
94 #if defined(CONFIG_MX31)
95 struct clock_control_regs *sc_regs =
96 (struct clock_control_regs *)CCM_BASE;
98 freq = mx31_get_ipg_clk();
99 /* start the required I2C clock */
100 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
103 freq = mxc_get_clock(MXC_IPG_PERCLK);
106 for (i = 0; i < 0x1f; i++)
107 if (freq / div[i] <= speed)
110 debug("%s: speed: %d\n", __func__, speed);
112 writew(i, I2C_BASE + IFDR);
116 static int wait_idle(void)
118 int timeout = I2C_MAX_TIMEOUT;
120 while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) {
121 writew(0, I2C_BASE + I2SR);
124 return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB));
127 static int wait_busy(void)
129 int timeout = I2C_MAX_TIMEOUT;
131 while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
133 writew(0, I2C_BASE + I2SR); /* clear interrupt */
138 static int wait_complete(void)
140 int timeout = I2C_MAX_TIMEOUT;
142 while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) {
143 writew(0, I2C_BASE + I2SR);
148 writew(0, I2C_BASE + I2SR); /* clear interrupt */
154 static int tx_byte(u8 byte)
156 writew(byte, I2C_BASE + I2DR);
158 if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
163 static int rx_byte(int last)
165 if (!wait_complete())
169 writew(I2CR_IEN, I2C_BASE + I2CR);
171 return readw(I2C_BASE + I2DR);
174 int i2c_probe(uchar chip)
178 writew(0, I2C_BASE + I2CR); /* Reset module */
179 writew(I2CR_IEN, I2C_BASE + I2CR);
181 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
182 ret = tx_byte(chip << 1);
183 writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR);
188 static int i2c_addr(uchar chip, uint addr, int alen)
191 for (retry = 0; retry < 3; retry++) {
195 for (i = 0; i < I2C_MAX_TIMEOUT; i++)
198 if (retry >= I2C_MAX_RETRIES) {
199 debug("%s:bus is busy(%x)\n",
200 __func__, readw(I2C_BASE + I2SR));
203 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
206 debug("%s:trigger start fail(%x)\n",
207 __func__, readw(I2C_BASE + I2SR));
211 if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
212 debug("%s:chip address cycle fail(%x)\n",
213 __func__, readw(I2C_BASE + I2SR));
217 if (tx_byte((addr >> (alen * 8)) & 0xff) ||
218 (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
219 debug("%s:device address cycle fail(%x)\n",
220 __func__, readw(I2C_BASE + I2SR));
226 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
228 int timeout = I2C_MAX_TIMEOUT;
231 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
232 __func__, chip, addr, alen, len);
234 if (i2c_addr(chip, addr, alen)) {
235 printf("i2c_addr failed\n");
239 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR);
241 if (tx_byte(chip << 1 | 1))
244 writew(I2CR_IEN | I2CR_MSTA |
245 ((len == 1) ? I2CR_TX_NO_AK : 0),
248 ret = readw(I2C_BASE + I2DR);
251 ret = rx_byte(len == 0);
256 writew(I2CR_IEN | I2CR_MSTA |
261 writew(I2CR_IEN, I2C_BASE + I2CR);
263 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
269 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
271 int timeout = I2C_MAX_TIMEOUT;
272 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
273 __func__, chip, addr, alen, len);
275 if (i2c_addr(chip, addr, alen))
282 writew(I2CR_IEN, I2C_BASE + I2CR);
284 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
290 #endif /* CONFIG_HARD_I2C */