git.sur5r.net Git - u-boot/blob - drivers/i2c/mxs_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX28 I2C Driver
   4  *
   5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  * on behalf of DENX Software Engineering GmbH
   7  *
   8  * Partly based on Linux kernel i2c-mxs.c driver:
   9  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
  10  *
  11  * Which was based on a (non-working) driver which was:
  12  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  13  */
  14
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <i2c.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/sys_proto.h>
  23
  24 #define MXS_I2C_MAX_TIMEOUT     1000000
  25
  26 static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
  27 {
  28         if (adap->hwadapnr == 0)
  29                 return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  30         else
  31                 return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
  32 }
  33
  34 static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
  35 {
  36         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  37         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  38         uint32_t timing0;
  39
  40         timing0 = readl(&i2c_regs->hw_i2c_timing0);
  41         /*
  42          * This is a reverse version of the algorithm presented in
  43          * i2c_set_bus_speed(). Please refer there for details.
  44          */
  45         return clk / ((((timing0 >> 16) - 3) * 2) + 38);
  46 }
  47
  48 static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  49 {
  50         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  51         /*
  52          * The timing derivation algorithm. There is no documentation for this
  53          * algorithm available, it was derived by using the scope and fiddling
  54          * with constants until the result observed on the scope was good enough
  55          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
  56          * possible to assume the algorithm works for other frequencies as well.
  57          *
  58          * Note it was necessary to cap the frequency on both ends as it's not
  59          * possible to configure completely arbitrary frequency for the I2C bus
  60          * clock.
  61          */
  62         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  63         uint32_t base = ((clk / speed) - 38) / 2;
  64         uint16_t high_count = base + 3;
  65         uint16_t low_count = base - 3;
  66         uint16_t rcv_count = (high_count * 3) / 4;
  67         uint16_t xmit_count = low_count / 4;
  68
  69         if (speed > 540000) {
  70                 printf("MXS I2C: Speed too high (%d Hz)\n", speed);
  71                 return -EINVAL;
  72         }
  73
  74         if (speed < 12000) {
  75                 printf("MXS I2C: Speed too low (%d Hz)\n", speed);
  76                 return -EINVAL;
  77         }
  78
  79         writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
  80         writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
  81
  82         writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
  83                 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
  84                 &i2c_regs->hw_i2c_timing2);
  85
  86         return 0;
  87 }
  88
  89 static void mxs_i2c_reset(struct i2c_adapter *adap)
  90 {
  91         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  92         int ret;
  93         int speed = mxs_i2c_get_bus_speed(adap);
  94
  95         ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
  96         if (ret) {
  97                 debug("MXS I2C: Block reset timeout\n");
  98                 return;
  99         }
 100
 101         writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
 102                 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 103                 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
 104                 &i2c_regs->hw_i2c_ctrl1_clr);
 105
 106         writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
 107
 108         mxs_i2c_set_bus_speed(adap, speed);
 109 }
 110
 111 static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
 112 {
 113         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 114
 115         writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
 116                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 117                 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
 118                 &i2c_regs->hw_i2c_queuecmd);
 119
 120         writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
 121
 122         writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
 123                 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
 124                 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
 125
 126         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 127 }
 128
 129 static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 130                          int alen, uchar *buf, int blen, int stop)
 131 {
 132         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 133         uint32_t data, tmp;
 134         int i, remain, off;
 135         int timeout = MXS_I2C_MAX_TIMEOUT;
 136
 137         if ((alen > 4) || (alen == 0)) {
 138                 debug("MXS I2C: Invalid address length\n");
 139                 return -EINVAL;
 140         }
 141
 142         if (stop)
 143                 stop = I2C_QUEUECMD_POST_SEND_STOP;
 144
 145         writel(I2C_QUEUECMD_PRE_SEND_START |
 146                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 147                 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
 148                 &i2c_regs->hw_i2c_queuecmd);
 149
 150         data = (chip << 1) << 24;
 151
 152         for (i = 0; i < alen; i++) {
 153                 data >>= 8;
 154                 data |= ((char *)&addr)[alen - i - 1] << 24;
 155                 if ((i & 3) == 2)
 156                         writel(data, &i2c_regs->hw_i2c_data);
 157         }
 158
 159         off = i;
 160         for (; i < off + blen; i++) {
 161                 data >>= 8;
 162                 data |= buf[i - off] << 24;
 163                 if ((i & 3) == 2)
 164                         writel(data, &i2c_regs->hw_i2c_data);
 165         }
 166
 167         remain = 24 - ((i & 3) * 8);
 168         if (remain)
 169                 writel(data >> remain, &i2c_regs->hw_i2c_data);
 170
 171         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 172
 173         while (--timeout) {
 174                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 175                 if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
 176                         break;
 177         }
 178
 179         if (!timeout) {
 180                 debug("MXS I2C: Failed transmitting data!\n");
 181                 return -EINVAL;
 182         }
 183
 184         return 0;
 185 }
 186
 187 static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
 188 {
 189         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 190         uint32_t tmp;
 191         int timeout = MXS_I2C_MAX_TIMEOUT;
 192
 193         for (;;) {
 194                 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
 195                 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
 196                         debug("MXS I2C: No slave ACK\n");
 197                         goto err;
 198                 }
 199
 200                 if (tmp & (
 201                         I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 202                         I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
 203                         debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
 204                         goto err;
 205                 }
 206
 207                 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
 208                         break;
 209
 210                 if (!timeout--) {
 211                         debug("MXS I2C: Operation timed out\n");
 212                         goto err;
 213                 }
 214
 215                 udelay(1);
 216         }
 217
 218         return 0;
 219
 220 err:
 221         mxs_i2c_reset(adap);
 222         return 1;
 223 }
 224
 225 static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
 226                            uint addr, int alen, uint8_t *buffer,
 227                            int len)
 228 {
 229         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 230         uint32_t tmp = 0;
 231         int timeout = MXS_I2C_MAX_TIMEOUT;
 232         int ret;
 233         int i;
 234
 235         ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
 236         if (ret) {
 237                 debug("MXS I2C: Failed writing address\n");
 238                 return ret;
 239         }
 240
 241         ret = mxs_i2c_wait_for_ack(adap);
 242         if (ret) {
 243                 debug("MXS I2C: Failed writing address\n");
 244                 return ret;
 245         }
 246
 247         mxs_i2c_setup_read(adap, chip, len);
 248         ret = mxs_i2c_wait_for_ack(adap);
 249         if (ret) {
 250                 debug("MXS I2C: Failed reading address\n");
 251                 return ret;
 252         }
 253
 254         for (i = 0; i < len; i++) {
 255                 if (!(i & 3)) {
 256                         while (--timeout) {
 257                                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 258                                 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
 259                                         break;
 260                         }
 261
 262                         if (!timeout) {
 263                                 debug("MXS I2C: Failed receiving data!\n");
 264                                 return -ETIMEDOUT;
 265                         }
 266
 267                         tmp = readl(&i2c_regs->hw_i2c_queuedata);
 268                 }
 269                 buffer[i] = tmp & 0xff;
 270                 tmp >>= 8;
 271         }
 272
 273         return 0;
 274 }
 275
 276 static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
 277                             uint addr, int alen, uint8_t *buffer,
 278                             int len)
 279 {
 280         int ret;
 281         ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
 282         if (ret) {
 283                 debug("MXS I2C: Failed writing address\n");
 284                 return ret;
 285         }
 286
 287         ret = mxs_i2c_wait_for_ack(adap);
 288         if (ret)
 289                 debug("MXS I2C: Failed writing address\n");
 290
 291         return ret;
 292 }
 293
 294 static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 295 {
 296         int ret;
 297         ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
 298         if (!ret)
 299                 ret = mxs_i2c_wait_for_ack(adap);
 300         mxs_i2c_reset(adap);
 301         return ret;
 302 }
 303
 304 static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 305 {
 306         mxs_i2c_reset(adap);
 307         mxs_i2c_set_bus_speed(adap, speed);
 308
 309         return;
 310 }
 311
 312 U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
 313                          mxs_i2c_if_read, mxs_i2c_if_write,
 314                          mxs_i2c_set_bus_speed,
 315                          CONFIG_SYS_I2C_SPEED, 0, 0)
 316 U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
 317                          mxs_i2c_if_read, mxs_i2c_if_write,
 318                          mxs_i2c_set_bus_speed,
 319                          CONFIG_SYS_I2C_SPEED, 0, 1)