git.sur5r.net Git - u-boot/blob - drivers/i2c/mxs_i2c.c

   1 /*
   2  * Freescale i.MX28 I2C Driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Partly based on Linux kernel i2c-mxs.c driver:
   8  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   9  *
  10  * Which was based on a (non-working) driver which was:
  11  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <malloc.h>
  18 #include <i2c.h>
  19 #include <asm/errno.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/sys_proto.h>
  24
  25 #define MXS_I2C_MAX_TIMEOUT     1000000
  26
  27 static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
  28 {
  29         if (adap->hwadapnr == 0)
  30                 return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  31         else
  32                 return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
  33 }
  34
  35 static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
  36 {
  37         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  38         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  39         uint32_t timing0;
  40
  41         timing0 = readl(&i2c_regs->hw_i2c_timing0);
  42         /*
  43          * This is a reverse version of the algorithm presented in
  44          * i2c_set_bus_speed(). Please refer there for details.
  45          */
  46         return clk / ((((timing0 >> 16) - 3) * 2) + 38);
  47 }
  48
  49 static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  50 {
  51         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  52         /*
  53          * The timing derivation algorithm. There is no documentation for this
  54          * algorithm available, it was derived by using the scope and fiddling
  55          * with constants until the result observed on the scope was good enough
  56          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
  57          * possible to assume the algorithm works for other frequencies as well.
  58          *
  59          * Note it was necessary to cap the frequency on both ends as it's not
  60          * possible to configure completely arbitrary frequency for the I2C bus
  61          * clock.
  62          */
  63         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  64         uint32_t base = ((clk / speed) - 38) / 2;
  65         uint16_t high_count = base + 3;
  66         uint16_t low_count = base - 3;
  67         uint16_t rcv_count = (high_count * 3) / 4;
  68         uint16_t xmit_count = low_count / 4;
  69
  70         if (speed > 540000) {
  71                 printf("MXS I2C: Speed too high (%d Hz)\n", speed);
  72                 return -EINVAL;
  73         }
  74
  75         if (speed < 12000) {
  76                 printf("MXS I2C: Speed too low (%d Hz)\n", speed);
  77                 return -EINVAL;
  78         }
  79
  80         writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
  81         writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
  82
  83         writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
  84                 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
  85                 &i2c_regs->hw_i2c_timing2);
  86
  87         return 0;
  88 }
  89
  90 static void mxs_i2c_reset(struct i2c_adapter *adap)
  91 {
  92         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  93         int ret;
  94         int speed = mxs_i2c_get_bus_speed(adap);
  95
  96         ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
  97         if (ret) {
  98                 debug("MXS I2C: Block reset timeout\n");
  99                 return;
 100         }
 101
 102         writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
 103                 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 104                 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
 105                 &i2c_regs->hw_i2c_ctrl1_clr);
 106
 107         writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
 108
 109         mxs_i2c_set_bus_speed(adap, speed);
 110 }
 111
 112 static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
 113 {
 114         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 115
 116         writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
 117                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 118                 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
 119                 &i2c_regs->hw_i2c_queuecmd);
 120
 121         writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
 122
 123         writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
 124                 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
 125                 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
 126
 127         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 128 }
 129
 130 static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 131                          int alen, uchar *buf, int blen, int stop)
 132 {
 133         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 134         uint32_t data, tmp;
 135         int i, remain, off;
 136         int timeout = MXS_I2C_MAX_TIMEOUT;
 137
 138         if ((alen > 4) || (alen == 0)) {
 139                 debug("MXS I2C: Invalid address length\n");
 140                 return -EINVAL;
 141         }
 142
 143         if (stop)
 144                 stop = I2C_QUEUECMD_POST_SEND_STOP;
 145
 146         writel(I2C_QUEUECMD_PRE_SEND_START |
 147                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 148                 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
 149                 &i2c_regs->hw_i2c_queuecmd);
 150
 151         data = (chip << 1) << 24;
 152
 153         for (i = 0; i < alen; i++) {
 154                 data >>= 8;
 155                 data |= ((char *)&addr)[alen - i - 1] << 24;
 156                 if ((i & 3) == 2)
 157                         writel(data, &i2c_regs->hw_i2c_data);
 158         }
 159
 160         off = i;
 161         for (; i < off + blen; i++) {
 162                 data >>= 8;
 163                 data |= buf[i - off] << 24;
 164                 if ((i & 3) == 2)
 165                         writel(data, &i2c_regs->hw_i2c_data);
 166         }
 167
 168         remain = 24 - ((i & 3) * 8);
 169         if (remain)
 170                 writel(data >> remain, &i2c_regs->hw_i2c_data);
 171
 172         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 173
 174         while (--timeout) {
 175                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 176                 if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
 177                         break;
 178         }
 179
 180         if (!timeout) {
 181                 debug("MXS I2C: Failed transmitting data!\n");
 182                 return -EINVAL;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
 189 {
 190         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 191         uint32_t tmp;
 192         int timeout = MXS_I2C_MAX_TIMEOUT;
 193
 194         for (;;) {
 195                 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
 196                 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
 197                         debug("MXS I2C: No slave ACK\n");
 198                         goto err;
 199                 }
 200
 201                 if (tmp & (
 202                         I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 203                         I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
 204                         debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
 205                         goto err;
 206                 }
 207
 208                 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
 209                         break;
 210
 211                 if (!timeout--) {
 212                         debug("MXS I2C: Operation timed out\n");
 213                         goto err;
 214                 }
 215
 216                 udelay(1);
 217         }
 218
 219         return 0;
 220
 221 err:
 222         mxs_i2c_reset(adap);
 223         return 1;
 224 }
 225
 226 static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
 227                            uint addr, int alen, uint8_t *buffer,
 228                            int len)
 229 {
 230         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 231         uint32_t tmp = 0;
 232         int timeout = MXS_I2C_MAX_TIMEOUT;
 233         int ret;
 234         int i;
 235
 236         ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
 237         if (ret) {
 238                 debug("MXS I2C: Failed writing address\n");
 239                 return ret;
 240         }
 241
 242         ret = mxs_i2c_wait_for_ack(adap);
 243         if (ret) {
 244                 debug("MXS I2C: Failed writing address\n");
 245                 return ret;
 246         }
 247
 248         mxs_i2c_setup_read(adap, chip, len);
 249         ret = mxs_i2c_wait_for_ack(adap);
 250         if (ret) {
 251                 debug("MXS I2C: Failed reading address\n");
 252                 return ret;
 253         }
 254
 255         for (i = 0; i < len; i++) {
 256                 if (!(i & 3)) {
 257                         while (--timeout) {
 258                                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 259                                 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
 260                                         break;
 261                         }
 262
 263                         if (!timeout) {
 264                                 debug("MXS I2C: Failed receiving data!\n");
 265                                 return -ETIMEDOUT;
 266                         }
 267
 268                         tmp = readl(&i2c_regs->hw_i2c_queuedata);
 269                 }
 270                 buffer[i] = tmp & 0xff;
 271                 tmp >>= 8;
 272         }
 273
 274         return 0;
 275 }
 276
 277 static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
 278                             uint addr, int alen, uint8_t *buffer,
 279                             int len)
 280 {
 281         int ret;
 282         ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
 283         if (ret) {
 284                 debug("MXS I2C: Failed writing address\n");
 285                 return ret;
 286         }
 287
 288         ret = mxs_i2c_wait_for_ack(adap);
 289         if (ret)
 290                 debug("MXS I2C: Failed writing address\n");
 291
 292         return ret;
 293 }
 294
 295 static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 296 {
 297         int ret;
 298         ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
 299         if (!ret)
 300                 ret = mxs_i2c_wait_for_ack(adap);
 301         mxs_i2c_reset(adap);
 302         return ret;
 303 }
 304
 305 static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 306 {
 307         mxs_i2c_reset(adap);
 308         mxs_i2c_set_bus_speed(adap, speed);
 309
 310         return;
 311 }
 312
 313 U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
 314                          mxs_i2c_if_read, mxs_i2c_if_write,
 315                          mxs_i2c_set_bus_speed,
 316                          CONFIG_SYS_I2C_SPEED, 0, 0)
 317 U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
 318                          mxs_i2c_if_read, mxs_i2c_if_write,
 319                          mxs_i2c_set_bus_speed,
 320                          CONFIG_SYS_I2C_SPEED, 0, 1)