4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 #define I2C_TIMEOUT 10
32 static void wait_for_bb (void);
33 static u16 wait_for_pin (void);
34 static void flush_fifo(void);
36 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
38 static unsigned int bus_initialized[I2C_BUS_MAX];
39 static unsigned int current_bus;
41 void i2c_init (int speed, int slaveadd)
43 DECLARE_GLOBAL_DATA_PTR;
44 int psc, fsscll, fssclh;
45 int hsscll = 0, hssclh = 0;
47 int timeout = I2C_TIMEOUT;
49 /* Only handle standard, fast and high speeds */
50 if ((speed != OMAP_I2C_STANDARD) &&
51 (speed != OMAP_I2C_FAST_MODE) &&
52 (speed != OMAP_I2C_HIGH_SPEED)) {
53 printf("Error : I2C unsupported speed %d\n", speed);
57 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
59 if (psc < I2C_PSC_MIN) {
60 printf("Error : I2C unsupported prescalar %d\n", psc);
64 if (speed == OMAP_I2C_HIGH_SPEED) {
67 /* For first phase of HS mode */
68 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
69 (2 * OMAP_I2C_FAST_MODE);
71 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
72 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
73 if (((fsscll < 0) || (fssclh < 0)) ||
74 ((fsscll > 255) || (fssclh > 255))) {
75 printf("Error : I2C initializing first phase clock\n");
79 /* For second phase of HS mode */
80 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
82 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
83 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
84 if (((fsscll < 0) || (fssclh < 0)) ||
85 ((fsscll > 255) || (fssclh > 255))) {
86 printf("Error : I2C initializing second phase clock\n");
90 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
91 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
94 /* Standard and fast speed */
95 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
97 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
98 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
99 if (((fsscll < 0) || (fssclh < 0)) ||
100 ((fsscll > 255) || (fssclh > 255))) {
101 printf("Error : I2C initializing clock\n");
105 scll = (unsigned int)fsscll;
106 sclh = (unsigned int)fssclh;
109 if (readw (&i2c_base->con) & I2C_CON_EN) {
110 writew (0, &i2c_base->con);
114 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
117 writew(I2C_CON_EN, &i2c_base->con);
118 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
120 printf("ERROR: Timeout in soft-reset\n");
126 writew(0, &i2c_base->con);
127 writew(psc, &i2c_base->psc);
128 writew(scll, &i2c_base->scll);
129 writew(sclh, &i2c_base->sclh);
132 writew (slaveadd, &i2c_base->oa);
133 writew (I2C_CON_EN, &i2c_base->con);
135 /* have to enable intrrupts or OMAP i2c module doesn't work */
136 writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
137 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
140 writew (0xFFFF, &i2c_base->stat);
141 writew (0, &i2c_base->cnt);
143 if (gd->flags & GD_FLG_RELOC)
144 bus_initialized[current_bus] = 1;
147 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
152 /* wait until bus not busy */
156 writew (1, &i2c_base->cnt);
157 /* set slave address */
158 writew (devaddr, &i2c_base->sa);
159 /* no stop bit needed here */
160 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
162 status = wait_for_pin ();
164 if (status & I2C_STAT_XRDY) {
165 /* Important: have to use byte access */
166 writeb (regoffset, &i2c_base->data);
168 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
176 writew (I2C_CON_EN, &i2c_base->con);
177 while (readw(&i2c_base->stat) &
178 (I2C_STAT_XRDY | I2C_STAT_ARDY)) {
180 /* Have to clear pending interrupt to clear I2C_STAT */
181 writew (0xFFFF, &i2c_base->stat);
184 /* set slave address */
185 writew (devaddr, &i2c_base->sa);
186 /* read one byte from slave */
187 writew (1, &i2c_base->cnt);
188 /* need stop bit here */
189 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
192 status = wait_for_pin ();
193 if (status & I2C_STAT_RRDY) {
194 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
195 defined(CONFIG_OMAP44XX)
196 *value = readb (&i2c_base->data);
198 *value = readw (&i2c_base->data);
206 writew (I2C_CON_EN, &i2c_base->con);
207 while (readw (&i2c_base->stat) &
208 (I2C_STAT_RRDY | I2C_STAT_ARDY)) {
210 writew (0xFFFF, &i2c_base->stat);
215 writew (0xFFFF, &i2c_base->stat);
216 writew (0, &i2c_base->cnt);
220 static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
225 /* wait until bus not busy */
229 writew (2, &i2c_base->cnt);
230 /* set slave address */
231 writew (devaddr, &i2c_base->sa);
232 /* stop bit needed here */
233 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
234 I2C_CON_STP, &i2c_base->con);
236 /* wait until state change */
237 status = wait_for_pin ();
239 if (status & I2C_STAT_XRDY) {
240 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
241 defined(CONFIG_OMAP44XX)
242 /* send out 1 byte */
243 writeb (regoffset, &i2c_base->data);
244 writew (I2C_STAT_XRDY, &i2c_base->stat);
246 status = wait_for_pin ();
247 if ((status & I2C_STAT_XRDY)) {
248 /* send out next 1 byte */
249 writeb (value, &i2c_base->data);
250 writew (I2C_STAT_XRDY, &i2c_base->stat);
255 /* send out two bytes */
256 writew ((value << 8) + regoffset, &i2c_base->data);
258 /* must have enough delay to allow BB bit to go low */
260 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
270 writew (I2C_CON_EN, &i2c_base->con);
271 while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
273 /* have to read to clear intrrupt */
274 writew (0xFFFF, &i2c_base->stat);
275 if(--eout == 0) /* better leave with error than hang */
280 writew (0xFFFF, &i2c_base->stat);
281 writew (0, &i2c_base->cnt);
285 static void flush_fifo(void)
288 /* note: if you try and read data when its not there or ready
289 * you get a bus error
292 stat = readw(&i2c_base->stat);
293 if(stat == I2C_STAT_RRDY){
294 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
295 defined(CONFIG_OMAP44XX)
296 readb(&i2c_base->data);
298 readw(&i2c_base->data);
300 writew(I2C_STAT_RRDY,&i2c_base->stat);
307 int i2c_probe (uchar chip)
309 int res = 1; /* default = fail */
311 if (chip == readw (&i2c_base->oa)) {
315 /* wait until bus not busy */
318 /* try to read one byte */
319 writew (1, &i2c_base->cnt);
320 /* set slave address */
321 writew (chip, &i2c_base->sa);
322 /* stop bit needed here */
323 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
324 /* enough delay for the NACK bit set */
327 if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
328 res = 0; /* success case */
330 writew(0xFFFF, &i2c_base->stat);
332 writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
333 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
338 writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
339 writew(0xFFFF, &i2c_base->stat);
343 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
348 printf ("I2C read: addr len %d not supported\n", alen);
352 if (addr + len > 256) {
353 printf ("I2C read: address out of range\n");
357 for (i = 0; i < len; i++) {
358 if (i2c_read_byte (chip, addr + i, &buffer[i])) {
359 printf ("I2C read: I/O error\n");
360 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
368 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
373 printf ("I2C read: addr len %d not supported\n", alen);
377 if (addr + len > 256) {
378 printf ("I2C read: address out of range\n");
382 for (i = 0; i < len; i++) {
383 if (i2c_write_byte (chip, addr + i, buffer[i])) {
384 printf ("I2C read: I/O error\n");
385 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
393 static void wait_for_bb (void)
398 writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
399 while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
400 writew (stat, &i2c_base->stat);
405 printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
406 readw (&i2c_base->stat));
408 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
411 static u16 wait_for_pin (void)
418 status = readw (&i2c_base->stat);
420 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
421 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
422 I2C_STAT_AL)) && timeout--);
425 printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
426 readw (&i2c_base->stat));
427 writew(0xFFFF, &i2c_base->stat);
432 int i2c_set_bus_num(unsigned int bus)
434 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
435 printf("Bad bus: %d\n", bus);
441 i2c_base = (struct i2c *)I2C_BASE3;
445 i2c_base = (struct i2c *)I2C_BASE2;
447 i2c_base = (struct i2c *)I2C_BASE1;
451 if(!bus_initialized[current_bus])
452 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
457 int i2c_get_bus_num(void)
459 return (int) current_bus;