]> git.sur5r.net Git - u-boot/blob - drivers/i2c/omap24xx_i2c.c
arm: mvebu: Disable L2 cache before enabling d-cache
[u-boot] / drivers / i2c / omap24xx_i2c.c
1 /*
2  * Basic I2C functions
3  *
4  * Copyright (c) 2004 Texas Instruments
5  *
6  * This package is free software;  you can redistribute it and/or
7  * modify it under the terms of the license found in the file
8  * named COPYING that should have accompanied this file.
9  *
10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13  *
14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15  *
16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17  * Rewritten to fit into the current U-Boot framework
18  *
19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20  *
21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24  * OMAPs and derivatives as well. The only anticipated exception would
25  * be the OMAP2420, which shall require driver modification.
26  * - Rewritten i2c_read to operate correctly with all types of chips
27  *   (old function could not read consistent data from some I2C slaves).
28  * - Optimized i2c_write.
29  * - New i2c_probe, performs write access vs read. The old probe could
30  *   hang the system under certain conditions (e.g. unconfigured pads).
31  * - The read/write/probe functions try to identify unconfigured bus.
32  * - Status functions now read irqstatus_raw as per TRM guidelines
33  *   (except for OMAP243X and OMAP34XX).
34  * - Driver now supports up to I2C5 (OMAP5).
35  *
36  * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
37  * - Added support for set_speed
38  *
39  */
40
41 #include <common.h>
42 #include <i2c.h>
43
44 #include <asm/arch/i2c.h>
45 #include <asm/io.h>
46
47 #include "omap24xx_i2c.h"
48
49 DECLARE_GLOBAL_DATA_PTR;
50
51 #define I2C_TIMEOUT     1000
52
53 /* Absolutely safe for status update at 100 kHz I2C: */
54 #define I2C_WAIT        200
55
56 static int wait_for_bb(struct i2c_adapter *adap);
57 static struct i2c *omap24_get_base(struct i2c_adapter *adap);
58 static u16 wait_for_event(struct i2c_adapter *adap);
59 static void flush_fifo(struct i2c_adapter *adap);
60 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
61 {
62         unsigned int sampleclk, prescaler;
63         int fsscll, fssclh;
64
65         speed <<= 1;
66         prescaler = 0;
67         /*
68          * some divisors may cause a precission loss, but shouldn't
69          * be a big thing, because i2c_clk is then allready very slow.
70          */
71         while (prescaler <= 0xFF) {
72                 sampleclk = I2C_IP_CLK / (prescaler+1);
73
74                 fsscll = sampleclk / speed;
75                 fssclh = fsscll;
76                 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
77                 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
78
79                 if (((fsscll > 0) && (fssclh > 0)) &&
80                     ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
81                     (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
82                         if (pscl)
83                                 *pscl = fsscll;
84                         if (psch)
85                                 *psch = fssclh;
86
87                         return prescaler;
88                 }
89                 prescaler++;
90         }
91         return -1;
92 }
93 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
94 {
95         struct i2c *i2c_base = omap24_get_base(adap);
96         int psc, fsscll = 0, fssclh = 0;
97         int hsscll = 0, hssclh = 0;
98         u32 scll = 0, sclh = 0;
99
100         if (speed >= OMAP_I2C_HIGH_SPEED) {
101                 /* High speed */
102                 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
103                 psc -= 1;
104                 if (psc < I2C_PSC_MIN) {
105                         printf("Error : I2C unsupported prescaler %d\n", psc);
106                         return -1;
107                 }
108
109                 /* For first phase of HS mode */
110                 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
111
112                 fssclh = fsscll;
113
114                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
115                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
116                 if (((fsscll < 0) || (fssclh < 0)) ||
117                     ((fsscll > 255) || (fssclh > 255))) {
118                         puts("Error : I2C initializing first phase clock\n");
119                         return -1;
120                 }
121
122                 /* For second phase of HS mode */
123                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
124
125                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
126                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
127                 if (((fsscll < 0) || (fssclh < 0)) ||
128                     ((fsscll > 255) || (fssclh > 255))) {
129                         puts("Error : I2C initializing second phase clock\n");
130                         return -1;
131                 }
132
133                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
134                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
135
136         } else {
137                 /* Standard and fast speed */
138                 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
139                 if (0 > psc) {
140                         puts("Error : I2C initializing clock\n");
141                         return -1;
142                 }
143         }
144
145         adap->speed     = speed;
146         adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
147         writew(0, &i2c_base->con);
148         writew(psc, &i2c_base->psc);
149         writew(scll, &i2c_base->scll);
150         writew(sclh, &i2c_base->sclh);
151         writew(I2C_CON_EN, &i2c_base->con);
152         writew(0xFFFF, &i2c_base->stat);        /* clear all pending status */
153
154         return 0;
155 }
156
157 static void omap24_i2c_deblock(struct i2c_adapter *adap)
158 {
159         struct i2c *i2c_base = omap24_get_base(adap);
160         int i;
161         u16 systest;
162         u16 orgsystest;
163
164         /* set test mode ST_EN = 1 */
165         orgsystest = readw(&i2c_base->systest);
166         systest = orgsystest;
167         /* enable testmode */
168         systest |= I2C_SYSTEST_ST_EN;
169         writew(systest, &i2c_base->systest);
170         systest &= ~I2C_SYSTEST_TMODE_MASK;
171         systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
172         writew(systest, &i2c_base->systest);
173
174         /* set SCL, SDA  = 1 */
175         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
176         writew(systest, &i2c_base->systest);
177         udelay(10);
178
179         /* toggle scl 9 clocks */
180         for (i = 0; i < 9; i++) {
181                 /* SCL = 0 */
182                 systest &= ~I2C_SYSTEST_SCL_O;
183                 writew(systest, &i2c_base->systest);
184                 udelay(10);
185                 /* SCL = 1 */
186                 systest |= I2C_SYSTEST_SCL_O;
187                 writew(systest, &i2c_base->systest);
188                 udelay(10);
189         }
190
191         /* send stop */
192         systest &= ~I2C_SYSTEST_SDA_O;
193         writew(systest, &i2c_base->systest);
194         udelay(10);
195         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
196         writew(systest, &i2c_base->systest);
197         udelay(10);
198
199         /* restore original mode */
200         writew(orgsystest, &i2c_base->systest);
201 }
202
203 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
204 {
205         struct i2c *i2c_base = omap24_get_base(adap);
206         int timeout = I2C_TIMEOUT;
207         int deblock = 1;
208
209 retry:
210         if (readw(&i2c_base->con) & I2C_CON_EN) {
211                 writew(0, &i2c_base->con);
212                 udelay(50000);
213         }
214
215         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
216         udelay(1000);
217
218         writew(I2C_CON_EN, &i2c_base->con);
219         while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
220                 if (timeout <= 0) {
221                         puts("ERROR: Timeout in soft-reset\n");
222                         return;
223                 }
224                 udelay(1000);
225         }
226
227         if (0 != omap24_i2c_setspeed(adap, speed)) {
228                 printf("ERROR: failed to setup I2C bus-speed!\n");
229                 return;
230         }
231
232         /* own address */
233         writew(slaveadd, &i2c_base->oa);
234
235 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
236         /*
237          * Have to enable interrupts for OMAP2/3, these IPs don't have
238          * an 'irqstatus_raw' register and we shall have to poll 'stat'
239          */
240         writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
241                I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
242 #endif
243         udelay(1000);
244         flush_fifo(adap);
245         writew(0xFFFF, &i2c_base->stat);
246
247         /* Handle possible failed I2C state */
248         if (wait_for_bb(adap))
249                 if (deblock == 1) {
250                         omap24_i2c_deblock(adap);
251                         deblock = 0;
252                         goto retry;
253                 }
254 }
255
256 static void flush_fifo(struct i2c_adapter *adap)
257 {
258         struct i2c *i2c_base = omap24_get_base(adap);
259         u16 stat;
260
261         /*
262          * note: if you try and read data when its not there or ready
263          * you get a bus error
264          */
265         while (1) {
266                 stat = readw(&i2c_base->stat);
267                 if (stat == I2C_STAT_RRDY) {
268                         readb(&i2c_base->data);
269                         writew(I2C_STAT_RRDY, &i2c_base->stat);
270                         udelay(1000);
271                 } else
272                         break;
273         }
274 }
275
276 /*
277  * i2c_probe: Use write access. Allows to identify addresses that are
278  *            write-only (like the config register of dual-port EEPROMs)
279  */
280 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
281 {
282         struct i2c *i2c_base = omap24_get_base(adap);
283         u16 status;
284         int res = 1; /* default = fail */
285
286         if (chip == readw(&i2c_base->oa))
287                 return res;
288
289         /* Wait until bus is free */
290         if (wait_for_bb(adap))
291                 return res;
292
293         /* No data transfer, slave addr only */
294         writew(chip, &i2c_base->sa);
295         /* Stop bit needed here */
296         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
297                I2C_CON_STP, &i2c_base->con);
298
299         status = wait_for_event(adap);
300
301         if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
302                 /*
303                  * With current high-level command implementation, notifying
304                  * the user shall flood the console with 127 messages. If
305                  * silent exit is desired upon unconfigured bus, remove the
306                  * following 'if' section:
307                  */
308                 if (status == I2C_STAT_XRDY)
309                         printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
310                                adap->hwadapnr, status);
311
312                 goto pr_exit;
313         }
314
315         /* Check for ACK (!NAK) */
316         if (!(status & I2C_STAT_NACK)) {
317                 res = 0;                                /* Device found */
318                 udelay(adap->waitdelay);/* Required by AM335X in SPL */
319                 /* Abort transfer (force idle state) */
320                 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
321                 udelay(1000);
322                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
323                        I2C_CON_STP, &i2c_base->con);            /* STP */
324         }
325 pr_exit:
326         flush_fifo(adap);
327         writew(0xFFFF, &i2c_base->stat);
328         return res;
329 }
330
331 /*
332  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
333  *           of the requested number of bytes (note that the 'i2c md' command
334  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
335  *           defined in the board config header, this transaction shall be with
336  *           Repeated Start (Sr) between the address and data phases; otherwise
337  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
338  *           The address (reg offset) may be 0, 1 or 2 bytes long.
339  *           Function now reads correctly from chips that return more than one
340  *           byte of data per addressed register (like TI temperature sensors),
341  *           or that do not need a register address at all (such as some clock
342  *           distributors).
343  */
344 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
345                            int alen, uchar *buffer, int len)
346 {
347         struct i2c *i2c_base = omap24_get_base(adap);
348         int i2c_error = 0;
349         u16 status;
350
351         if (alen < 0) {
352                 puts("I2C read: addr len < 0\n");
353                 return 1;
354         }
355         if (len < 0) {
356                 puts("I2C read: data len < 0\n");
357                 return 1;
358         }
359         if (buffer == NULL) {
360                 puts("I2C read: NULL pointer passed\n");
361                 return 1;
362         }
363
364         if (alen > 2) {
365                 printf("I2C read: addr len %d not supported\n", alen);
366                 return 1;
367         }
368
369         if (addr + len > (1 << 16)) {
370                 puts("I2C read: address out of range\n");
371                 return 1;
372         }
373
374         /* Wait until bus not busy */
375         if (wait_for_bb(adap))
376                 return 1;
377
378         /* Zero, one or two bytes reg address (offset) */
379         writew(alen, &i2c_base->cnt);
380         /* Set slave address */
381         writew(chip, &i2c_base->sa);
382
383         if (alen) {
384                 /* Must write reg offset first */
385 #ifdef CONFIG_I2C_REPEATED_START
386                 /* No stop bit, use Repeated Start (Sr) */
387                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
388                        I2C_CON_TRX, &i2c_base->con);
389 #else
390                 /* Stop - Start (P-S) */
391                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
392                        I2C_CON_TRX, &i2c_base->con);
393 #endif
394                 /* Send register offset */
395                 while (1) {
396                         status = wait_for_event(adap);
397                         /* Try to identify bus that is not padconf'd for I2C */
398                         if (status == I2C_STAT_XRDY) {
399                                 i2c_error = 2;
400                                 printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
401                                        adap->hwadapnr, status);
402                                 goto rd_exit;
403                         }
404                         if (status == 0 || (status & I2C_STAT_NACK)) {
405                                 i2c_error = 1;
406                                 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
407                                        status);
408                                 goto rd_exit;
409                         }
410                         if (alen) {
411                                 if (status & I2C_STAT_XRDY) {
412                                         alen--;
413                                         /* Do we have to use byte access? */
414                                         writeb((addr >> (8 * alen)) & 0xff,
415                                                &i2c_base->data);
416                                         writew(I2C_STAT_XRDY, &i2c_base->stat);
417                                 }
418                         }
419                         if (status & I2C_STAT_ARDY) {
420                                 writew(I2C_STAT_ARDY, &i2c_base->stat);
421                                 break;
422                         }
423                 }
424         }
425         /* Set slave address */
426         writew(chip, &i2c_base->sa);
427         /* Read len bytes from slave */
428         writew(len, &i2c_base->cnt);
429         /* Need stop bit here */
430         writew(I2C_CON_EN | I2C_CON_MST |
431                I2C_CON_STT | I2C_CON_STP,
432                &i2c_base->con);
433
434         /* Receive data */
435         while (1) {
436                 status = wait_for_event(adap);
437                 /*
438                  * Try to identify bus that is not padconf'd for I2C. This
439                  * state could be left over from previous transactions if
440                  * the address phase is skipped due to alen=0.
441                  */
442                 if (status == I2C_STAT_XRDY) {
443                         i2c_error = 2;
444                         printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
445                                adap->hwadapnr, status);
446                         goto rd_exit;
447                 }
448                 if (status == 0 || (status & I2C_STAT_NACK)) {
449                         i2c_error = 1;
450                         goto rd_exit;
451                 }
452                 if (status & I2C_STAT_RRDY) {
453                         *buffer++ = readb(&i2c_base->data);
454                         writew(I2C_STAT_RRDY, &i2c_base->stat);
455                 }
456                 if (status & I2C_STAT_ARDY) {
457                         writew(I2C_STAT_ARDY, &i2c_base->stat);
458                         break;
459                 }
460         }
461
462 rd_exit:
463         flush_fifo(adap);
464         writew(0xFFFF, &i2c_base->stat);
465         return i2c_error;
466 }
467
468 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
469 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
470                             int alen, uchar *buffer, int len)
471 {
472         struct i2c *i2c_base = omap24_get_base(adap);
473         int i;
474         u16 status;
475         int i2c_error = 0;
476         int timeout = I2C_TIMEOUT;
477
478         if (alen < 0) {
479                 puts("I2C write: addr len < 0\n");
480                 return 1;
481         }
482
483         if (len < 0) {
484                 puts("I2C write: data len < 0\n");
485                 return 1;
486         }
487
488         if (buffer == NULL) {
489                 puts("I2C write: NULL pointer passed\n");
490                 return 1;
491         }
492
493         if (alen > 2) {
494                 printf("I2C write: addr len %d not supported\n", alen);
495                 return 1;
496         }
497
498         if (addr + len > (1 << 16)) {
499                 printf("I2C write: address 0x%x + 0x%x out of range\n",
500                        addr, len);
501                 return 1;
502         }
503
504         /* Wait until bus not busy */
505         if (wait_for_bb(adap))
506                 return 1;
507
508         /* Start address phase - will write regoffset + len bytes data */
509         writew(alen + len, &i2c_base->cnt);
510         /* Set slave address */
511         writew(chip, &i2c_base->sa);
512         /* Stop bit needed here */
513         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
514                I2C_CON_STP, &i2c_base->con);
515
516         while (alen) {
517                 /* Must write reg offset (one or two bytes) */
518                 status = wait_for_event(adap);
519                 /* Try to identify bus that is not padconf'd for I2C */
520                 if (status == I2C_STAT_XRDY) {
521                         i2c_error = 2;
522                         printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
523                                adap->hwadapnr, status);
524                         goto wr_exit;
525                 }
526                 if (status == 0 || (status & I2C_STAT_NACK)) {
527                         i2c_error = 1;
528                         printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
529                                status);
530                         goto wr_exit;
531                 }
532                 if (status & I2C_STAT_XRDY) {
533                         alen--;
534                         writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
535                         writew(I2C_STAT_XRDY, &i2c_base->stat);
536                 } else {
537                         i2c_error = 1;
538                         printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
539                                status);
540                         goto wr_exit;
541                 }
542         }
543         /* Address phase is over, now write data */
544         for (i = 0; i < len; i++) {
545                 status = wait_for_event(adap);
546                 if (status == 0 || (status & I2C_STAT_NACK)) {
547                         i2c_error = 1;
548                         printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
549                                status);
550                         goto wr_exit;
551                 }
552                 if (status & I2C_STAT_XRDY) {
553                         writeb(buffer[i], &i2c_base->data);
554                         writew(I2C_STAT_XRDY, &i2c_base->stat);
555                 } else {
556                         i2c_error = 1;
557                         printf("i2c_write: bus not ready for data Tx (i=%d)\n",
558                                i);
559                         goto wr_exit;
560                 }
561         }
562         /*
563          * poll ARDY bit for making sure that last byte really has been
564          * transferred on the bus.
565          */
566         do {
567                 status = wait_for_event(adap);
568         } while (!(status & I2C_STAT_ARDY) && timeout--);
569         if (timeout <= 0)
570                 printf("i2c_write: timed out writig last byte!\n");
571
572 wr_exit:
573         flush_fifo(adap);
574         writew(0xFFFF, &i2c_base->stat);
575         return i2c_error;
576 }
577
578 /*
579  * Wait for the bus to be free by checking the Bus Busy (BB)
580  * bit to become clear
581  */
582 static int wait_for_bb(struct i2c_adapter *adap)
583 {
584         struct i2c *i2c_base = omap24_get_base(adap);
585         int timeout = I2C_TIMEOUT;
586         u16 stat;
587
588         writew(0xFFFF, &i2c_base->stat);        /* clear current interrupts...*/
589 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
590         while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
591 #else
592         /* Read RAW status */
593         while ((stat = readw(&i2c_base->irqstatus_raw) &
594                 I2C_STAT_BB) && timeout--) {
595 #endif
596                 writew(stat, &i2c_base->stat);
597                 udelay(adap->waitdelay);
598         }
599
600         if (timeout <= 0) {
601                 printf("Timed out in wait_for_bb: status=%04x\n",
602                        stat);
603                 return 1;
604         }
605         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
606         return 0;
607 }
608
609 /*
610  * Wait for the I2C controller to complete current action
611  * and update status
612  */
613 static u16 wait_for_event(struct i2c_adapter *adap)
614 {
615         struct i2c *i2c_base = omap24_get_base(adap);
616         u16 status;
617         int timeout = I2C_TIMEOUT;
618
619         do {
620                 udelay(adap->waitdelay);
621 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
622                 status = readw(&i2c_base->stat);
623 #else
624                 /* Read RAW status */
625                 status = readw(&i2c_base->irqstatus_raw);
626 #endif
627         } while (!(status &
628                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
629                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
630                     I2C_STAT_AL)) && timeout--);
631
632         if (timeout <= 0) {
633                 printf("Timed out in wait_for_event: status=%04x\n",
634                        status);
635                 /*
636                  * If status is still 0 here, probably the bus pads have
637                  * not been configured for I2C, and/or pull-ups are missing.
638                  */
639                 printf("Check if pads/pull-ups of bus %d are properly configured\n",
640                        adap->hwadapnr);
641                 writew(0xFFFF, &i2c_base->stat);
642                 status = 0;
643         }
644
645         return status;
646 }
647
648 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
649 {
650         switch (adap->hwadapnr) {
651         case 0:
652                 return (struct i2c *)I2C_BASE1;
653                 break;
654         case 1:
655                 return (struct i2c *)I2C_BASE2;
656                 break;
657 #if (I2C_BUS_MAX > 2)
658         case 2:
659                 return (struct i2c *)I2C_BASE3;
660                 break;
661 #if (I2C_BUS_MAX > 3)
662         case 3:
663                 return (struct i2c *)I2C_BASE4;
664                 break;
665 #if (I2C_BUS_MAX > 4)
666         case 4:
667                 return (struct i2c *)I2C_BASE5;
668                 break;
669 #endif
670 #endif
671 #endif
672         default:
673                 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
674                 break;
675         }
676         return NULL;
677 }
678
679 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
680 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
681 #endif
682 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
683 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
684 #endif
685
686 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
687                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
688                          CONFIG_SYS_OMAP24_I2C_SPEED,
689                          CONFIG_SYS_OMAP24_I2C_SLAVE,
690                          0)
691 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
692                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
693                          CONFIG_SYS_OMAP24_I2C_SPEED1,
694                          CONFIG_SYS_OMAP24_I2C_SLAVE1,
695                          1)
696 #if (I2C_BUS_MAX > 2)
697 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
698 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
699 #endif
700 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
701 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
702 #endif
703
704 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
705                          omap24_i2c_read, omap24_i2c_write, NULL,
706                          CONFIG_SYS_OMAP24_I2C_SPEED2,
707                          CONFIG_SYS_OMAP24_I2C_SLAVE2,
708                          2)
709 #if (I2C_BUS_MAX > 3)
710 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
711 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
712 #endif
713 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
714 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
715 #endif
716
717 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
718                          omap24_i2c_read, omap24_i2c_write, NULL,
719                          CONFIG_SYS_OMAP24_I2C_SPEED3,
720                          CONFIG_SYS_OMAP24_I2C_SLAVE3,
721                          3)
722 #if (I2C_BUS_MAX > 4)
723 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
724 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
725 #endif
726 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
727 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
728 #endif
729
730 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
731                          omap24_i2c_read, omap24_i2c_write, NULL,
732                          CONFIG_SYS_OMAP24_I2C_SPEED4,
733                          CONFIG_SYS_OMAP24_I2C_SLAVE4,
734                          4)
735 #endif
736 #endif
737 #endif