4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
36 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
37 * - Added support for set_speed
45 #include <asm/arch/i2c.h>
48 #include "omap24xx_i2c.h"
50 DECLARE_GLOBAL_DATA_PTR;
52 #define I2C_TIMEOUT 1000
54 /* Absolutely safe for status update at 100 kHz I2C: */
65 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
67 unsigned long internal_clk = 0, fclk;
68 unsigned int prescaler;
71 * This method is only called for Standard and Fast Mode speeds
73 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
74 * page 5685, Table 24-7)
75 * that the internal I2C clock (after prescaler) should be between
76 * 7-12 MHz (at least for Fast Mode (FS)).
78 * Such approach is used in v4.9 Linux kernel in:
79 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
82 speed /= 1000; /* convert speed to kHz */
89 fclk = I2C_IP_CLK / 1000;
90 prescaler = fclk / internal_clk;
91 prescaler = prescaler - 1;
97 scl = internal_clk / speed;
98 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
99 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
102 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
103 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
106 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
107 __func__, speed, prescaler, *pscl, *psch);
109 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
116 * Wait for the bus to be free by checking the Bus Busy (BB)
117 * bit to become clear
119 static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
121 int timeout = I2C_TIMEOUT;
124 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
125 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
126 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
128 /* Read RAW status */
129 while ((stat = readw(&i2c_base->irqstatus_raw) &
130 I2C_STAT_BB) && timeout--) {
132 writew(stat, &i2c_base->stat);
137 printf("Timed out in wait_for_bb: status=%04x\n",
141 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
146 * Wait for the I2C controller to complete current action
149 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
152 int timeout = I2C_TIMEOUT;
156 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
157 status = readw(&i2c_base->stat);
159 /* Read RAW status */
160 status = readw(&i2c_base->irqstatus_raw);
163 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
164 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
165 I2C_STAT_AL)) && timeout--);
168 printf("Timed out in wait_for_event: status=%04x\n",
171 * If status is still 0 here, probably the bus pads have
172 * not been configured for I2C, and/or pull-ups are missing.
174 printf("Check if pads/pull-ups of bus are properly configured\n");
175 writew(0xFFFF, &i2c_base->stat);
182 static void flush_fifo(struct i2c *i2c_base)
187 * note: if you try and read data when its not there or ready
188 * you get a bus error
191 stat = readw(&i2c_base->stat);
192 if (stat == I2C_STAT_RRDY) {
193 readb(&i2c_base->data);
194 writew(I2C_STAT_RRDY, &i2c_base->stat);
201 static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
204 int psc, fsscll = 0, fssclh = 0;
205 int hsscll = 0, hssclh = 0;
206 u32 scll = 0, sclh = 0;
208 if (speed >= OMAP_I2C_HIGH_SPEED) {
210 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
212 if (psc < I2C_PSC_MIN) {
213 printf("Error : I2C unsupported prescaler %d\n", psc);
217 /* For first phase of HS mode */
218 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
222 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
223 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
224 if (((fsscll < 0) || (fssclh < 0)) ||
225 ((fsscll > 255) || (fssclh > 255))) {
226 puts("Error : I2C initializing first phase clock\n");
230 /* For second phase of HS mode */
231 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
233 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
234 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
235 if (((fsscll < 0) || (fssclh < 0)) ||
236 ((fsscll > 255) || (fssclh > 255))) {
237 puts("Error : I2C initializing second phase clock\n");
241 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
242 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
245 /* Standard and fast speed */
246 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
248 puts("Error : I2C initializing clock\n");
253 *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
254 writew(0, &i2c_base->con);
255 writew(psc, &i2c_base->psc);
256 writew(scll, &i2c_base->scll);
257 writew(sclh, &i2c_base->sclh);
258 writew(I2C_CON_EN, &i2c_base->con);
259 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
264 static void omap24_i2c_deblock(struct i2c *i2c_base)
270 /* set test mode ST_EN = 1 */
271 orgsystest = readw(&i2c_base->systest);
272 systest = orgsystest;
273 /* enable testmode */
274 systest |= I2C_SYSTEST_ST_EN;
275 writew(systest, &i2c_base->systest);
276 systest &= ~I2C_SYSTEST_TMODE_MASK;
277 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
278 writew(systest, &i2c_base->systest);
280 /* set SCL, SDA = 1 */
281 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
282 writew(systest, &i2c_base->systest);
285 /* toggle scl 9 clocks */
286 for (i = 0; i < 9; i++) {
288 systest &= ~I2C_SYSTEST_SCL_O;
289 writew(systest, &i2c_base->systest);
292 systest |= I2C_SYSTEST_SCL_O;
293 writew(systest, &i2c_base->systest);
298 systest &= ~I2C_SYSTEST_SDA_O;
299 writew(systest, &i2c_base->systest);
301 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
302 writew(systest, &i2c_base->systest);
305 /* restore original mode */
306 writew(orgsystest, &i2c_base->systest);
309 static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
312 int timeout = I2C_TIMEOUT;
316 if (readw(&i2c_base->con) & I2C_CON_EN) {
317 writew(0, &i2c_base->con);
321 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
324 writew(I2C_CON_EN, &i2c_base->con);
325 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
327 puts("ERROR: Timeout in soft-reset\n");
333 if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
334 printf("ERROR: failed to setup I2C bus-speed!\n");
339 writew(slaveadd, &i2c_base->oa);
341 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
343 * Have to enable interrupts for OMAP2/3, these IPs don't have
344 * an 'irqstatus_raw' register and we shall have to poll 'stat'
346 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
347 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
350 flush_fifo(i2c_base);
351 writew(0xFFFF, &i2c_base->stat);
353 /* Handle possible failed I2C state */
354 if (wait_for_bb(i2c_base, *waitdelay))
356 omap24_i2c_deblock(i2c_base);
363 * i2c_probe: Use write access. Allows to identify addresses that are
364 * write-only (like the config register of dual-port EEPROMs)
366 static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
369 int res = 1; /* default = fail */
371 if (chip == readw(&i2c_base->oa))
374 /* Wait until bus is free */
375 if (wait_for_bb(i2c_base, waitdelay))
378 /* No data transfer, slave addr only */
379 writew(chip, &i2c_base->sa);
380 /* Stop bit needed here */
381 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
382 I2C_CON_STP, &i2c_base->con);
384 status = wait_for_event(i2c_base, waitdelay);
386 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
388 * With current high-level command implementation, notifying
389 * the user shall flood the console with 127 messages. If
390 * silent exit is desired upon unconfigured bus, remove the
391 * following 'if' section:
393 if (status == I2C_STAT_XRDY)
394 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
400 /* Check for ACK (!NAK) */
401 if (!(status & I2C_STAT_NACK)) {
402 res = 0; /* Device found */
403 udelay(waitdelay);/* Required by AM335X in SPL */
404 /* Abort transfer (force idle state) */
405 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
407 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
408 I2C_CON_STP, &i2c_base->con); /* STP */
411 flush_fifo(i2c_base);
412 writew(0xFFFF, &i2c_base->stat);
417 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
418 * of the requested number of bytes (note that the 'i2c md' command
419 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
420 * defined in the board config header, this transaction shall be with
421 * Repeated Start (Sr) between the address and data phases; otherwise
422 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
423 * The address (reg offset) may be 0, 1 or 2 bytes long.
424 * Function now reads correctly from chips that return more than one
425 * byte of data per addressed register (like TI temperature sensors),
426 * or that do not need a register address at all (such as some clock
429 static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
430 uint addr, int alen, uchar *buffer, int len)
436 puts("I2C read: addr len < 0\n");
440 puts("I2C read: data len < 0\n");
443 if (buffer == NULL) {
444 puts("I2C read: NULL pointer passed\n");
449 printf("I2C read: addr len %d not supported\n", alen);
453 if (addr + len > (1 << 16)) {
454 puts("I2C read: address out of range\n");
458 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
460 * EEPROM chips that implement "address overflow" are ones
461 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
462 * address and the extra bits end up in the "chip address"
463 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
464 * four 256 byte chips.
466 * Note that we consider the length of the address field to
467 * still be one byte because the extra address bits are
468 * hidden in the chip address.
471 chip |= ((addr >> (alen * 8)) &
472 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
475 /* Wait until bus not busy */
476 if (wait_for_bb(i2c_base, waitdelay))
479 /* Zero, one or two bytes reg address (offset) */
480 writew(alen, &i2c_base->cnt);
481 /* Set slave address */
482 writew(chip, &i2c_base->sa);
485 /* Must write reg offset first */
486 #ifdef CONFIG_I2C_REPEATED_START
487 /* No stop bit, use Repeated Start (Sr) */
488 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
489 I2C_CON_TRX, &i2c_base->con);
491 /* Stop - Start (P-S) */
492 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
493 I2C_CON_TRX, &i2c_base->con);
495 /* Send register offset */
497 status = wait_for_event(i2c_base, waitdelay);
498 /* Try to identify bus that is not padconf'd for I2C */
499 if (status == I2C_STAT_XRDY) {
501 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
505 if (status == 0 || (status & I2C_STAT_NACK)) {
507 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
512 if (status & I2C_STAT_XRDY) {
514 /* Do we have to use byte access? */
515 writeb((addr >> (8 * alen)) & 0xff,
517 writew(I2C_STAT_XRDY, &i2c_base->stat);
520 if (status & I2C_STAT_ARDY) {
521 writew(I2C_STAT_ARDY, &i2c_base->stat);
526 /* Set slave address */
527 writew(chip, &i2c_base->sa);
528 /* Read len bytes from slave */
529 writew(len, &i2c_base->cnt);
530 /* Need stop bit here */
531 writew(I2C_CON_EN | I2C_CON_MST |
532 I2C_CON_STT | I2C_CON_STP,
537 status = wait_for_event(i2c_base, waitdelay);
539 * Try to identify bus that is not padconf'd for I2C. This
540 * state could be left over from previous transactions if
541 * the address phase is skipped due to alen=0.
543 if (status == I2C_STAT_XRDY) {
545 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
549 if (status == 0 || (status & I2C_STAT_NACK)) {
553 if (status & I2C_STAT_RRDY) {
554 *buffer++ = readb(&i2c_base->data);
555 writew(I2C_STAT_RRDY, &i2c_base->stat);
557 if (status & I2C_STAT_ARDY) {
558 writew(I2C_STAT_ARDY, &i2c_base->stat);
564 flush_fifo(i2c_base);
565 writew(0xFFFF, &i2c_base->stat);
569 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
570 static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
571 uint addr, int alen, uchar *buffer, int len)
576 int timeout = I2C_TIMEOUT;
579 puts("I2C write: addr len < 0\n");
584 puts("I2C write: data len < 0\n");
588 if (buffer == NULL) {
589 puts("I2C write: NULL pointer passed\n");
594 printf("I2C write: addr len %d not supported\n", alen);
598 if (addr + len > (1 << 16)) {
599 printf("I2C write: address 0x%x + 0x%x out of range\n",
604 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
606 * EEPROM chips that implement "address overflow" are ones
607 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
608 * address and the extra bits end up in the "chip address"
609 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
610 * four 256 byte chips.
612 * Note that we consider the length of the address field to
613 * still be one byte because the extra address bits are
614 * hidden in the chip address.
617 chip |= ((addr >> (alen * 8)) &
618 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
621 /* Wait until bus not busy */
622 if (wait_for_bb(i2c_base, waitdelay))
625 /* Start address phase - will write regoffset + len bytes data */
626 writew(alen + len, &i2c_base->cnt);
627 /* Set slave address */
628 writew(chip, &i2c_base->sa);
629 /* Stop bit needed here */
630 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
631 I2C_CON_STP, &i2c_base->con);
634 /* Must write reg offset (one or two bytes) */
635 status = wait_for_event(i2c_base, waitdelay);
636 /* Try to identify bus that is not padconf'd for I2C */
637 if (status == I2C_STAT_XRDY) {
639 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
643 if (status == 0 || (status & I2C_STAT_NACK)) {
645 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
649 if (status & I2C_STAT_XRDY) {
651 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
652 writew(I2C_STAT_XRDY, &i2c_base->stat);
655 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
660 /* Address phase is over, now write data */
661 for (i = 0; i < len; i++) {
662 status = wait_for_event(i2c_base, waitdelay);
663 if (status == 0 || (status & I2C_STAT_NACK)) {
665 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
669 if (status & I2C_STAT_XRDY) {
670 writeb(buffer[i], &i2c_base->data);
671 writew(I2C_STAT_XRDY, &i2c_base->stat);
674 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
680 * poll ARDY bit for making sure that last byte really has been
681 * transferred on the bus.
684 status = wait_for_event(i2c_base, waitdelay);
685 } while (!(status & I2C_STAT_ARDY) && timeout--);
687 printf("i2c_write: timed out writig last byte!\n");
690 flush_fifo(i2c_base);
691 writew(0xFFFF, &i2c_base->stat);
695 #ifndef CONFIG_DM_I2C
697 * The legacy I2C functions. These need to get removed once
698 * all users of this driver are converted to DM.
700 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
702 switch (adap->hwadapnr) {
704 return (struct i2c *)I2C_BASE1;
707 return (struct i2c *)I2C_BASE2;
709 #if (I2C_BUS_MAX > 2)
711 return (struct i2c *)I2C_BASE3;
713 #if (I2C_BUS_MAX > 3)
715 return (struct i2c *)I2C_BASE4;
717 #if (I2C_BUS_MAX > 4)
719 return (struct i2c *)I2C_BASE5;
725 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
732 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
733 int alen, uchar *buffer, int len)
735 struct i2c *i2c_base = omap24_get_base(adap);
737 return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
742 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
743 int alen, uchar *buffer, int len)
745 struct i2c *i2c_base = omap24_get_base(adap);
747 return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
751 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
753 struct i2c *i2c_base = omap24_get_base(adap);
756 ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
758 error("%s: set i2c speed failed\n", __func__);
767 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
769 struct i2c *i2c_base = omap24_get_base(adap);
771 return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
774 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
776 struct i2c *i2c_base = omap24_get_base(adap);
778 return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
781 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
782 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
784 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
785 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
788 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
789 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
790 CONFIG_SYS_OMAP24_I2C_SPEED,
791 CONFIG_SYS_OMAP24_I2C_SLAVE,
793 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
794 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
795 CONFIG_SYS_OMAP24_I2C_SPEED1,
796 CONFIG_SYS_OMAP24_I2C_SLAVE1,
798 #if (I2C_BUS_MAX > 2)
799 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
800 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
802 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
803 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
806 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
807 omap24_i2c_read, omap24_i2c_write, NULL,
808 CONFIG_SYS_OMAP24_I2C_SPEED2,
809 CONFIG_SYS_OMAP24_I2C_SLAVE2,
811 #if (I2C_BUS_MAX > 3)
812 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
813 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
815 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
816 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
819 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
820 omap24_i2c_read, omap24_i2c_write, NULL,
821 CONFIG_SYS_OMAP24_I2C_SPEED3,
822 CONFIG_SYS_OMAP24_I2C_SLAVE3,
824 #if (I2C_BUS_MAX > 4)
825 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
826 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
828 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
829 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
832 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
833 omap24_i2c_read, omap24_i2c_write, NULL,
834 CONFIG_SYS_OMAP24_I2C_SPEED4,
835 CONFIG_SYS_OMAP24_I2C_SLAVE4,
841 #else /* CONFIG_DM_I2C */
843 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
845 struct omap_i2c *priv = dev_get_priv(bus);
848 debug("i2c_xfer: %d messages\n", nmsgs);
849 for (; nmsgs > 0; nmsgs--, msg++) {
850 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
851 if (msg->flags & I2C_M_RD) {
852 ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
853 msg->addr, 0, 0, msg->buf,
856 ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
857 msg->addr, 0, 0, msg->buf,
861 debug("i2c_write: error sending\n");
869 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
871 struct omap_i2c *priv = dev_get_priv(bus);
875 return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
878 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
881 struct omap_i2c *priv = dev_get_priv(bus);
883 return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
886 static int omap_i2c_probe(struct udevice *bus)
888 struct omap_i2c *priv = dev_get_priv(bus);
890 __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
895 static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
897 struct omap_i2c *priv = dev_get_priv(bus);
899 priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *),
901 priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
906 static const struct dm_i2c_ops omap_i2c_ops = {
907 .xfer = omap_i2c_xfer,
908 .probe_chip = omap_i2c_probe_chip,
909 .set_bus_speed = omap_i2c_set_bus_speed,
912 static const struct udevice_id omap_i2c_ids[] = {
913 { .compatible = "ti,omap4-i2c" },
917 U_BOOT_DRIVER(i2c_omap) = {
920 .of_match = omap_i2c_ids,
921 .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
922 .probe = omap_i2c_probe,
923 .priv_auto_alloc_size = sizeof(struct omap_i2c),
924 .ops = &omap_i2c_ops,
925 .flags = DM_FLAG_PRE_RELOC,
928 #endif /* CONFIG_DM_I2C */