git.sur5r.net Git - u-boot/blob - drivers/i2c/omap24xx_i2c.c

   1 /*
   2  * Basic I2C functions
   3  *
   4  * Copyright (c) 2004 Texas Instruments
   5  *
   6  * This package is free software;  you can redistribute it and/or
   7  * modify it under the terms of the license found in the file
   8  * named COPYING that should have accompanied this file.
   9  *
  10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13  *
  14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15  *
  16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17  * Rewritten to fit into the current U-Boot framework
  18  *
  19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20  *
  21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
  22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
  23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
  24  * OMAPs and derivatives as well. The only anticipated exception would
  25  * be the OMAP2420, which shall require driver modification.
  26  * - Rewritten i2c_read to operate correctly with all types of chips
  27  *   (old function could not read consistent data from some I2C slaves).
  28  * - Optimized i2c_write.
  29  * - New i2c_probe, performs write access vs read. The old probe could
  30  *   hang the system under certain conditions (e.g. unconfigured pads).
  31  * - The read/write/probe functions try to identify unconfigured bus.
  32  * - Status functions now read irqstatus_raw as per TRM guidelines
  33  *   (except for OMAP243X and OMAP34XX).
  34  * - Driver now supports up to I2C5 (OMAP5).
  35  *
  36  * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
  37  * - Added support for set_speed
  38  *
  39  */
  40
  41 #include <common.h>
  42 #include <i2c.h>
  43
  44 #include <asm/arch/i2c.h>
  45 #include <asm/io.h>
  46
  47 #include "omap24xx_i2c.h"
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 #define I2C_TIMEOUT     1000
  52
  53 /* Absolutely safe for status update at 100 kHz I2C: */
  54 #define I2C_WAIT        200
  55
  56 static int wait_for_bb(struct i2c_adapter *adap);
  57 static struct i2c *omap24_get_base(struct i2c_adapter *adap);
  58 static u16 wait_for_event(struct i2c_adapter *adap);
  59 static void flush_fifo(struct i2c_adapter *adap);
  60 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
  61 {
  62         unsigned int sampleclk, prescaler;
  63         int fsscll, fssclh;
  64
  65         speed <<= 1;
  66         prescaler = 0;
  67         /*
  68          * some divisors may cause a precission loss, but shouldn't
  69          * be a big thing, because i2c_clk is then allready very slow.
  70          */
  71         while (prescaler <= 0xFF) {
  72                 sampleclk = I2C_IP_CLK / (prescaler+1);
  73
  74                 fsscll = sampleclk / speed;
  75                 fssclh = fsscll;
  76                 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
  77                 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
  78
  79                 if (((fsscll > 0) && (fssclh > 0)) &&
  80                     ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
  81                     (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
  82                         if (pscl)
  83                                 *pscl = fsscll;
  84                         if (psch)
  85                                 *psch = fssclh;
  86
  87                         return prescaler;
  88                 }
  89                 prescaler++;
  90         }
  91         return -1;
  92 }
  93 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  94 {
  95         struct i2c *i2c_base = omap24_get_base(adap);
  96         int psc, fsscll = 0, fssclh = 0;
  97         int hsscll = 0, hssclh = 0;
  98         u32 scll = 0, sclh = 0;
  99
 100         if (speed >= OMAP_I2C_HIGH_SPEED) {
 101                 /* High speed */
 102                 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
 103                 psc -= 1;
 104                 if (psc < I2C_PSC_MIN) {
 105                         printf("Error : I2C unsupported prescaler %d\n", psc);
 106                         return -1;
 107                 }
 108
 109                 /* For first phase of HS mode */
 110                 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
 111
 112                 fssclh = fsscll;
 113
 114                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
 115                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
 116                 if (((fsscll < 0) || (fssclh < 0)) ||
 117                     ((fsscll > 255) || (fssclh > 255))) {
 118                         puts("Error : I2C initializing first phase clock\n");
 119                         return -1;
 120                 }
 121
 122                 /* For second phase of HS mode */
 123                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
 124
 125                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
 126                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
 127                 if (((fsscll < 0) || (fssclh < 0)) ||
 128                     ((fsscll > 255) || (fssclh > 255))) {
 129                         puts("Error : I2C initializing second phase clock\n");
 130                         return -1;
 131                 }
 132
 133                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
 134                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
 135
 136         } else {
 137                 /* Standard and fast speed */
 138                 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
 139                 if (0 > psc) {
 140                         puts("Error : I2C initializing clock\n");
 141                         return -1;
 142                 }
 143         }
 144
 145         adap->speed     = speed;
 146         adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
 147         writew(0, &i2c_base->con);
 148         writew(psc, &i2c_base->psc);
 149         writew(scll, &i2c_base->scll);
 150         writew(sclh, &i2c_base->sclh);
 151         writew(I2C_CON_EN, &i2c_base->con);
 152         writew(0xFFFF, &i2c_base->stat);        /* clear all pending status */
 153
 154         return 0;
 155 }
 156
 157 static void omap24_i2c_deblock(struct i2c_adapter *adap)
 158 {
 159         struct i2c *i2c_base = omap24_get_base(adap);
 160         int i;
 161         u16 systest;
 162         u16 orgsystest;
 163
 164         /* set test mode ST_EN = 1 */
 165         orgsystest = readw(&i2c_base->systest);
 166         systest = orgsystest;
 167         /* enable testmode */
 168         systest |= I2C_SYSTEST_ST_EN;
 169         writew(systest, &i2c_base->systest);
 170         systest &= ~I2C_SYSTEST_TMODE_MASK;
 171         systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
 172         writew(systest, &i2c_base->systest);
 173
 174         /* set SCL, SDA  = 1 */
 175         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
 176         writew(systest, &i2c_base->systest);
 177         udelay(10);
 178
 179         /* toggle scl 9 clocks */
 180         for (i = 0; i < 9; i++) {
 181                 /* SCL = 0 */
 182                 systest &= ~I2C_SYSTEST_SCL_O;
 183                 writew(systest, &i2c_base->systest);
 184                 udelay(10);
 185                 /* SCL = 1 */
 186                 systest |= I2C_SYSTEST_SCL_O;
 187                 writew(systest, &i2c_base->systest);
 188                 udelay(10);
 189         }
 190
 191         /* send stop */
 192         systest &= ~I2C_SYSTEST_SDA_O;
 193         writew(systest, &i2c_base->systest);
 194         udelay(10);
 195         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
 196         writew(systest, &i2c_base->systest);
 197         udelay(10);
 198
 199         /* restore original mode */
 200         writew(orgsystest, &i2c_base->systest);
 201 }
 202
 203 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 204 {
 205         struct i2c *i2c_base = omap24_get_base(adap);
 206         int timeout = I2C_TIMEOUT;
 207         int deblock = 1;
 208
 209 retry:
 210         if (readw(&i2c_base->con) & I2C_CON_EN) {
 211                 writew(0, &i2c_base->con);
 212                 udelay(50000);
 213         }
 214
 215         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
 216         udelay(1000);
 217
 218         writew(I2C_CON_EN, &i2c_base->con);
 219         while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
 220                 if (timeout <= 0) {
 221                         puts("ERROR: Timeout in soft-reset\n");
 222                         return;
 223                 }
 224                 udelay(1000);
 225         }
 226
 227         if (0 != omap24_i2c_setspeed(adap, speed)) {
 228                 printf("ERROR: failed to setup I2C bus-speed!\n");
 229                 return;
 230         }
 231
 232         /* own address */
 233         writew(slaveadd, &i2c_base->oa);
 234
 235 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 236         /*
 237          * Have to enable interrupts for OMAP2/3, these IPs don't have
 238          * an 'irqstatus_raw' register and we shall have to poll 'stat'
 239          */
 240         writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
 241                I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
 242 #endif
 243         udelay(1000);
 244         flush_fifo(adap);
 245         writew(0xFFFF, &i2c_base->stat);
 246
 247         /* Handle possible failed I2C state */
 248         if (wait_for_bb(adap))
 249                 if (deblock == 1) {
 250                         omap24_i2c_deblock(adap);
 251                         deblock = 0;
 252                         goto retry;
 253                 }
 254 }
 255
 256 static void flush_fifo(struct i2c_adapter *adap)
 257 {
 258         struct i2c *i2c_base = omap24_get_base(adap);
 259         u16 stat;
 260
 261         /*
 262          * note: if you try and read data when its not there or ready
 263          * you get a bus error
 264          */
 265         while (1) {
 266                 stat = readw(&i2c_base->stat);
 267                 if (stat == I2C_STAT_RRDY) {
 268                         readb(&i2c_base->data);
 269                         writew(I2C_STAT_RRDY, &i2c_base->stat);
 270                         udelay(1000);
 271                 } else
 272                         break;
 273         }
 274 }
 275
 276 /*
 277  * i2c_probe: Use write access. Allows to identify addresses that are
 278  *            write-only (like the config register of dual-port EEPROMs)
 279  */
 280 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 281 {
 282         struct i2c *i2c_base = omap24_get_base(adap);
 283         u16 status;
 284         int res = 1; /* default = fail */
 285
 286         if (chip == readw(&i2c_base->oa))
 287                 return res;
 288
 289         /* Wait until bus is free */
 290         if (wait_for_bb(adap))
 291                 return res;
 292
 293         /* No data transfer, slave addr only */
 294         writew(chip, &i2c_base->sa);
 295         /* Stop bit needed here */
 296         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 297                I2C_CON_STP, &i2c_base->con);
 298
 299         status = wait_for_event(adap);
 300
 301         if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
 302                 /*
 303                  * With current high-level command implementation, notifying
 304                  * the user shall flood the console with 127 messages. If
 305                  * silent exit is desired upon unconfigured bus, remove the
 306                  * following 'if' section:
 307                  */
 308                 if (status == I2C_STAT_XRDY)
 309                         printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
 310                                adap->hwadapnr, status);
 311
 312                 goto pr_exit;
 313         }
 314
 315         /* Check for ACK (!NAK) */
 316         if (!(status & I2C_STAT_NACK)) {
 317                 res = 0;                                /* Device found */
 318                 udelay(adap->waitdelay);/* Required by AM335X in SPL */
 319                 /* Abort transfer (force idle state) */
 320                 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
 321                 udelay(1000);
 322                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
 323                        I2C_CON_STP, &i2c_base->con);            /* STP */
 324         }
 325 pr_exit:
 326         flush_fifo(adap);
 327         writew(0xFFFF, &i2c_base->stat);
 328         return res;
 329 }
 330
 331 /*
 332  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
 333  *           of the requested number of bytes (note that the 'i2c md' command
 334  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
 335  *           defined in the board config header, this transaction shall be with
 336  *           Repeated Start (Sr) between the address and data phases; otherwise
 337  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
 338  *           The address (reg offset) may be 0, 1 or 2 bytes long.
 339  *           Function now reads correctly from chips that return more than one
 340  *           byte of data per addressed register (like TI temperature sensors),
 341  *           or that do not need a register address at all (such as some clock
 342  *           distributors).
 343  */
 344 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 345                            int alen, uchar *buffer, int len)
 346 {
 347         struct i2c *i2c_base = omap24_get_base(adap);
 348         int i2c_error = 0;
 349         u16 status;
 350
 351         if (alen < 0) {
 352                 puts("I2C read: addr len < 0\n");
 353                 return 1;
 354         }
 355         if (len < 0) {
 356                 puts("I2C read: data len < 0\n");
 357                 return 1;
 358         }
 359         if (buffer == NULL) {
 360                 puts("I2C read: NULL pointer passed\n");
 361                 return 1;
 362         }
 363
 364         if (alen > 2) {
 365                 printf("I2C read: addr len %d not supported\n", alen);
 366                 return 1;
 367         }
 368
 369         if (addr + len > (1 << 16)) {
 370                 puts("I2C read: address out of range\n");
 371                 return 1;
 372         }
 373
 374 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 375         /*
 376          * EEPROM chips that implement "address overflow" are ones
 377          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 378          * address and the extra bits end up in the "chip address"
 379          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 380          * four 256 byte chips.
 381          *
 382          * Note that we consider the length of the address field to
 383          * still be one byte because the extra address bits are
 384          * hidden in the chip address.
 385          */
 386         if (alen > 0)
 387                 chip |= ((addr >> (alen * 8)) &
 388                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 389 #endif
 390
 391         /* Wait until bus not busy */
 392         if (wait_for_bb(adap))
 393                 return 1;
 394
 395         /* Zero, one or two bytes reg address (offset) */
 396         writew(alen, &i2c_base->cnt);
 397         /* Set slave address */
 398         writew(chip, &i2c_base->sa);
 399
 400         if (alen) {
 401                 /* Must write reg offset first */
 402 #ifdef CONFIG_I2C_REPEATED_START
 403                 /* No stop bit, use Repeated Start (Sr) */
 404                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
 405                        I2C_CON_TRX, &i2c_base->con);
 406 #else
 407                 /* Stop - Start (P-S) */
 408                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
 409                        I2C_CON_TRX, &i2c_base->con);
 410 #endif
 411                 /* Send register offset */
 412                 while (1) {
 413                         status = wait_for_event(adap);
 414                         /* Try to identify bus that is not padconf'd for I2C */
 415                         if (status == I2C_STAT_XRDY) {
 416                                 i2c_error = 2;
 417                                 printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
 418                                        adap->hwadapnr, status);
 419                                 goto rd_exit;
 420                         }
 421                         if (status == 0 || (status & I2C_STAT_NACK)) {
 422                                 i2c_error = 1;
 423                                 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
 424                                        status);
 425                                 goto rd_exit;
 426                         }
 427                         if (alen) {
 428                                 if (status & I2C_STAT_XRDY) {
 429                                         alen--;
 430                                         /* Do we have to use byte access? */
 431                                         writeb((addr >> (8 * alen)) & 0xff,
 432                                                &i2c_base->data);
 433                                         writew(I2C_STAT_XRDY, &i2c_base->stat);
 434                                 }
 435                         }
 436                         if (status & I2C_STAT_ARDY) {
 437                                 writew(I2C_STAT_ARDY, &i2c_base->stat);
 438                                 break;
 439                         }
 440                 }
 441         }
 442         /* Set slave address */
 443         writew(chip, &i2c_base->sa);
 444         /* Read len bytes from slave */
 445         writew(len, &i2c_base->cnt);
 446         /* Need stop bit here */
 447         writew(I2C_CON_EN | I2C_CON_MST |
 448                I2C_CON_STT | I2C_CON_STP,
 449                &i2c_base->con);
 450
 451         /* Receive data */
 452         while (1) {
 453                 status = wait_for_event(adap);
 454                 /*
 455                  * Try to identify bus that is not padconf'd for I2C. This
 456                  * state could be left over from previous transactions if
 457                  * the address phase is skipped due to alen=0.
 458                  */
 459                 if (status == I2C_STAT_XRDY) {
 460                         i2c_error = 2;
 461                         printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
 462                                adap->hwadapnr, status);
 463                         goto rd_exit;
 464                 }
 465                 if (status == 0 || (status & I2C_STAT_NACK)) {
 466                         i2c_error = 1;
 467                         goto rd_exit;
 468                 }
 469                 if (status & I2C_STAT_RRDY) {
 470                         *buffer++ = readb(&i2c_base->data);
 471                         writew(I2C_STAT_RRDY, &i2c_base->stat);
 472                 }
 473                 if (status & I2C_STAT_ARDY) {
 474                         writew(I2C_STAT_ARDY, &i2c_base->stat);
 475                         break;
 476                 }
 477         }
 478
 479 rd_exit:
 480         flush_fifo(adap);
 481         writew(0xFFFF, &i2c_base->stat);
 482         return i2c_error;
 483 }
 484
 485 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
 486 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 487                             int alen, uchar *buffer, int len)
 488 {
 489         struct i2c *i2c_base = omap24_get_base(adap);
 490         int i;
 491         u16 status;
 492         int i2c_error = 0;
 493         int timeout = I2C_TIMEOUT;
 494
 495         if (alen < 0) {
 496                 puts("I2C write: addr len < 0\n");
 497                 return 1;
 498         }
 499
 500         if (len < 0) {
 501                 puts("I2C write: data len < 0\n");
 502                 return 1;
 503         }
 504
 505         if (buffer == NULL) {
 506                 puts("I2C write: NULL pointer passed\n");
 507                 return 1;
 508         }
 509
 510         if (alen > 2) {
 511                 printf("I2C write: addr len %d not supported\n", alen);
 512                 return 1;
 513         }
 514
 515         if (addr + len > (1 << 16)) {
 516                 printf("I2C write: address 0x%x + 0x%x out of range\n",
 517                        addr, len);
 518                 return 1;
 519         }
 520
 521 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 522         /*
 523          * EEPROM chips that implement "address overflow" are ones
 524          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 525          * address and the extra bits end up in the "chip address"
 526          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 527          * four 256 byte chips.
 528          *
 529          * Note that we consider the length of the address field to
 530          * still be one byte because the extra address bits are
 531          * hidden in the chip address.
 532          */
 533         if (alen > 0)
 534                 chip |= ((addr >> (alen * 8)) &
 535                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 536 #endif
 537
 538         /* Wait until bus not busy */
 539         if (wait_for_bb(adap))
 540                 return 1;
 541
 542         /* Start address phase - will write regoffset + len bytes data */
 543         writew(alen + len, &i2c_base->cnt);
 544         /* Set slave address */
 545         writew(chip, &i2c_base->sa);
 546         /* Stop bit needed here */
 547         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 548                I2C_CON_STP, &i2c_base->con);
 549
 550         while (alen) {
 551                 /* Must write reg offset (one or two bytes) */
 552                 status = wait_for_event(adap);
 553                 /* Try to identify bus that is not padconf'd for I2C */
 554                 if (status == I2C_STAT_XRDY) {
 555                         i2c_error = 2;
 556                         printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
 557                                adap->hwadapnr, status);
 558                         goto wr_exit;
 559                 }
 560                 if (status == 0 || (status & I2C_STAT_NACK)) {
 561                         i2c_error = 1;
 562                         printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
 563                                status);
 564                         goto wr_exit;
 565                 }
 566                 if (status & I2C_STAT_XRDY) {
 567                         alen--;
 568                         writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
 569                         writew(I2C_STAT_XRDY, &i2c_base->stat);
 570                 } else {
 571                         i2c_error = 1;
 572                         printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
 573                                status);
 574                         goto wr_exit;
 575                 }
 576         }
 577         /* Address phase is over, now write data */
 578         for (i = 0; i < len; i++) {
 579                 status = wait_for_event(adap);
 580                 if (status == 0 || (status & I2C_STAT_NACK)) {
 581                         i2c_error = 1;
 582                         printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
 583                                status);
 584                         goto wr_exit;
 585                 }
 586                 if (status & I2C_STAT_XRDY) {
 587                         writeb(buffer[i], &i2c_base->data);
 588                         writew(I2C_STAT_XRDY, &i2c_base->stat);
 589                 } else {
 590                         i2c_error = 1;
 591                         printf("i2c_write: bus not ready for data Tx (i=%d)\n",
 592                                i);
 593                         goto wr_exit;
 594                 }
 595         }
 596         /*
 597          * poll ARDY bit for making sure that last byte really has been
 598          * transferred on the bus.
 599          */
 600         do {
 601                 status = wait_for_event(adap);
 602         } while (!(status & I2C_STAT_ARDY) && timeout--);
 603         if (timeout <= 0)
 604                 printf("i2c_write: timed out writig last byte!\n");
 605
 606 wr_exit:
 607         flush_fifo(adap);
 608         writew(0xFFFF, &i2c_base->stat);
 609         return i2c_error;
 610 }
 611
 612 /*
 613  * Wait for the bus to be free by checking the Bus Busy (BB)
 614  * bit to become clear
 615  */
 616 static int wait_for_bb(struct i2c_adapter *adap)
 617 {
 618         struct i2c *i2c_base = omap24_get_base(adap);
 619         int timeout = I2C_TIMEOUT;
 620         u16 stat;
 621
 622         writew(0xFFFF, &i2c_base->stat);        /* clear current interrupts...*/
 623 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 624         while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
 625 #else
 626         /* Read RAW status */
 627         while ((stat = readw(&i2c_base->irqstatus_raw) &
 628                 I2C_STAT_BB) && timeout--) {
 629 #endif
 630                 writew(stat, &i2c_base->stat);
 631                 udelay(adap->waitdelay);
 632         }
 633
 634         if (timeout <= 0) {
 635                 printf("Timed out in wait_for_bb: status=%04x\n",
 636                        stat);
 637                 return 1;
 638         }
 639         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
 640         return 0;
 641 }
 642
 643 /*
 644  * Wait for the I2C controller to complete current action
 645  * and update status
 646  */
 647 static u16 wait_for_event(struct i2c_adapter *adap)
 648 {
 649         struct i2c *i2c_base = omap24_get_base(adap);
 650         u16 status;
 651         int timeout = I2C_TIMEOUT;
 652
 653         do {
 654                 udelay(adap->waitdelay);
 655 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 656                 status = readw(&i2c_base->stat);
 657 #else
 658                 /* Read RAW status */
 659                 status = readw(&i2c_base->irqstatus_raw);
 660 #endif
 661         } while (!(status &
 662                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
 663                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
 664                     I2C_STAT_AL)) && timeout--);
 665
 666         if (timeout <= 0) {
 667                 printf("Timed out in wait_for_event: status=%04x\n",
 668                        status);
 669                 /*
 670                  * If status is still 0 here, probably the bus pads have
 671                  * not been configured for I2C, and/or pull-ups are missing.
 672                  */
 673                 printf("Check if pads/pull-ups of bus %d are properly configured\n",
 674                        adap->hwadapnr);
 675                 writew(0xFFFF, &i2c_base->stat);
 676                 status = 0;
 677         }
 678
 679         return status;
 680 }
 681
 682 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
 683 {
 684         switch (adap->hwadapnr) {
 685         case 0:
 686                 return (struct i2c *)I2C_BASE1;
 687                 break;
 688         case 1:
 689                 return (struct i2c *)I2C_BASE2;
 690                 break;
 691 #if (I2C_BUS_MAX > 2)
 692         case 2:
 693                 return (struct i2c *)I2C_BASE3;
 694                 break;
 695 #if (I2C_BUS_MAX > 3)
 696         case 3:
 697                 return (struct i2c *)I2C_BASE4;
 698                 break;
 699 #if (I2C_BUS_MAX > 4)
 700         case 4:
 701                 return (struct i2c *)I2C_BASE5;
 702                 break;
 703 #endif
 704 #endif
 705 #endif
 706         default:
 707                 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
 708                 break;
 709         }
 710         return NULL;
 711 }
 712
 713 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
 714 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
 715 #endif
 716 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
 717 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
 718 #endif
 719
 720 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
 721                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
 722                          CONFIG_SYS_OMAP24_I2C_SPEED,
 723                          CONFIG_SYS_OMAP24_I2C_SLAVE,
 724                          0)
 725 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
 726                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
 727                          CONFIG_SYS_OMAP24_I2C_SPEED1,
 728                          CONFIG_SYS_OMAP24_I2C_SLAVE1,
 729                          1)
 730 #if (I2C_BUS_MAX > 2)
 731 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
 732 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
 733 #endif
 734 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
 735 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
 736 #endif
 737
 738 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
 739                          omap24_i2c_read, omap24_i2c_write, NULL,
 740                          CONFIG_SYS_OMAP24_I2C_SPEED2,
 741                          CONFIG_SYS_OMAP24_I2C_SLAVE2,
 742                          2)
 743 #if (I2C_BUS_MAX > 3)
 744 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
 745 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
 746 #endif
 747 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
 748 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
 749 #endif
 750
 751 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
 752                          omap24_i2c_read, omap24_i2c_write, NULL,
 753                          CONFIG_SYS_OMAP24_I2C_SPEED3,
 754                          CONFIG_SYS_OMAP24_I2C_SLAVE3,
 755                          3)
 756 #if (I2C_BUS_MAX > 4)
 757 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
 758 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
 759 #endif
 760 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
 761 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
 762 #endif
 763
 764 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
 765                          omap24_i2c_read, omap24_i2c_write, NULL,
 766                          CONFIG_SYS_OMAP24_I2C_SPEED4,
 767                          CONFIG_SYS_OMAP24_I2C_SLAVE4,
 768                          4)
 769 #endif
 770 #endif
 771 #endif