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[u-boot] / drivers / i2c / omap24xx_i2c.c
1 /*
2  * Basic I2C functions
3  *
4  * Copyright (c) 2004 Texas Instruments
5  *
6  * This package is free software;  you can redistribute it and/or
7  * modify it under the terms of the license found in the file
8  * named COPYING that should have accompanied this file.
9  *
10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13  *
14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15  *
16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17  * Rewritten to fit into the current U-Boot framework
18  *
19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20  *
21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24  * OMAPs and derivatives as well. The only anticipated exception would
25  * be the OMAP2420, which shall require driver modification.
26  * - Rewritten i2c_read to operate correctly with all types of chips
27  *   (old function could not read consistent data from some I2C slaves).
28  * - Optimized i2c_write.
29  * - New i2c_probe, performs write access vs read. The old probe could
30  *   hang the system under certain conditions (e.g. unconfigured pads).
31  * - The read/write/probe functions try to identify unconfigured bus.
32  * - Status functions now read irqstatus_raw as per TRM guidelines
33  *   (except for OMAP243X and OMAP34XX).
34  * - Driver now supports up to I2C5 (OMAP5).
35  *
36  * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
37  * - Added support for set_speed
38  *
39  */
40
41 #include <common.h>
42 #include <dm.h>
43 #include <i2c.h>
44
45 #include <asm/arch/i2c.h>
46 #include <asm/io.h>
47
48 #include "omap24xx_i2c.h"
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 #define I2C_TIMEOUT     1000
53
54 /* Absolutely safe for status update at 100 kHz I2C: */
55 #define I2C_WAIT        200
56
57 struct omap_i2c {
58         struct udevice *clk;
59         struct i2c *regs;
60         unsigned int speed;
61         int waitdelay;
62         int clk_id;
63 };
64
65 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
66 {
67         unsigned long internal_clk = 0, fclk;
68         unsigned int prescaler;
69
70         /*
71          * This method is only called for Standard and Fast Mode speeds
72          *
73          * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
74          * page 5685, Table 24-7)
75          * that the internal I2C clock (after prescaler) should be between
76          * 7-12 MHz (at least for Fast Mode (FS)).
77          *
78          * Such approach is used in v4.9 Linux kernel in:
79          * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
80          */
81
82         speed /= 1000; /* convert speed to kHz */
83
84         if (speed > 100)
85                 internal_clk = 9600;
86         else
87                 internal_clk = 4000;
88
89         fclk = I2C_IP_CLK / 1000;
90         prescaler = fclk / internal_clk;
91         prescaler = prescaler - 1;
92
93         if (speed > 100) {
94                 unsigned long scl;
95
96                 /* Fast mode */
97                 scl = internal_clk / speed;
98                 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
99                 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
100         } else {
101                 /* Standard mode */
102                 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
103                 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
104         }
105
106         debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
107               __func__, speed, prescaler, *pscl, *psch);
108
109         if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
110                 return -EINVAL;
111
112         return prescaler;
113 }
114
115 /*
116  * Wait for the bus to be free by checking the Bus Busy (BB)
117  * bit to become clear
118  */
119 static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
120 {
121         int timeout = I2C_TIMEOUT;
122         u16 stat;
123
124         writew(0xFFFF, &i2c_base->stat);        /* clear current interrupts...*/
125 #if defined(CONFIG_OMAP34XX)
126         while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
127 #else
128         /* Read RAW status */
129         while ((stat = readw(&i2c_base->irqstatus_raw) &
130                 I2C_STAT_BB) && timeout--) {
131 #endif
132                 writew(stat, &i2c_base->stat);
133                 udelay(waitdelay);
134         }
135
136         if (timeout <= 0) {
137                 printf("Timed out in wait_for_bb: status=%04x\n",
138                        stat);
139                 return 1;
140         }
141         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
142         return 0;
143 }
144
145 /*
146  * Wait for the I2C controller to complete current action
147  * and update status
148  */
149 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
150 {
151         u16 status;
152         int timeout = I2C_TIMEOUT;
153
154         do {
155                 udelay(waitdelay);
156 #if defined(CONFIG_OMAP34XX)
157                 status = readw(&i2c_base->stat);
158 #else
159                 /* Read RAW status */
160                 status = readw(&i2c_base->irqstatus_raw);
161 #endif
162         } while (!(status &
163                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
164                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
165                     I2C_STAT_AL)) && timeout--);
166
167         if (timeout <= 0) {
168                 printf("Timed out in wait_for_event: status=%04x\n",
169                        status);
170                 /*
171                  * If status is still 0 here, probably the bus pads have
172                  * not been configured for I2C, and/or pull-ups are missing.
173                  */
174                 printf("Check if pads/pull-ups of bus are properly configured\n");
175                 writew(0xFFFF, &i2c_base->stat);
176                 status = 0;
177         }
178
179         return status;
180 }
181
182 static void flush_fifo(struct i2c *i2c_base)
183 {
184         u16 stat;
185
186         /*
187          * note: if you try and read data when its not there or ready
188          * you get a bus error
189          */
190         while (1) {
191                 stat = readw(&i2c_base->stat);
192                 if (stat == I2C_STAT_RRDY) {
193                         readb(&i2c_base->data);
194                         writew(I2C_STAT_RRDY, &i2c_base->stat);
195                         udelay(1000);
196                 } else
197                         break;
198         }
199 }
200
201 static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
202                                  int *waitdelay)
203 {
204         int psc, fsscll = 0, fssclh = 0;
205         int hsscll = 0, hssclh = 0;
206         u32 scll = 0, sclh = 0;
207
208         if (speed >= OMAP_I2C_HIGH_SPEED) {
209                 /* High speed */
210                 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
211                 psc -= 1;
212                 if (psc < I2C_PSC_MIN) {
213                         printf("Error : I2C unsupported prescaler %d\n", psc);
214                         return -1;
215                 }
216
217                 /* For first phase of HS mode */
218                 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
219
220                 fssclh = fsscll;
221
222                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
223                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
224                 if (((fsscll < 0) || (fssclh < 0)) ||
225                     ((fsscll > 255) || (fssclh > 255))) {
226                         puts("Error : I2C initializing first phase clock\n");
227                         return -1;
228                 }
229
230                 /* For second phase of HS mode */
231                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
232
233                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
234                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
235                 if (((fsscll < 0) || (fssclh < 0)) ||
236                     ((fsscll > 255) || (fssclh > 255))) {
237                         puts("Error : I2C initializing second phase clock\n");
238                         return -1;
239                 }
240
241                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
242                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
243
244         } else {
245                 /* Standard and fast speed */
246                 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
247                 if (0 > psc) {
248                         puts("Error : I2C initializing clock\n");
249                         return -1;
250                 }
251         }
252
253         *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
254         writew(0, &i2c_base->con);
255         writew(psc, &i2c_base->psc);
256         writew(scll, &i2c_base->scll);
257         writew(sclh, &i2c_base->sclh);
258         writew(I2C_CON_EN, &i2c_base->con);
259         writew(0xFFFF, &i2c_base->stat);        /* clear all pending status */
260
261         return 0;
262 }
263
264 static void omap24_i2c_deblock(struct i2c *i2c_base)
265 {
266         int i;
267         u16 systest;
268         u16 orgsystest;
269
270         /* set test mode ST_EN = 1 */
271         orgsystest = readw(&i2c_base->systest);
272         systest = orgsystest;
273         /* enable testmode */
274         systest |= I2C_SYSTEST_ST_EN;
275         writew(systest, &i2c_base->systest);
276         systest &= ~I2C_SYSTEST_TMODE_MASK;
277         systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
278         writew(systest, &i2c_base->systest);
279
280         /* set SCL, SDA  = 1 */
281         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
282         writew(systest, &i2c_base->systest);
283         udelay(10);
284
285         /* toggle scl 9 clocks */
286         for (i = 0; i < 9; i++) {
287                 /* SCL = 0 */
288                 systest &= ~I2C_SYSTEST_SCL_O;
289                 writew(systest, &i2c_base->systest);
290                 udelay(10);
291                 /* SCL = 1 */
292                 systest |= I2C_SYSTEST_SCL_O;
293                 writew(systest, &i2c_base->systest);
294                 udelay(10);
295         }
296
297         /* send stop */
298         systest &= ~I2C_SYSTEST_SDA_O;
299         writew(systest, &i2c_base->systest);
300         udelay(10);
301         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
302         writew(systest, &i2c_base->systest);
303         udelay(10);
304
305         /* restore original mode */
306         writew(orgsystest, &i2c_base->systest);
307 }
308
309 static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
310                               int *waitdelay)
311 {
312         int timeout = I2C_TIMEOUT;
313         int deblock = 1;
314
315 retry:
316         if (readw(&i2c_base->con) & I2C_CON_EN) {
317                 writew(0, &i2c_base->con);
318                 udelay(50000);
319         }
320
321         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
322         udelay(1000);
323
324         writew(I2C_CON_EN, &i2c_base->con);
325         while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
326                 if (timeout <= 0) {
327                         puts("ERROR: Timeout in soft-reset\n");
328                         return;
329                 }
330                 udelay(1000);
331         }
332
333         if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
334                 printf("ERROR: failed to setup I2C bus-speed!\n");
335                 return;
336         }
337
338         /* own address */
339         writew(slaveadd, &i2c_base->oa);
340
341 #if defined(CONFIG_OMAP34XX)
342         /*
343          * Have to enable interrupts for OMAP2/3, these IPs don't have
344          * an 'irqstatus_raw' register and we shall have to poll 'stat'
345          */
346         writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
347                I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
348 #endif
349         udelay(1000);
350         flush_fifo(i2c_base);
351         writew(0xFFFF, &i2c_base->stat);
352
353         /* Handle possible failed I2C state */
354         if (wait_for_bb(i2c_base, *waitdelay))
355                 if (deblock == 1) {
356                         omap24_i2c_deblock(i2c_base);
357                         deblock = 0;
358                         goto retry;
359                 }
360 }
361
362 /*
363  * i2c_probe: Use write access. Allows to identify addresses that are
364  *            write-only (like the config register of dual-port EEPROMs)
365  */
366 static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
367 {
368         u16 status;
369         int res = 1; /* default = fail */
370
371         if (chip == readw(&i2c_base->oa))
372                 return res;
373
374         /* Wait until bus is free */
375         if (wait_for_bb(i2c_base, waitdelay))
376                 return res;
377
378         /* No data transfer, slave addr only */
379         writew(chip, &i2c_base->sa);
380         /* Stop bit needed here */
381         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
382                I2C_CON_STP, &i2c_base->con);
383
384         status = wait_for_event(i2c_base, waitdelay);
385
386         if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
387                 /*
388                  * With current high-level command implementation, notifying
389                  * the user shall flood the console with 127 messages. If
390                  * silent exit is desired upon unconfigured bus, remove the
391                  * following 'if' section:
392                  */
393                 if (status == I2C_STAT_XRDY)
394                         printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
395                                status);
396
397                 goto pr_exit;
398         }
399
400         /* Check for ACK (!NAK) */
401         if (!(status & I2C_STAT_NACK)) {
402                 res = 0;                                /* Device found */
403                 udelay(waitdelay);/* Required by AM335X in SPL */
404                 /* Abort transfer (force idle state) */
405                 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
406                 udelay(1000);
407                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
408                        I2C_CON_STP, &i2c_base->con);            /* STP */
409         }
410 pr_exit:
411         flush_fifo(i2c_base);
412         writew(0xFFFF, &i2c_base->stat);
413         return res;
414 }
415
416 /*
417  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
418  *           of the requested number of bytes (note that the 'i2c md' command
419  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
420  *           defined in the board config header, this transaction shall be with
421  *           Repeated Start (Sr) between the address and data phases; otherwise
422  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
423  *           The address (reg offset) may be 0, 1 or 2 bytes long.
424  *           Function now reads correctly from chips that return more than one
425  *           byte of data per addressed register (like TI temperature sensors),
426  *           or that do not need a register address at all (such as some clock
427  *           distributors).
428  */
429 static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
430                              uint addr, int alen, uchar *buffer, int len)
431 {
432         int i2c_error = 0;
433         u16 status;
434
435         if (alen < 0) {
436                 puts("I2C read: addr len < 0\n");
437                 return 1;
438         }
439         if (len < 0) {
440                 puts("I2C read: data len < 0\n");
441                 return 1;
442         }
443         if (buffer == NULL) {
444                 puts("I2C read: NULL pointer passed\n");
445                 return 1;
446         }
447
448         if (alen > 2) {
449                 printf("I2C read: addr len %d not supported\n", alen);
450                 return 1;
451         }
452
453         if (addr + len > (1 << 16)) {
454                 puts("I2C read: address out of range\n");
455                 return 1;
456         }
457
458 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
459         /*
460          * EEPROM chips that implement "address overflow" are ones
461          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
462          * address and the extra bits end up in the "chip address"
463          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
464          * four 256 byte chips.
465          *
466          * Note that we consider the length of the address field to
467          * still be one byte because the extra address bits are
468          * hidden in the chip address.
469          */
470         if (alen > 0)
471                 chip |= ((addr >> (alen * 8)) &
472                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
473 #endif
474
475         /* Wait until bus not busy */
476         if (wait_for_bb(i2c_base, waitdelay))
477                 return 1;
478
479         /* Zero, one or two bytes reg address (offset) */
480         writew(alen, &i2c_base->cnt);
481         /* Set slave address */
482         writew(chip, &i2c_base->sa);
483
484         if (alen) {
485                 /* Must write reg offset first */
486 #ifdef CONFIG_I2C_REPEATED_START
487                 /* No stop bit, use Repeated Start (Sr) */
488                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
489                        I2C_CON_TRX, &i2c_base->con);
490 #else
491                 /* Stop - Start (P-S) */
492                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
493                        I2C_CON_TRX, &i2c_base->con);
494 #endif
495                 /* Send register offset */
496                 while (1) {
497                         status = wait_for_event(i2c_base, waitdelay);
498                         /* Try to identify bus that is not padconf'd for I2C */
499                         if (status == I2C_STAT_XRDY) {
500                                 i2c_error = 2;
501                                 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
502                                        status);
503                                 goto rd_exit;
504                         }
505                         if (status == 0 || (status & I2C_STAT_NACK)) {
506                                 i2c_error = 1;
507                                 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
508                                        status);
509                                 goto rd_exit;
510                         }
511                         if (alen) {
512                                 if (status & I2C_STAT_XRDY) {
513                                         alen--;
514                                         /* Do we have to use byte access? */
515                                         writeb((addr >> (8 * alen)) & 0xff,
516                                                &i2c_base->data);
517                                         writew(I2C_STAT_XRDY, &i2c_base->stat);
518                                 }
519                         }
520                         if (status & I2C_STAT_ARDY) {
521                                 writew(I2C_STAT_ARDY, &i2c_base->stat);
522                                 break;
523                         }
524                 }
525         }
526         /* Set slave address */
527         writew(chip, &i2c_base->sa);
528         /* Read len bytes from slave */
529         writew(len, &i2c_base->cnt);
530         /* Need stop bit here */
531         writew(I2C_CON_EN | I2C_CON_MST |
532                I2C_CON_STT | I2C_CON_STP,
533                &i2c_base->con);
534
535         /* Receive data */
536         while (1) {
537                 status = wait_for_event(i2c_base, waitdelay);
538                 /*
539                  * Try to identify bus that is not padconf'd for I2C. This
540                  * state could be left over from previous transactions if
541                  * the address phase is skipped due to alen=0.
542                  */
543                 if (status == I2C_STAT_XRDY) {
544                         i2c_error = 2;
545                         printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
546                                status);
547                         goto rd_exit;
548                 }
549                 if (status == 0 || (status & I2C_STAT_NACK)) {
550                         i2c_error = 1;
551                         goto rd_exit;
552                 }
553                 if (status & I2C_STAT_RRDY) {
554                         *buffer++ = readb(&i2c_base->data);
555                         writew(I2C_STAT_RRDY, &i2c_base->stat);
556                 }
557                 if (status & I2C_STAT_ARDY) {
558                         writew(I2C_STAT_ARDY, &i2c_base->stat);
559                         break;
560                 }
561         }
562
563 rd_exit:
564         flush_fifo(i2c_base);
565         writew(0xFFFF, &i2c_base->stat);
566         return i2c_error;
567 }
568
569 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
570 static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
571                               uint addr, int alen, uchar *buffer, int len)
572 {
573         int i;
574         u16 status;
575         int i2c_error = 0;
576         int timeout = I2C_TIMEOUT;
577
578         if (alen < 0) {
579                 puts("I2C write: addr len < 0\n");
580                 return 1;
581         }
582
583         if (len < 0) {
584                 puts("I2C write: data len < 0\n");
585                 return 1;
586         }
587
588         if (buffer == NULL) {
589                 puts("I2C write: NULL pointer passed\n");
590                 return 1;
591         }
592
593         if (alen > 2) {
594                 printf("I2C write: addr len %d not supported\n", alen);
595                 return 1;
596         }
597
598         if (addr + len > (1 << 16)) {
599                 printf("I2C write: address 0x%x + 0x%x out of range\n",
600                        addr, len);
601                 return 1;
602         }
603
604 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
605         /*
606          * EEPROM chips that implement "address overflow" are ones
607          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
608          * address and the extra bits end up in the "chip address"
609          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
610          * four 256 byte chips.
611          *
612          * Note that we consider the length of the address field to
613          * still be one byte because the extra address bits are
614          * hidden in the chip address.
615          */
616         if (alen > 0)
617                 chip |= ((addr >> (alen * 8)) &
618                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
619 #endif
620
621         /* Wait until bus not busy */
622         if (wait_for_bb(i2c_base, waitdelay))
623                 return 1;
624
625         /* Start address phase - will write regoffset + len bytes data */
626         writew(alen + len, &i2c_base->cnt);
627         /* Set slave address */
628         writew(chip, &i2c_base->sa);
629         /* Stop bit needed here */
630         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
631                I2C_CON_STP, &i2c_base->con);
632
633         while (alen) {
634                 /* Must write reg offset (one or two bytes) */
635                 status = wait_for_event(i2c_base, waitdelay);
636                 /* Try to identify bus that is not padconf'd for I2C */
637                 if (status == I2C_STAT_XRDY) {
638                         i2c_error = 2;
639                         printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
640                                status);
641                         goto wr_exit;
642                 }
643                 if (status == 0 || (status & I2C_STAT_NACK)) {
644                         i2c_error = 1;
645                         printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
646                                status);
647                         goto wr_exit;
648                 }
649                 if (status & I2C_STAT_XRDY) {
650                         alen--;
651                         writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
652                         writew(I2C_STAT_XRDY, &i2c_base->stat);
653                 } else {
654                         i2c_error = 1;
655                         printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
656                                status);
657                         goto wr_exit;
658                 }
659         }
660         /* Address phase is over, now write data */
661         for (i = 0; i < len; i++) {
662                 status = wait_for_event(i2c_base, waitdelay);
663                 if (status == 0 || (status & I2C_STAT_NACK)) {
664                         i2c_error = 1;
665                         printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
666                                status);
667                         goto wr_exit;
668                 }
669                 if (status & I2C_STAT_XRDY) {
670                         writeb(buffer[i], &i2c_base->data);
671                         writew(I2C_STAT_XRDY, &i2c_base->stat);
672                 } else {
673                         i2c_error = 1;
674                         printf("i2c_write: bus not ready for data Tx (i=%d)\n",
675                                i);
676                         goto wr_exit;
677                 }
678         }
679         /*
680          * poll ARDY bit for making sure that last byte really has been
681          * transferred on the bus.
682          */
683         do {
684                 status = wait_for_event(i2c_base, waitdelay);
685         } while (!(status & I2C_STAT_ARDY) && timeout--);
686         if (timeout <= 0)
687                 printf("i2c_write: timed out writig last byte!\n");
688
689 wr_exit:
690         flush_fifo(i2c_base);
691         writew(0xFFFF, &i2c_base->stat);
692         return i2c_error;
693 }
694
695 #ifndef CONFIG_DM_I2C
696 /*
697  * The legacy I2C functions. These need to get removed once
698  * all users of this driver are converted to DM.
699  */
700 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
701 {
702         switch (adap->hwadapnr) {
703         case 0:
704                 return (struct i2c *)I2C_BASE1;
705                 break;
706         case 1:
707                 return (struct i2c *)I2C_BASE2;
708                 break;
709 #if (I2C_BUS_MAX > 2)
710         case 2:
711                 return (struct i2c *)I2C_BASE3;
712                 break;
713 #if (I2C_BUS_MAX > 3)
714         case 3:
715                 return (struct i2c *)I2C_BASE4;
716                 break;
717 #if (I2C_BUS_MAX > 4)
718         case 4:
719                 return (struct i2c *)I2C_BASE5;
720                 break;
721 #endif
722 #endif
723 #endif
724         default:
725                 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
726                 break;
727         }
728         return NULL;
729 }
730
731
732 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
733                            int alen, uchar *buffer, int len)
734 {
735         struct i2c *i2c_base = omap24_get_base(adap);
736
737         return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
738                                  alen, buffer, len);
739 }
740
741
742 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
743                             int alen, uchar *buffer, int len)
744 {
745         struct i2c *i2c_base = omap24_get_base(adap);
746
747         return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
748                                   alen, buffer, len);
749 }
750
751 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
752 {
753         struct i2c *i2c_base = omap24_get_base(adap);
754         int ret;
755
756         ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
757         if (ret) {
758                 error("%s: set i2c speed failed\n", __func__);
759                 return ret;
760         }
761
762         adap->speed = speed;
763
764         return 0;
765 }
766
767 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
768 {
769         struct i2c *i2c_base = omap24_get_base(adap);
770
771         return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
772 }
773
774 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
775 {
776         struct i2c *i2c_base = omap24_get_base(adap);
777
778         return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
779 }
780
781 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
782 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
783 #endif
784 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
785 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
786 #endif
787
788 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
789                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
790                          CONFIG_SYS_OMAP24_I2C_SPEED,
791                          CONFIG_SYS_OMAP24_I2C_SLAVE,
792                          0)
793 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
794                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
795                          CONFIG_SYS_OMAP24_I2C_SPEED1,
796                          CONFIG_SYS_OMAP24_I2C_SLAVE1,
797                          1)
798 #if (I2C_BUS_MAX > 2)
799 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
800 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
801 #endif
802 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
803 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
804 #endif
805
806 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
807                          omap24_i2c_read, omap24_i2c_write, NULL,
808                          CONFIG_SYS_OMAP24_I2C_SPEED2,
809                          CONFIG_SYS_OMAP24_I2C_SLAVE2,
810                          2)
811 #if (I2C_BUS_MAX > 3)
812 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
813 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
814 #endif
815 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
816 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
817 #endif
818
819 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
820                          omap24_i2c_read, omap24_i2c_write, NULL,
821                          CONFIG_SYS_OMAP24_I2C_SPEED3,
822                          CONFIG_SYS_OMAP24_I2C_SLAVE3,
823                          3)
824 #if (I2C_BUS_MAX > 4)
825 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
826 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
827 #endif
828 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
829 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
830 #endif
831
832 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
833                          omap24_i2c_read, omap24_i2c_write, NULL,
834                          CONFIG_SYS_OMAP24_I2C_SPEED4,
835                          CONFIG_SYS_OMAP24_I2C_SLAVE4,
836                          4)
837 #endif
838 #endif
839 #endif
840
841 #else /* CONFIG_DM_I2C */
842
843 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
844 {
845         struct omap_i2c *priv = dev_get_priv(bus);
846         int ret;
847
848         debug("i2c_xfer: %d messages\n", nmsgs);
849         for (; nmsgs > 0; nmsgs--, msg++) {
850                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
851                 if (msg->flags & I2C_M_RD) {
852                         ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
853                                                 msg->addr, 0, 0, msg->buf,
854                                                 msg->len);
855                 } else {
856                         ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
857                                                  msg->addr, 0, 0, msg->buf,
858                                                  msg->len);
859                 }
860                 if (ret) {
861                         debug("i2c_write: error sending\n");
862                         return -EREMOTEIO;
863                 }
864         }
865
866         return 0;
867 }
868
869 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
870 {
871         struct omap_i2c *priv = dev_get_priv(bus);
872
873         priv->speed = speed;
874
875         return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
876 }
877
878 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
879                                      uint chip_flags)
880 {
881         struct omap_i2c *priv = dev_get_priv(bus);
882
883         return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
884 }
885
886 static int omap_i2c_probe(struct udevice *bus)
887 {
888         struct omap_i2c *priv = dev_get_priv(bus);
889
890         __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
891
892         return 0;
893 }
894
895 static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
896 {
897         struct omap_i2c *priv = dev_get_priv(bus);
898
899         priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *),
900                                  MAP_NOCACHE);
901         priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
902
903         return 0;
904 }
905
906 static const struct dm_i2c_ops omap_i2c_ops = {
907         .xfer           = omap_i2c_xfer,
908         .probe_chip     = omap_i2c_probe_chip,
909         .set_bus_speed  = omap_i2c_set_bus_speed,
910 };
911
912 static const struct udevice_id omap_i2c_ids[] = {
913         { .compatible = "ti,omap3-i2c" },
914         { .compatible = "ti,omap4-i2c" },
915         { }
916 };
917
918 U_BOOT_DRIVER(i2c_omap) = {
919         .name   = "i2c_omap",
920         .id     = UCLASS_I2C,
921         .of_match = omap_i2c_ids,
922         .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
923         .probe  = omap_i2c_probe,
924         .priv_auto_alloc_size = sizeof(struct omap_i2c),
925         .ops    = &omap_i2c_ops,
926         .flags  = DM_FLAG_PRE_RELOC,
927 };
928
929 #endif /* CONFIG_DM_I2C */