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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
[u-boot] / drivers / i2c / omap24xx_i2c.c
1 /*
2  * Basic I2C functions
3  *
4  * Copyright (c) 2004 Texas Instruments
5  *
6  * This package is free software;  you can redistribute it and/or
7  * modify it under the terms of the license found in the file
8  * named COPYING that should have accompanied this file.
9  *
10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13  *
14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15  *
16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17  * Rewritten to fit into the current U-Boot framework
18  *
19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20  *
21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24  * OMAPs and derivatives as well. The only anticipated exception would
25  * be the OMAP2420, which shall require driver modification.
26  * - Rewritten i2c_read to operate correctly with all types of chips
27  *   (old function could not read consistent data from some I2C slaves).
28  * - Optimized i2c_write.
29  * - New i2c_probe, performs write access vs read. The old probe could
30  *   hang the system under certain conditions (e.g. unconfigured pads).
31  * - The read/write/probe functions try to identify unconfigured bus.
32  * - Status functions now read irqstatus_raw as per TRM guidelines
33  *   (except for OMAP243X and OMAP34XX).
34  * - Driver now supports up to I2C5 (OMAP5).
35  *
36  * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
37  * - Added support for set_speed
38  *
39  */
40
41 #include <common.h>
42 #include <dm.h>
43 #include <i2c.h>
44
45 #include <asm/arch/i2c.h>
46 #include <asm/io.h>
47
48 #include "omap24xx_i2c.h"
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 #define I2C_TIMEOUT     1000
53
54 /* Absolutely safe for status update at 100 kHz I2C: */
55 #define I2C_WAIT        200
56
57 struct omap_i2c {
58         struct udevice *clk;
59         struct i2c *regs;
60         unsigned int speed;
61         int waitdelay;
62         int clk_id;
63 };
64
65 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
66 {
67         unsigned int sampleclk, prescaler;
68         int fsscll, fssclh;
69
70         speed <<= 1;
71         prescaler = 0;
72         /*
73          * some divisors may cause a precission loss, but shouldn't
74          * be a big thing, because i2c_clk is then allready very slow.
75          */
76         while (prescaler <= 0xFF) {
77                 sampleclk = I2C_IP_CLK / (prescaler+1);
78
79                 fsscll = sampleclk / speed;
80                 fssclh = fsscll;
81                 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
82                 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
83
84                 if (((fsscll > 0) && (fssclh > 0)) &&
85                     ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
86                     (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
87                         if (pscl)
88                                 *pscl = fsscll;
89                         if (psch)
90                                 *psch = fssclh;
91
92                         return prescaler;
93                 }
94                 prescaler++;
95         }
96         return -1;
97 }
98
99 /*
100  * Wait for the bus to be free by checking the Bus Busy (BB)
101  * bit to become clear
102  */
103 static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
104 {
105         int timeout = I2C_TIMEOUT;
106         u16 stat;
107
108         writew(0xFFFF, &i2c_base->stat);        /* clear current interrupts...*/
109 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
110         while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
111 #else
112         /* Read RAW status */
113         while ((stat = readw(&i2c_base->irqstatus_raw) &
114                 I2C_STAT_BB) && timeout--) {
115 #endif
116                 writew(stat, &i2c_base->stat);
117                 udelay(waitdelay);
118         }
119
120         if (timeout <= 0) {
121                 printf("Timed out in wait_for_bb: status=%04x\n",
122                        stat);
123                 return 1;
124         }
125         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
126         return 0;
127 }
128
129 /*
130  * Wait for the I2C controller to complete current action
131  * and update status
132  */
133 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
134 {
135         u16 status;
136         int timeout = I2C_TIMEOUT;
137
138         do {
139                 udelay(waitdelay);
140 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
141                 status = readw(&i2c_base->stat);
142 #else
143                 /* Read RAW status */
144                 status = readw(&i2c_base->irqstatus_raw);
145 #endif
146         } while (!(status &
147                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
148                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
149                     I2C_STAT_AL)) && timeout--);
150
151         if (timeout <= 0) {
152                 printf("Timed out in wait_for_event: status=%04x\n",
153                        status);
154                 /*
155                  * If status is still 0 here, probably the bus pads have
156                  * not been configured for I2C, and/or pull-ups are missing.
157                  */
158                 printf("Check if pads/pull-ups of bus are properly configured\n");
159                 writew(0xFFFF, &i2c_base->stat);
160                 status = 0;
161         }
162
163         return status;
164 }
165
166 static void flush_fifo(struct i2c *i2c_base)
167 {
168         u16 stat;
169
170         /*
171          * note: if you try and read data when its not there or ready
172          * you get a bus error
173          */
174         while (1) {
175                 stat = readw(&i2c_base->stat);
176                 if (stat == I2C_STAT_RRDY) {
177                         readb(&i2c_base->data);
178                         writew(I2C_STAT_RRDY, &i2c_base->stat);
179                         udelay(1000);
180                 } else
181                         break;
182         }
183 }
184
185 static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
186                                  int *waitdelay)
187 {
188         int psc, fsscll = 0, fssclh = 0;
189         int hsscll = 0, hssclh = 0;
190         u32 scll = 0, sclh = 0;
191
192         if (speed >= OMAP_I2C_HIGH_SPEED) {
193                 /* High speed */
194                 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
195                 psc -= 1;
196                 if (psc < I2C_PSC_MIN) {
197                         printf("Error : I2C unsupported prescaler %d\n", psc);
198                         return -1;
199                 }
200
201                 /* For first phase of HS mode */
202                 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
203
204                 fssclh = fsscll;
205
206                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
207                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
208                 if (((fsscll < 0) || (fssclh < 0)) ||
209                     ((fsscll > 255) || (fssclh > 255))) {
210                         puts("Error : I2C initializing first phase clock\n");
211                         return -1;
212                 }
213
214                 /* For second phase of HS mode */
215                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
216
217                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
218                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
219                 if (((fsscll < 0) || (fssclh < 0)) ||
220                     ((fsscll > 255) || (fssclh > 255))) {
221                         puts("Error : I2C initializing second phase clock\n");
222                         return -1;
223                 }
224
225                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
226                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
227
228         } else {
229                 /* Standard and fast speed */
230                 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
231                 if (0 > psc) {
232                         puts("Error : I2C initializing clock\n");
233                         return -1;
234                 }
235         }
236
237         *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
238         writew(0, &i2c_base->con);
239         writew(psc, &i2c_base->psc);
240         writew(scll, &i2c_base->scll);
241         writew(sclh, &i2c_base->sclh);
242         writew(I2C_CON_EN, &i2c_base->con);
243         writew(0xFFFF, &i2c_base->stat);        /* clear all pending status */
244
245         return 0;
246 }
247
248 static void omap24_i2c_deblock(struct i2c *i2c_base)
249 {
250         int i;
251         u16 systest;
252         u16 orgsystest;
253
254         /* set test mode ST_EN = 1 */
255         orgsystest = readw(&i2c_base->systest);
256         systest = orgsystest;
257         /* enable testmode */
258         systest |= I2C_SYSTEST_ST_EN;
259         writew(systest, &i2c_base->systest);
260         systest &= ~I2C_SYSTEST_TMODE_MASK;
261         systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
262         writew(systest, &i2c_base->systest);
263
264         /* set SCL, SDA  = 1 */
265         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
266         writew(systest, &i2c_base->systest);
267         udelay(10);
268
269         /* toggle scl 9 clocks */
270         for (i = 0; i < 9; i++) {
271                 /* SCL = 0 */
272                 systest &= ~I2C_SYSTEST_SCL_O;
273                 writew(systest, &i2c_base->systest);
274                 udelay(10);
275                 /* SCL = 1 */
276                 systest |= I2C_SYSTEST_SCL_O;
277                 writew(systest, &i2c_base->systest);
278                 udelay(10);
279         }
280
281         /* send stop */
282         systest &= ~I2C_SYSTEST_SDA_O;
283         writew(systest, &i2c_base->systest);
284         udelay(10);
285         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
286         writew(systest, &i2c_base->systest);
287         udelay(10);
288
289         /* restore original mode */
290         writew(orgsystest, &i2c_base->systest);
291 }
292
293 static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
294                               int *waitdelay)
295 {
296         int timeout = I2C_TIMEOUT;
297         int deblock = 1;
298
299 retry:
300         if (readw(&i2c_base->con) & I2C_CON_EN) {
301                 writew(0, &i2c_base->con);
302                 udelay(50000);
303         }
304
305         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
306         udelay(1000);
307
308         writew(I2C_CON_EN, &i2c_base->con);
309         while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
310                 if (timeout <= 0) {
311                         puts("ERROR: Timeout in soft-reset\n");
312                         return;
313                 }
314                 udelay(1000);
315         }
316
317         if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
318                 printf("ERROR: failed to setup I2C bus-speed!\n");
319                 return;
320         }
321
322         /* own address */
323         writew(slaveadd, &i2c_base->oa);
324
325 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
326         /*
327          * Have to enable interrupts for OMAP2/3, these IPs don't have
328          * an 'irqstatus_raw' register and we shall have to poll 'stat'
329          */
330         writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
331                I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
332 #endif
333         udelay(1000);
334         flush_fifo(i2c_base);
335         writew(0xFFFF, &i2c_base->stat);
336
337         /* Handle possible failed I2C state */
338         if (wait_for_bb(i2c_base, *waitdelay))
339                 if (deblock == 1) {
340                         omap24_i2c_deblock(i2c_base);
341                         deblock = 0;
342                         goto retry;
343                 }
344 }
345
346 /*
347  * i2c_probe: Use write access. Allows to identify addresses that are
348  *            write-only (like the config register of dual-port EEPROMs)
349  */
350 static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
351 {
352         u16 status;
353         int res = 1; /* default = fail */
354
355         if (chip == readw(&i2c_base->oa))
356                 return res;
357
358         /* Wait until bus is free */
359         if (wait_for_bb(i2c_base, waitdelay))
360                 return res;
361
362         /* No data transfer, slave addr only */
363         writew(chip, &i2c_base->sa);
364         /* Stop bit needed here */
365         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
366                I2C_CON_STP, &i2c_base->con);
367
368         status = wait_for_event(i2c_base, waitdelay);
369
370         if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
371                 /*
372                  * With current high-level command implementation, notifying
373                  * the user shall flood the console with 127 messages. If
374                  * silent exit is desired upon unconfigured bus, remove the
375                  * following 'if' section:
376                  */
377                 if (status == I2C_STAT_XRDY)
378                         printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
379                                status);
380
381                 goto pr_exit;
382         }
383
384         /* Check for ACK (!NAK) */
385         if (!(status & I2C_STAT_NACK)) {
386                 res = 0;                                /* Device found */
387                 udelay(waitdelay);/* Required by AM335X in SPL */
388                 /* Abort transfer (force idle state) */
389                 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
390                 udelay(1000);
391                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
392                        I2C_CON_STP, &i2c_base->con);            /* STP */
393         }
394 pr_exit:
395         flush_fifo(i2c_base);
396         writew(0xFFFF, &i2c_base->stat);
397         return res;
398 }
399
400 /*
401  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
402  *           of the requested number of bytes (note that the 'i2c md' command
403  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
404  *           defined in the board config header, this transaction shall be with
405  *           Repeated Start (Sr) between the address and data phases; otherwise
406  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
407  *           The address (reg offset) may be 0, 1 or 2 bytes long.
408  *           Function now reads correctly from chips that return more than one
409  *           byte of data per addressed register (like TI temperature sensors),
410  *           or that do not need a register address at all (such as some clock
411  *           distributors).
412  */
413 static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
414                              uint addr, int alen, uchar *buffer, int len)
415 {
416         int i2c_error = 0;
417         u16 status;
418
419         if (alen < 0) {
420                 puts("I2C read: addr len < 0\n");
421                 return 1;
422         }
423         if (len < 0) {
424                 puts("I2C read: data len < 0\n");
425                 return 1;
426         }
427         if (buffer == NULL) {
428                 puts("I2C read: NULL pointer passed\n");
429                 return 1;
430         }
431
432         if (alen > 2) {
433                 printf("I2C read: addr len %d not supported\n", alen);
434                 return 1;
435         }
436
437         if (addr + len > (1 << 16)) {
438                 puts("I2C read: address out of range\n");
439                 return 1;
440         }
441
442 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
443         /*
444          * EEPROM chips that implement "address overflow" are ones
445          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
446          * address and the extra bits end up in the "chip address"
447          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
448          * four 256 byte chips.
449          *
450          * Note that we consider the length of the address field to
451          * still be one byte because the extra address bits are
452          * hidden in the chip address.
453          */
454         if (alen > 0)
455                 chip |= ((addr >> (alen * 8)) &
456                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
457 #endif
458
459         /* Wait until bus not busy */
460         if (wait_for_bb(i2c_base, waitdelay))
461                 return 1;
462
463         /* Zero, one or two bytes reg address (offset) */
464         writew(alen, &i2c_base->cnt);
465         /* Set slave address */
466         writew(chip, &i2c_base->sa);
467
468         if (alen) {
469                 /* Must write reg offset first */
470 #ifdef CONFIG_I2C_REPEATED_START
471                 /* No stop bit, use Repeated Start (Sr) */
472                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
473                        I2C_CON_TRX, &i2c_base->con);
474 #else
475                 /* Stop - Start (P-S) */
476                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
477                        I2C_CON_TRX, &i2c_base->con);
478 #endif
479                 /* Send register offset */
480                 while (1) {
481                         status = wait_for_event(i2c_base, waitdelay);
482                         /* Try to identify bus that is not padconf'd for I2C */
483                         if (status == I2C_STAT_XRDY) {
484                                 i2c_error = 2;
485                                 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
486                                        status);
487                                 goto rd_exit;
488                         }
489                         if (status == 0 || (status & I2C_STAT_NACK)) {
490                                 i2c_error = 1;
491                                 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
492                                        status);
493                                 goto rd_exit;
494                         }
495                         if (alen) {
496                                 if (status & I2C_STAT_XRDY) {
497                                         alen--;
498                                         /* Do we have to use byte access? */
499                                         writeb((addr >> (8 * alen)) & 0xff,
500                                                &i2c_base->data);
501                                         writew(I2C_STAT_XRDY, &i2c_base->stat);
502                                 }
503                         }
504                         if (status & I2C_STAT_ARDY) {
505                                 writew(I2C_STAT_ARDY, &i2c_base->stat);
506                                 break;
507                         }
508                 }
509         }
510         /* Set slave address */
511         writew(chip, &i2c_base->sa);
512         /* Read len bytes from slave */
513         writew(len, &i2c_base->cnt);
514         /* Need stop bit here */
515         writew(I2C_CON_EN | I2C_CON_MST |
516                I2C_CON_STT | I2C_CON_STP,
517                &i2c_base->con);
518
519         /* Receive data */
520         while (1) {
521                 status = wait_for_event(i2c_base, waitdelay);
522                 /*
523                  * Try to identify bus that is not padconf'd for I2C. This
524                  * state could be left over from previous transactions if
525                  * the address phase is skipped due to alen=0.
526                  */
527                 if (status == I2C_STAT_XRDY) {
528                         i2c_error = 2;
529                         printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
530                                status);
531                         goto rd_exit;
532                 }
533                 if (status == 0 || (status & I2C_STAT_NACK)) {
534                         i2c_error = 1;
535                         goto rd_exit;
536                 }
537                 if (status & I2C_STAT_RRDY) {
538                         *buffer++ = readb(&i2c_base->data);
539                         writew(I2C_STAT_RRDY, &i2c_base->stat);
540                 }
541                 if (status & I2C_STAT_ARDY) {
542                         writew(I2C_STAT_ARDY, &i2c_base->stat);
543                         break;
544                 }
545         }
546
547 rd_exit:
548         flush_fifo(i2c_base);
549         writew(0xFFFF, &i2c_base->stat);
550         return i2c_error;
551 }
552
553 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
554 static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
555                               uint addr, int alen, uchar *buffer, int len)
556 {
557         int i;
558         u16 status;
559         int i2c_error = 0;
560         int timeout = I2C_TIMEOUT;
561
562         if (alen < 0) {
563                 puts("I2C write: addr len < 0\n");
564                 return 1;
565         }
566
567         if (len < 0) {
568                 puts("I2C write: data len < 0\n");
569                 return 1;
570         }
571
572         if (buffer == NULL) {
573                 puts("I2C write: NULL pointer passed\n");
574                 return 1;
575         }
576
577         if (alen > 2) {
578                 printf("I2C write: addr len %d not supported\n", alen);
579                 return 1;
580         }
581
582         if (addr + len > (1 << 16)) {
583                 printf("I2C write: address 0x%x + 0x%x out of range\n",
584                        addr, len);
585                 return 1;
586         }
587
588 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
589         /*
590          * EEPROM chips that implement "address overflow" are ones
591          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
592          * address and the extra bits end up in the "chip address"
593          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
594          * four 256 byte chips.
595          *
596          * Note that we consider the length of the address field to
597          * still be one byte because the extra address bits are
598          * hidden in the chip address.
599          */
600         if (alen > 0)
601                 chip |= ((addr >> (alen * 8)) &
602                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
603 #endif
604
605         /* Wait until bus not busy */
606         if (wait_for_bb(i2c_base, waitdelay))
607                 return 1;
608
609         /* Start address phase - will write regoffset + len bytes data */
610         writew(alen + len, &i2c_base->cnt);
611         /* Set slave address */
612         writew(chip, &i2c_base->sa);
613         /* Stop bit needed here */
614         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
615                I2C_CON_STP, &i2c_base->con);
616
617         while (alen) {
618                 /* Must write reg offset (one or two bytes) */
619                 status = wait_for_event(i2c_base, waitdelay);
620                 /* Try to identify bus that is not padconf'd for I2C */
621                 if (status == I2C_STAT_XRDY) {
622                         i2c_error = 2;
623                         printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
624                                status);
625                         goto wr_exit;
626                 }
627                 if (status == 0 || (status & I2C_STAT_NACK)) {
628                         i2c_error = 1;
629                         printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
630                                status);
631                         goto wr_exit;
632                 }
633                 if (status & I2C_STAT_XRDY) {
634                         alen--;
635                         writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
636                         writew(I2C_STAT_XRDY, &i2c_base->stat);
637                 } else {
638                         i2c_error = 1;
639                         printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
640                                status);
641                         goto wr_exit;
642                 }
643         }
644         /* Address phase is over, now write data */
645         for (i = 0; i < len; i++) {
646                 status = wait_for_event(i2c_base, waitdelay);
647                 if (status == 0 || (status & I2C_STAT_NACK)) {
648                         i2c_error = 1;
649                         printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
650                                status);
651                         goto wr_exit;
652                 }
653                 if (status & I2C_STAT_XRDY) {
654                         writeb(buffer[i], &i2c_base->data);
655                         writew(I2C_STAT_XRDY, &i2c_base->stat);
656                 } else {
657                         i2c_error = 1;
658                         printf("i2c_write: bus not ready for data Tx (i=%d)\n",
659                                i);
660                         goto wr_exit;
661                 }
662         }
663         /*
664          * poll ARDY bit for making sure that last byte really has been
665          * transferred on the bus.
666          */
667         do {
668                 status = wait_for_event(i2c_base, waitdelay);
669         } while (!(status & I2C_STAT_ARDY) && timeout--);
670         if (timeout <= 0)
671                 printf("i2c_write: timed out writig last byte!\n");
672
673 wr_exit:
674         flush_fifo(i2c_base);
675         writew(0xFFFF, &i2c_base->stat);
676         return i2c_error;
677 }
678
679 #ifndef CONFIG_DM_I2C
680 /*
681  * The legacy I2C functions. These need to get removed once
682  * all users of this driver are converted to DM.
683  */
684 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
685 {
686         switch (adap->hwadapnr) {
687         case 0:
688                 return (struct i2c *)I2C_BASE1;
689                 break;
690         case 1:
691                 return (struct i2c *)I2C_BASE2;
692                 break;
693 #if (I2C_BUS_MAX > 2)
694         case 2:
695                 return (struct i2c *)I2C_BASE3;
696                 break;
697 #if (I2C_BUS_MAX > 3)
698         case 3:
699                 return (struct i2c *)I2C_BASE4;
700                 break;
701 #if (I2C_BUS_MAX > 4)
702         case 4:
703                 return (struct i2c *)I2C_BASE5;
704                 break;
705 #endif
706 #endif
707 #endif
708         default:
709                 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
710                 break;
711         }
712         return NULL;
713 }
714
715
716 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
717                            int alen, uchar *buffer, int len)
718 {
719         struct i2c *i2c_base = omap24_get_base(adap);
720
721         return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
722                                  alen, buffer, len);
723 }
724
725
726 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
727                             int alen, uchar *buffer, int len)
728 {
729         struct i2c *i2c_base = omap24_get_base(adap);
730
731         return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
732                                   alen, buffer, len);
733 }
734
735 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
736 {
737         struct i2c *i2c_base = omap24_get_base(adap);
738         int ret;
739
740         ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
741         if (ret) {
742                 error("%s: set i2c speed failed\n", __func__);
743                 return ret;
744         }
745
746         adap->speed = speed;
747
748         return 0;
749 }
750
751 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
752 {
753         struct i2c *i2c_base = omap24_get_base(adap);
754
755         return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
756 }
757
758 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
759 {
760         struct i2c *i2c_base = omap24_get_base(adap);
761
762         return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
763 }
764
765 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
766 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
767 #endif
768 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
769 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
770 #endif
771
772 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
773                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
774                          CONFIG_SYS_OMAP24_I2C_SPEED,
775                          CONFIG_SYS_OMAP24_I2C_SLAVE,
776                          0)
777 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
778                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
779                          CONFIG_SYS_OMAP24_I2C_SPEED1,
780                          CONFIG_SYS_OMAP24_I2C_SLAVE1,
781                          1)
782 #if (I2C_BUS_MAX > 2)
783 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
784 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
785 #endif
786 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
787 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
788 #endif
789
790 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
791                          omap24_i2c_read, omap24_i2c_write, NULL,
792                          CONFIG_SYS_OMAP24_I2C_SPEED2,
793                          CONFIG_SYS_OMAP24_I2C_SLAVE2,
794                          2)
795 #if (I2C_BUS_MAX > 3)
796 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
797 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
798 #endif
799 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
800 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
801 #endif
802
803 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
804                          omap24_i2c_read, omap24_i2c_write, NULL,
805                          CONFIG_SYS_OMAP24_I2C_SPEED3,
806                          CONFIG_SYS_OMAP24_I2C_SLAVE3,
807                          3)
808 #if (I2C_BUS_MAX > 4)
809 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
810 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
811 #endif
812 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
813 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
814 #endif
815
816 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
817                          omap24_i2c_read, omap24_i2c_write, NULL,
818                          CONFIG_SYS_OMAP24_I2C_SPEED4,
819                          CONFIG_SYS_OMAP24_I2C_SLAVE4,
820                          4)
821 #endif
822 #endif
823 #endif
824
825 #else /* CONFIG_DM_I2C */
826
827 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
828 {
829         struct omap_i2c *priv = dev_get_priv(bus);
830         int ret;
831
832         debug("i2c_xfer: %d messages\n", nmsgs);
833         for (; nmsgs > 0; nmsgs--, msg++) {
834                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
835                 if (msg->flags & I2C_M_RD) {
836                         ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
837                                                 msg->addr, 0, 0, msg->buf,
838                                                 msg->len);
839                 } else {
840                         ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
841                                                  msg->addr, 0, 0, msg->buf,
842                                                  msg->len);
843                 }
844                 if (ret) {
845                         debug("i2c_write: error sending\n");
846                         return -EREMOTEIO;
847                 }
848         }
849
850         return 0;
851 }
852
853 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
854 {
855         struct omap_i2c *priv = dev_get_priv(bus);
856
857         priv->speed = speed;
858
859         return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
860 }
861
862 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
863                                      uint chip_flags)
864 {
865         struct omap_i2c *priv = dev_get_priv(bus);
866
867         return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
868 }
869
870 static int omap_i2c_probe(struct udevice *bus)
871 {
872         struct omap_i2c *priv = dev_get_priv(bus);
873
874         __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
875
876         return 0;
877 }
878
879 static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
880 {
881         struct omap_i2c *priv = dev_get_priv(bus);
882
883         priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *),
884                                  MAP_NOCACHE);
885         priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
886
887         return 0;
888 }
889
890 static const struct dm_i2c_ops omap_i2c_ops = {
891         .xfer           = omap_i2c_xfer,
892         .probe_chip     = omap_i2c_probe_chip,
893         .set_bus_speed  = omap_i2c_set_bus_speed,
894 };
895
896 static const struct udevice_id omap_i2c_ids[] = {
897         { .compatible = "ti,omap4-i2c" },
898         { }
899 };
900
901 U_BOOT_DRIVER(i2c_omap) = {
902         .name   = "i2c_omap",
903         .id     = UCLASS_I2C,
904         .of_match = omap_i2c_ids,
905         .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
906         .probe  = omap_i2c_probe,
907         .priv_auto_alloc_size = sizeof(struct omap_i2c),
908         .ops    = &omap_i2c_ops,
909         .flags  = DM_FLAG_PRE_RELOC,
910 };
911
912 #endif /* CONFIG_DM_I2C */