2 * (C) Copyright 2007-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
10 * SPDX-License-Identifier: GPL-2.0+
12 * NOTE: This driver should be converted to driver model before June 2017.
13 * Please see doc/driver-model/i2c-howto.txt for instructions.
17 #include <asm/ppc4xx.h>
18 #include <asm/ppc4xx-i2c.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr)
28 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
29 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
30 defined(CONFIG_460EX) || defined(CONFIG_460GT)
31 base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100);
32 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
33 /* all remaining 440 variants */
34 base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100);
36 /* all 405 variants */
37 base = 0xEF600500 + (hwadapnr * 0x100);
39 return (struct ppc4xx_i2c *)base;
42 static void _i2c_bus_reset(struct i2c_adapter *adap)
44 struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
48 /* Reset status register */
49 /* write 1 in SCMP and IRQA to clear these fields */
50 out_8(&i2c->sts, 0x0A);
52 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
53 out_8(&i2c->extsts, 0x8F);
55 /* Place chip in the reset state */
56 out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
58 /* Check if bus is free */
59 dc = in_8(&i2c->directcntl);
60 if (!DIRCTNL_FREE(dc)){
61 /* Try to set bus free state */
62 out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
64 /* Wait until we regain bus control */
65 for (i = 0; i < 100; ++i) {
66 dc = in_8(&i2c->directcntl);
71 dc ^= IIC_DIRCNTL_SCC;
72 out_8(&i2c->directcntl, dc);
74 dc ^= IIC_DIRCNTL_SCC;
75 out_8(&i2c->directcntl, dc);
80 out_8(&i2c->xtcntlss, 0);
83 static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
85 struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
88 #ifdef CONFIG_SYS_I2C_INIT_BOARD
90 * Call board specific i2c bus reset routine before accessing the
91 * environment, which might be in a chip on that bus. For details
92 * about this problem see doc/I2C_Edge_Conditions.
97 /* Handle possible failed I2C state */
98 /* FIXME: put this into i2c_init_board()? */
101 /* clear lo master address */
102 out_8(&i2c->lmadr, 0);
104 /* clear hi master address */
105 out_8(&i2c->hmadr, 0);
107 /* clear lo slave address */
108 out_8(&i2c->lsadr, 0);
110 /* clear hi slave address */
111 out_8(&i2c->hsadr, 0);
113 /* Clock divide Register */
114 /* set divisor according to freq_opb */
115 divisor = (get_OPB_freq() - 1) / 10000000;
118 out_8(&i2c->clkdiv, divisor);
121 out_8(&i2c->intrmsk, 0);
123 /* clear transfer count */
124 out_8(&i2c->xfrcnt, 0);
126 /* clear extended control & stat */
127 /* write 1 in SRC SRS SWC SWS to clear these fields */
128 out_8(&i2c->xtcntlss, 0xF0);
130 /* Mode Control Register
131 Flush Slave/Master data buffer */
132 out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
134 val = in_8(&i2c->mdcntl);
136 /* Ignore General Call, slave transfers are ignored,
137 * disable interrupts, exit unknown bus state, enable hold
138 * SCL 100kHz normaly or FastMode for 400kHz and above
141 val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
143 val |= IIC_MDCNTL_FSM;
144 out_8(&i2c->mdcntl, val);
146 /* clear control reg */
147 out_8(&i2c->cntl, 0x00);
151 * This code tries to use the features of the 405GP i2c
152 * controller. It will transfer up to 4 bytes in one pass
153 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
154 * is possible to do out16(lhz) transfers.
156 * cmd_type is 0 for write 1 for read.
158 * addr_len can take any value from 0-255, it is only limited
159 * by the char, we could make it larger if needed. If it is
160 * 0 we skip the address write cycle.
162 * Typical case is a Write of an addr followd by a Read. The
163 * IBM FAQ does not cover this. On the last byte of the write
164 * we don't set the creg CHT bit but the RPST bit.
166 * It does not support address only transfers, there must be
167 * a data part. If you want to write the address yourself, put
168 * it in the data pointer.
170 * It does not support transfer to/from address 0.
172 * It does not check XFRCNT.
174 static int _i2c_transfer(struct i2c_adapter *adap,
175 unsigned char cmd_type,
177 unsigned char addr[],
178 unsigned char addr_len,
179 unsigned char data[],
180 unsigned short data_len)
182 struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
191 if (data == 0 || data_len == 0) {
192 /* Don't support data transfer of no length or to address 0 */
193 printf( "i2c_transfer: bad call\n" );
196 if (addr && addr_len) {
206 /* Clear Stop Complete Bit */
207 out_8(&i2c->sts, IIC_STS_SCMP);
213 status = in_8(&i2c->sts);
215 } while ((status & IIC_STS_PT) && (i > 0));
217 if (status & IIC_STS_PT) {
218 result = IIC_NOK_TOUT;
222 /* flush the Master/Slave Databuffers */
223 out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
224 IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
226 /* need to wait 4 OPB clocks? code below should take that long */
228 /* 7-bit adressing */
229 out_8(&i2c->hmadr, 0);
230 out_8(&i2c->lmadr, chip);
236 while (tran != cnt && (result == IIC_OK)) {
241 * Normal transfer, 7-bits adressing, Transfer up to
242 * bc bytes, Normal start, Transfer is a sequence of transfers
246 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
247 creg |= (bc - 1) << 4;
248 /* if the real cmd type is write continue trans */
249 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
250 creg |= IIC_CNTL_CHT;
252 /* last part of address, prepare for repeated start on read */
253 if (cmd_type && (ptr == addr) && ((tran + bc) == cnt))
254 creg |= IIC_CNTL_RPST;
257 creg |= IIC_CNTL_READ;
259 for(j = 0; j < bc; j++) {
261 out_8(&i2c->mdbuf, ptr[tran + j]);
264 out_8(&i2c->cntl, creg);
267 * Transfer is in progress
268 * we have to wait for upto 5 bytes of data
269 * 1 byte chip address+r/w bit then bc bytes
271 * udelay(10) is 1 bit time at 100khz
272 * Doubled for slop. 20 is too small.
277 status = in_8(&i2c->sts);
280 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
283 if (status & IIC_STS_ERR) {
285 status = in_8(&i2c->extsts);
286 /* Lost arbitration? */
287 if (status & IIC_EXTSTS_LA)
289 /* Incomplete transfer? */
290 if (status & IIC_EXTSTS_ICT)
291 result = IIC_NOK_ICT;
292 /* Transfer aborted? */
293 if (status & IIC_EXTSTS_XFRA)
294 result = IIC_NOK_XFRA;
296 * If error happened during combined xfer
297 * IIC interface is usually stuck in some strange
298 * state without a valid stop condition.
299 * Brute, but working: generate stop, then soft reset.
301 if ((status & IIC_EXTSTS_BCS_MASK)
302 != IIC_EXTSTS_BCS_FREE){
303 u8 mdcntl = in_8(&i2c->mdcntl);
305 /* Generate valid stop condition */
306 out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
307 out_8(&i2c->directcntl, IIC_DIRCNTL_SCC);
309 out_8(&i2c->directcntl,
310 IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC);
311 out_8(&i2c->xtcntlss, 0);
313 ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM)
314 ? 400000 : 100000, 0);
316 } else if ( status & IIC_STS_PT) {
317 result = IIC_NOK_TOUT;
320 /* Command is reading => get buffer */
321 if ((reading) && (result == IIC_OK)) {
322 /* Are there data in buffer */
323 if (status & IIC_STS_MDBS) {
325 * even if we have data we have to wait 4OPB
326 * clocks for it to hit the front of the FIFO,
327 * after that we can just read. We should check
328 * XFCNT here and if the FIFO is full there is
332 for (j = 0; j < bc; j++)
333 ptr[tran + j] = in_8(&i2c->mdbuf);
335 result = IIC_NOK_DATA;
339 if (ptr == addr && tran == cnt) {
349 static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip)
356 * What is needed is to send the chip address and verify that the
357 * address was <ACK>ed (i.e. there was a chip at that address which
358 * drove the data line low).
360 return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0);
363 static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr,
364 int alen, uchar *buffer, int len, int read)
370 printf("I2C: addr len %d not supported\n", alen);
375 xaddr[0] = (addr >> 24) & 0xFF;
376 xaddr[1] = (addr >> 16) & 0xFF;
377 xaddr[2] = (addr >> 8) & 0xFF;
378 xaddr[3] = addr & 0xFF;
382 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
384 * EEPROM chips that implement "address overflow" are ones
385 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
386 * address and the extra bits end up in the "chip address"
387 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
388 * four 256 byte chips.
390 * Note that we consider the length of the address field to
391 * still be one byte because the extra address bits are
392 * hidden in the chip address.
395 chip |= ((addr >> (alen * 8)) &
396 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
398 ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen,
401 printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
408 static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
409 int alen, uchar *buffer, int len)
411 return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1);
414 static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
415 int alen, uchar *buffer, int len)
417 return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
420 static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap,
423 if (speed != adap->speed)
429 * Register ppc4xx i2c adapters
431 #ifdef CONFIG_SYS_I2C_PPC4XX_CH0
432 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe,
433 ppc4xx_i2c_read, ppc4xx_i2c_write,
434 ppc4xx_i2c_set_bus_speed,
435 CONFIG_SYS_I2C_PPC4XX_SPEED_0,
436 CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0)
438 #ifdef CONFIG_SYS_I2C_PPC4XX_CH1
439 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe,
440 ppc4xx_i2c_read, ppc4xx_i2c_write,
441 ppc4xx_i2c_set_bus_speed,
442 CONFIG_SYS_I2C_PPC4XX_SPEED_1,
443 CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1)