3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
12 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
13 #include <asm/arch/clk.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
17 #include <asm/arch/s3c24x0_cpu.h>
21 #include "s3c24x0_i2c.h"
23 #ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
24 #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
26 #define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
29 DECLARE_GLOBAL_DATA_PTR;
32 * Wait til the byte transfer is completed.
34 * @param i2c- pointer to the appropriate i2c register bank.
35 * @return I2C_OK, if transmission was ACKED
36 * I2C_NACK, if transmission was NACKED
37 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
40 static int WaitForXfer(struct s3c24x0_i2c *i2c)
42 ulong start_time = get_timer(0);
45 if (readl(&i2c->iiccon) & I2CCON_IRPND)
46 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
48 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
53 static void read_write_byte(struct s3c24x0_i2c *i2c)
55 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
58 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
60 ulong freq, pres = 16, div;
61 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
66 /* calculate prescaler and divisor values */
67 if ((freq / pres / (16 + 1)) > speed)
68 /* set prescaler to 512 */
72 while ((freq / pres / (div + 1)) > speed)
75 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
76 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
78 /* init to SLAVE REVEIVE and set slaveaddr */
79 writel(0, &i2c->iicstat);
80 writel(slaveadd, &i2c->iicadd);
81 /* program Master Transmit (and implicit STOP) */
82 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
85 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
87 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
89 i2c_bus->clock_frequency = speed;
91 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
92 SYS_I2C_S3C24X0_SLAVE_ADDR);
98 * cmd_type is 0 for write, 1 for read.
100 * addr_len can take any value from 0-255, it is only limited
101 * by the char, we could make it larger if needed. If it is
102 * 0 we skip the address write cycle.
104 static int i2c_transfer(struct s3c24x0_i2c *i2c,
105 unsigned char cmd_type,
107 unsigned char addr[],
108 unsigned char addr_len,
109 unsigned char data[],
110 unsigned short data_len)
113 ulong start_time = get_timer(0);
115 if (data == 0 || data_len == 0) {
116 /*Don't support data transfer of no length or to address 0 */
117 debug("i2c_transfer: bad call\n");
121 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
122 if (get_timer(start_time) > I2C_TIMEOUT_MS)
126 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
128 /* Get the slave chip address going */
129 writel(chip, &i2c->iicds);
130 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
131 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
134 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
137 /* Wait for chip address to transmit. */
138 result = WaitForXfer(i2c);
139 if (result != I2C_OK)
142 /* If register address needs to be transmitted - do it now. */
143 if (addr && addr_len) {
144 while ((i < addr_len) && (result == I2C_OK)) {
145 writel(addr[i++], &i2c->iicds);
146 read_write_byte(i2c);
147 result = WaitForXfer(i2c);
150 if (result != I2C_OK)
156 while ((i < data_len) && (result == I2C_OK)) {
157 writel(data[i++], &i2c->iicds);
158 read_write_byte(i2c);
159 result = WaitForXfer(i2c);
164 if (addr && addr_len) {
166 * Register address has been sent, now send slave chip
167 * address again to start the actual read transaction.
169 writel(chip, &i2c->iicds);
171 /* Generate a re-START. */
172 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
174 read_write_byte(i2c);
175 result = WaitForXfer(i2c);
177 if (result != I2C_OK)
181 while ((i < data_len) && (result == I2C_OK)) {
182 /* disable ACK for final READ */
183 if (i == data_len - 1)
184 writel(readl(&i2c->iiccon)
187 read_write_byte(i2c);
188 result = WaitForXfer(i2c);
189 data[i++] = readl(&i2c->iicds);
191 if (result == I2C_NACK)
192 result = I2C_OK; /* Normal terminated read. */
196 debug("i2c_transfer: bad call\n");
203 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
204 read_write_byte(i2c);
209 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
211 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
218 * What is needed is to send the chip address and verify that the
219 * address was <ACK>ed (i.e. there was a chip at that address which
220 * drove the data line low).
222 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
224 return ret != I2C_OK;
227 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
230 struct s3c24x0_i2c *i2c = i2c_bus->regs;
231 bool is_read = msg->flags & I2C_M_RD;
237 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
239 /* Get the slave chip address going */
240 addr = msg->addr << 1;
241 writel(addr, &i2c->iicds);
242 status = I2C_TXRX_ENA | I2C_START_STOP;
244 status |= I2C_MODE_MR;
246 status |= I2C_MODE_MT;
247 writel(status, &i2c->iicstat);
249 read_write_byte(i2c);
251 /* Wait for chip address to transmit */
252 ret = WaitForXfer(i2c);
257 for (i = 0; !ret && i < msg->len; i++) {
258 /* disable ACK for final READ */
259 if (i == msg->len - 1)
260 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
261 read_write_byte(i2c);
262 ret = WaitForXfer(i2c);
263 msg->buf[i] = readl(&i2c->iicds);
266 ret = I2C_OK; /* Normal terminated read */
268 for (i = 0; !ret && i < msg->len; i++) {
269 writel(msg->buf[i], &i2c->iicds);
270 read_write_byte(i2c);
271 ret = WaitForXfer(i2c);
279 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
282 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
283 struct s3c24x0_i2c *i2c = i2c_bus->regs;
287 start_time = get_timer(0);
288 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
289 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
295 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
296 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
299 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
300 read_write_byte(i2c);
302 return ret ? -EREMOTEIO : 0;
305 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
307 const void *blob = gd->fdt_blob;
308 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
311 node = dev_of_offset(dev);
313 i2c_bus->regs = (struct s3c24x0_i2c *)devfdt_get_addr(dev);
315 i2c_bus->id = pinmux_decode_periph_id(blob, node);
317 i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
318 "clock-frequency", 100000);
319 i2c_bus->node = node;
320 i2c_bus->bus_num = dev->seq;
322 exynos_pinmux_config(i2c_bus->id, 0);
324 i2c_bus->active = true;
329 static const struct dm_i2c_ops s3c_i2c_ops = {
330 .xfer = s3c24x0_i2c_xfer,
331 .probe_chip = s3c24x0_i2c_probe,
332 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
335 static const struct udevice_id s3c_i2c_ids[] = {
336 { .compatible = "samsung,s3c2440-i2c" },
340 U_BOOT_DRIVER(i2c_s3c) = {
343 .of_match = s3c_i2c_ids,
344 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
345 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),