git.sur5r.net Git - u-boot/blob - drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* This code should work for both the S3C2400 and the S3C2410
   9  * as they seem to have the same I2C controller inside.
  10  * The different address mapping is handled by the s3c24xx.h files below.
  11  */
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <dm.h>
  15 #include <fdtdec.h>
  16 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  17 #include <asm/arch/clk.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/pinmux.h>
  20 #else
  21 #include <asm/arch/s3c24x0_cpu.h>
  22 #endif
  23 #include <asm/io.h>
  24 #include <i2c.h>
  25 #include "s3c24x0_i2c.h"
  26
  27 #define I2C_WRITE       0
  28 #define I2C_READ        1
  29
  30 #define I2C_OK          0
  31 #define I2C_NOK         1
  32 #define I2C_NACK        2
  33 #define I2C_NOK_LA      3       /* Lost arbitration */
  34 #define I2C_NOK_TOUT    4       /* time out */
  35
  36 /* HSI2C specific register description */
  37
  38 /* I2C_CTL Register bits */
  39 #define HSI2C_FUNC_MODE_I2C             (1u << 0)
  40 #define HSI2C_MASTER                    (1u << 3)
  41 #define HSI2C_RXCHON                    (1u << 6)       /* Write/Send */
  42 #define HSI2C_TXCHON                    (1u << 7)       /* Read/Receive */
  43 #define HSI2C_SW_RST                    (1u << 31)
  44
  45 /* I2C_FIFO_CTL Register bits */
  46 #define HSI2C_RXFIFO_EN                 (1u << 0)
  47 #define HSI2C_TXFIFO_EN                 (1u << 1)
  48 #define HSI2C_TXFIFO_TRIGGER_LEVEL      (0x20 << 16)
  49 #define HSI2C_RXFIFO_TRIGGER_LEVEL      (0x20 << 4)
  50
  51 /* I2C_TRAILING_CTL Register bits */
  52 #define HSI2C_TRAILING_COUNT            (0xff)
  53
  54 /* I2C_INT_EN Register bits */
  55 #define HSI2C_TX_UNDERRUN_EN            (1u << 2)
  56 #define HSI2C_TX_OVERRUN_EN             (1u << 3)
  57 #define HSI2C_RX_UNDERRUN_EN            (1u << 4)
  58 #define HSI2C_RX_OVERRUN_EN             (1u << 5)
  59 #define HSI2C_INT_TRAILING_EN           (1u << 6)
  60 #define HSI2C_INT_I2C_EN                (1u << 9)
  61
  62 #define HSI2C_INT_ERROR_MASK    (HSI2C_TX_UNDERRUN_EN |\
  63                                  HSI2C_TX_OVERRUN_EN  |\
  64                                  HSI2C_RX_UNDERRUN_EN |\
  65                                  HSI2C_RX_OVERRUN_EN  |\
  66                                  HSI2C_INT_TRAILING_EN)
  67
  68 /* I2C_CONF Register bits */
  69 #define HSI2C_AUTO_MODE                 (1u << 31)
  70 #define HSI2C_10BIT_ADDR_MODE           (1u << 30)
  71 #define HSI2C_HS_MODE                   (1u << 29)
  72
  73 /* I2C_AUTO_CONF Register bits */
  74 #define HSI2C_READ_WRITE                (1u << 16)
  75 #define HSI2C_STOP_AFTER_TRANS          (1u << 17)
  76 #define HSI2C_MASTER_RUN                (1u << 31)
  77
  78 /* I2C_TIMEOUT Register bits */
  79 #define HSI2C_TIMEOUT_EN                (1u << 31)
  80
  81 /* I2C_TRANS_STATUS register bits */
  82 #define HSI2C_MASTER_BUSY               (1u << 17)
  83 #define HSI2C_SLAVE_BUSY                (1u << 16)
  84 #define HSI2C_TIMEOUT_AUTO              (1u << 4)
  85 #define HSI2C_NO_DEV                    (1u << 3)
  86 #define HSI2C_NO_DEV_ACK                (1u << 2)
  87 #define HSI2C_TRANS_ABORT               (1u << 1)
  88 #define HSI2C_TRANS_SUCCESS             (1u << 0)
  89 #define HSI2C_TRANS_ERROR_MASK  (HSI2C_TIMEOUT_AUTO |\
  90                                  HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  91                                  HSI2C_TRANS_ABORT)
  92 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  93
  94
  95 /* I2C_FIFO_STAT Register bits */
  96 #define HSI2C_RX_FIFO_EMPTY             (1u << 24)
  97 #define HSI2C_RX_FIFO_FULL              (1u << 23)
  98 #define HSI2C_TX_FIFO_EMPTY             (1u << 8)
  99 #define HSI2C_TX_FIFO_FULL              (1u << 7)
 100 #define HSI2C_RX_FIFO_LEVEL(x)          (((x) >> 16) & 0x7f)
 101 #define HSI2C_TX_FIFO_LEVEL(x)          ((x) & 0x7f)
 102
 103 #define HSI2C_SLV_ADDR_MAS(x)           ((x & 0x3ff) << 10)
 104
 105 /* S3C I2C Controller bits */
 106 #define I2CSTAT_BSY     0x20    /* Busy bit */
 107 #define I2CSTAT_NACK    0x01    /* Nack bit */
 108 #define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
 109 #define I2CCON_IRPND    0x10    /* Interrupt pending bit */
 110 #define I2C_MODE_MT     0xC0    /* Master Transmit Mode */
 111 #define I2C_MODE_MR     0x80    /* Master Receive Mode */
 112 #define I2C_START_STOP  0x20    /* START / STOP */
 113 #define I2C_TXRX_ENA    0x10    /* I2C Tx/Rx enable */
 114
 115 #define I2C_TIMEOUT_MS 10               /* 10 ms */
 116
 117 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
 118
 119
 120 /* To support VCMA9 boards and other who dont define max_i2c_num */
 121 #ifndef CONFIG_MAX_I2C_NUM
 122 #define CONFIG_MAX_I2C_NUM 1
 123 #endif
 124
 125 DECLARE_GLOBAL_DATA_PTR;
 126
 127 /*
 128  * For SPL boot some boards need i2c before SDRAM is initialised so force
 129  * variables to live in SRAM
 130  */
 131 #ifdef CONFIG_SYS_I2C
 132 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
 133                         __attribute__((section(".data")));
 134 #endif
 135
 136 enum exynos_i2c_type {
 137         EXYNOS_I2C_STD,
 138         EXYNOS_I2C_HS,
 139 };
 140
 141 #ifdef CONFIG_SYS_I2C
 142 /**
 143  * Get a pointer to the given bus index
 144  *
 145  * @bus_idx: Bus index to look up
 146  * @return pointer to bus, or NULL if invalid or not available
 147  */
 148 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
 149 {
 150         if (bus_idx < ARRAY_SIZE(i2c_bus)) {
 151                 struct s3c24x0_i2c_bus *bus;
 152
 153                 bus = &i2c_bus[bus_idx];
 154                 if (bus->active)
 155                         return bus;
 156         }
 157
 158         debug("Undefined bus: %d\n", bus_idx);
 159         return NULL;
 160 }
 161 #endif
 162
 163 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 164 static int GetI2CSDA(void)
 165 {
 166         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 167
 168 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 169         return (readl(&gpio->gpedat) & 0x8000) >> 15;
 170 #endif
 171 #ifdef CONFIG_S3C2400
 172         return (readl(&gpio->pgdat) & 0x0020) >> 5;
 173 #endif
 174 }
 175
 176 static void SetI2CSCL(int x)
 177 {
 178         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 179
 180 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 181         writel((readl(&gpio->gpedat) & ~0x4000) |
 182                                         (x & 1) << 14, &gpio->gpedat);
 183 #endif
 184 #ifdef CONFIG_S3C2400
 185         writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
 186 #endif
 187 }
 188 #endif
 189
 190 /*
 191  * Wait til the byte transfer is completed.
 192  *
 193  * @param i2c- pointer to the appropriate i2c register bank.
 194  * @return I2C_OK, if transmission was ACKED
 195  *         I2C_NACK, if transmission was NACKED
 196  *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
 197  */
 198
 199 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 200 {
 201         ulong start_time = get_timer(0);
 202
 203         do {
 204                 if (readl(&i2c->iiccon) & I2CCON_IRPND)
 205                         return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
 206                                 I2C_NACK : I2C_OK;
 207         } while (get_timer(start_time) < I2C_TIMEOUT_MS);
 208
 209         return I2C_NOK_TOUT;
 210 }
 211
 212 /*
 213  * Wait for transfer completion.
 214  *
 215  * This function reads the interrupt status register waiting for the INT_I2C
 216  * bit to be set, which indicates copletion of a transaction.
 217  *
 218  * @param i2c: pointer to the appropriate register bank
 219  *
 220  * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
 221  *          the status bits do not get set in time, or an approrpiate error
 222  *          value in case of transfer errors.
 223  */
 224 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
 225 {
 226         int i = HSI2C_TIMEOUT_US;
 227
 228         while (i-- > 0) {
 229                 u32 int_status = readl(&i2c->usi_int_stat);
 230
 231                 if (int_status & HSI2C_INT_I2C_EN) {
 232                         u32 trans_status = readl(&i2c->usi_trans_status);
 233
 234                         /* Deassert pending interrupt. */
 235                         writel(int_status, &i2c->usi_int_stat);
 236
 237                         if (trans_status & HSI2C_NO_DEV_ACK) {
 238                                 debug("%s: no ACK from device\n", __func__);
 239                                 return I2C_NACK;
 240                         }
 241                         if (trans_status & HSI2C_NO_DEV) {
 242                                 debug("%s: no device\n", __func__);
 243                                 return I2C_NOK;
 244                         }
 245                         if (trans_status & HSI2C_TRANS_ABORT) {
 246                                 debug("%s: arbitration lost\n", __func__);
 247                                 return I2C_NOK_LA;
 248                         }
 249                         if (trans_status & HSI2C_TIMEOUT_AUTO) {
 250                                 debug("%s: device timed out\n", __func__);
 251                                 return I2C_NOK_TOUT;
 252                         }
 253                         return I2C_OK;
 254                 }
 255                 udelay(1);
 256         }
 257         debug("%s: transaction timeout!\n", __func__);
 258         return I2C_NOK_TOUT;
 259 }
 260
 261 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 262 {
 263         writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 264 }
 265
 266 #ifdef CONFIG_SYS_I2C
 267 static struct s3c24x0_i2c *get_base_i2c(int bus)
 268 {
 269 #ifdef CONFIG_EXYNOS4
 270         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 271                                                         + (EXYNOS4_I2C_SPACING
 272                                                         * bus));
 273         return i2c;
 274 #elif defined CONFIG_EXYNOS5
 275         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 276                                                         + (EXYNOS5_I2C_SPACING
 277                                                         * bus));
 278         return i2c;
 279 #else
 280         return s3c24x0_get_base_i2c();
 281 #endif
 282 }
 283 #endif
 284
 285 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 286 {
 287         ulong freq, pres = 16, div;
 288 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 289         freq = get_i2c_clk();
 290 #else
 291         freq = get_PCLK();
 292 #endif
 293         /* calculate prescaler and divisor values */
 294         if ((freq / pres / (16 + 1)) > speed)
 295                 /* set prescaler to 512 */
 296                 pres = 512;
 297
 298         div = 0;
 299         while ((freq / pres / (div + 1)) > speed)
 300                 div++;
 301
 302         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
 303         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 304
 305         /* init to SLAVE REVEIVE and set slaveaddr */
 306         writel(0, &i2c->iicstat);
 307         writel(slaveadd, &i2c->iicadd);
 308         /* program Master Transmit (and implicit STOP) */
 309         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 310 }
 311
 312 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 313 {
 314         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 315         ulong clkin;
 316         unsigned int op_clk = i2c_bus->clock_frequency;
 317         unsigned int i = 0, utemp0 = 0, utemp1 = 0;
 318         unsigned int t_ftl_cycle;
 319
 320 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 321         clkin = get_i2c_clk();
 322 #else
 323         clkin = get_PCLK();
 324 #endif
 325         /* FPCLK / FI2C =
 326          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 327          * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
 328          * uTemp1 = (TSCLK_L + TSCLK_H + 2)
 329          * uTemp2 = TSCLK_L + TSCLK_H
 330          */
 331         t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
 332         utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
 333
 334         /* CLK_DIV max is 256 */
 335         for (i = 0; i < 256; i++) {
 336                 utemp1 = utemp0 / (i + 1);
 337                 if ((utemp1 < 512) && (utemp1 > 4)) {
 338                         i2c_bus->clk_cycle = utemp1 - 2;
 339                         i2c_bus->clk_div = i;
 340                         return 0;
 341                 }
 342         }
 343         return -EINVAL;
 344 }
 345
 346 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
 347 {
 348         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 349         unsigned int t_sr_release;
 350         unsigned int n_clkdiv;
 351         unsigned int t_start_su, t_start_hd;
 352         unsigned int t_stop_su;
 353         unsigned int t_data_su, t_data_hd;
 354         unsigned int t_scl_l, t_scl_h;
 355         u32 i2c_timing_s1;
 356         u32 i2c_timing_s2;
 357         u32 i2c_timing_s3;
 358         u32 i2c_timing_sla;
 359
 360         n_clkdiv = i2c_bus->clk_div;
 361         t_scl_l = i2c_bus->clk_cycle / 2;
 362         t_scl_h = i2c_bus->clk_cycle / 2;
 363         t_start_su = t_scl_l;
 364         t_start_hd = t_scl_l;
 365         t_stop_su = t_scl_l;
 366         t_data_su = t_scl_l / 2;
 367         t_data_hd = t_scl_l / 2;
 368         t_sr_release = i2c_bus->clk_cycle;
 369
 370         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 371         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 372         i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
 373         i2c_timing_sla = t_data_hd << 0;
 374
 375         writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
 376
 377         /* Clear to enable Timeout */
 378         clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
 379
 380         /* set AUTO mode */
 381         writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
 382
 383         /* Enable completion conditions' reporting. */
 384         writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
 385
 386         /* Enable FIFOs */
 387         writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
 388
 389         /* Currently operating in Fast speed mode. */
 390         writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
 391         writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
 392         writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
 393         writel(i2c_timing_sla, &hsregs->usi_timing_sla);
 394 }
 395
 396 /* SW reset for the high speed bus */
 397 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
 398 {
 399         struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
 400         u32 i2c_ctl;
 401
 402         /* Set and clear the bit for reset */
 403         i2c_ctl = readl(&i2c->usi_ctl);
 404         i2c_ctl |= HSI2C_SW_RST;
 405         writel(i2c_ctl, &i2c->usi_ctl);
 406
 407         i2c_ctl = readl(&i2c->usi_ctl);
 408         i2c_ctl &= ~HSI2C_SW_RST;
 409         writel(i2c_ctl, &i2c->usi_ctl);
 410
 411         /* Initialize the configure registers */
 412         hsi2c_ch_init(i2c_bus);
 413 }
 414
 415 #ifdef CONFIG_SYS_I2C
 416 static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 417 {
 418         struct s3c24x0_i2c *i2c;
 419         struct s3c24x0_i2c_bus *bus;
 420 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 421         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 422 #endif
 423         ulong start_time = get_timer(0);
 424
 425         i2c = get_base_i2c(adap->hwadapnr);
 426         bus = &i2c_bus[adap->hwadapnr];
 427         if (!bus)
 428                 return;
 429
 430         /*
 431          * In case the previous transfer is still going, wait to give it a
 432          * chance to finish.
 433          */
 434         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
 435                 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
 436                         printf("%s: I2C bus busy for %p\n", __func__,
 437                                &i2c->iicstat);
 438                         return;
 439                 }
 440         }
 441
 442 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 443         int i;
 444
 445         if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 446 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 447                 ulong old_gpecon = readl(&gpio->gpecon);
 448 #endif
 449 #ifdef CONFIG_S3C2400
 450                 ulong old_gpecon = readl(&gpio->pgcon);
 451 #endif
 452                 /* bus still busy probably by (most) previously interrupted
 453                    transfer */
 454
 455 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 456                 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 457                 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
 458                        &gpio->gpecon);
 459 #endif
 460 #ifdef CONFIG_S3C2400
 461                 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
 462                 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
 463                        &gpio->pgcon);
 464 #endif
 465
 466                 /* toggle I2CSCL until bus idle */
 467                 SetI2CSCL(0);
 468                 udelay(1000);
 469                 i = 10;
 470                 while ((i > 0) && (GetI2CSDA() != 1)) {
 471                         SetI2CSCL(1);
 472                         udelay(1000);
 473                         SetI2CSCL(0);
 474                         udelay(1000);
 475                         i--;
 476                 }
 477                 SetI2CSCL(1);
 478                 udelay(1000);
 479
 480                 /* restore pin functions */
 481 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 482                 writel(old_gpecon, &gpio->gpecon);
 483 #endif
 484 #ifdef CONFIG_S3C2400
 485                 writel(old_gpecon, &gpio->pgcon);
 486 #endif
 487         }
 488 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 489
 490         i2c_ch_init(i2c, speed, slaveadd);
 491
 492         bus->active = true;
 493         bus->regs = i2c;
 494 }
 495 #endif /* CONFIG_SYS_I2C */
 496
 497 /*
 498  * Poll the appropriate bit of the fifo status register until the interface is
 499  * ready to process the next byte or timeout expires.
 500  *
 501  * In addition to the FIFO status register this function also polls the
 502  * interrupt status register to be able to detect unexpected transaction
 503  * completion.
 504  *
 505  * When FIFO is ready to process the next byte, this function returns I2C_OK.
 506  * If in course of polling the INT_I2C assertion is detected, the function
 507  * returns I2C_NOK. If timeout happens before any of the above conditions is
 508  * met - the function returns I2C_NOK_TOUT;
 509
 510  * @param i2c: pointer to the appropriate i2c register bank.
 511  * @param rx_transfer: set to True if the receive transaction is in progress.
 512  * @return: as described above.
 513  */
 514 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
 515 {
 516         u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
 517         int i = HSI2C_TIMEOUT_US;
 518
 519         while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
 520                 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
 521                         /*
 522                          * There is a chance that assertion of
 523                          * HSI2C_INT_I2C_EN and deassertion of
 524                          * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
 525                          * give FIFO status priority and check it one more
 526                          * time before reporting interrupt. The interrupt will
 527                          * be reported next time this function is called.
 528                          */
 529                         if (rx_transfer &&
 530                             !(readl(&i2c->usi_fifo_stat) & fifo_bit))
 531                                 break;
 532                         return I2C_NOK;
 533                 }
 534                 if (!i--) {
 535                         debug("%s: FIFO polling timeout!\n", __func__);
 536                         return I2C_NOK_TOUT;
 537                 }
 538                 udelay(1);
 539         }
 540         return I2C_OK;
 541 }
 542
 543 /*
 544  * Preapre hsi2c transaction, either read or write.
 545  *
 546  * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
 547  * the 5420 UM.
 548  *
 549  * @param i2c: pointer to the appropriate i2c register bank.
 550  * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
 551  * @param len: number of bytes expected to be sent or received
 552  * @param rx_transfer: set to true for receive transactions
 553  * @param: issue_stop: set to true if i2c stop condition should be generated
 554  *         after this transaction.
 555  * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
 556  *          I2C_OK otherwise.
 557  */
 558 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
 559                                      u8 chip,
 560                                      u16 len,
 561                                      bool rx_transfer,
 562                                      bool issue_stop)
 563 {
 564         u32 conf;
 565
 566         conf = len | HSI2C_MASTER_RUN;
 567
 568         if (issue_stop)
 569                 conf |= HSI2C_STOP_AFTER_TRANS;
 570
 571         /* Clear to enable Timeout */
 572         writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
 573
 574         /* Set slave address */
 575         writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
 576
 577         if (rx_transfer) {
 578                 /* i2c master, read transaction */
 579                 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 580                        &i2c->usi_ctl);
 581
 582                 /* read up to len bytes, stop after transaction is finished */
 583                 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
 584         } else {
 585                 /* i2c master, write transaction */
 586                 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 587                        &i2c->usi_ctl);
 588
 589                 /* write up to len bytes, stop after transaction is finished */
 590                 writel(conf, &i2c->usi_auto_conf);
 591         }
 592
 593         /* Reset all pending interrupt status bits we care about, if any */
 594         writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
 595
 596         return I2C_OK;
 597 }
 598
 599 /*
 600  * Wait while i2c bus is settling down (mostly stop gets completed).
 601  */
 602 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
 603 {
 604         int i = HSI2C_TIMEOUT_US;
 605
 606         while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
 607                 if (!i--) {
 608                         debug("%s: bus busy\n", __func__);
 609                         return I2C_NOK_TOUT;
 610                 }
 611                 udelay(1);
 612         }
 613         return I2C_OK;
 614 }
 615
 616 static int hsi2c_write(struct exynos5_hsi2c *i2c,
 617                        unsigned char chip,
 618                        unsigned char addr[],
 619                        unsigned char alen,
 620                        unsigned char data[],
 621                        unsigned short len,
 622                        bool issue_stop)
 623 {
 624         int i, rv = 0;
 625
 626         if (!(len + alen)) {
 627                 /* Writes of zero length not supported in auto mode. */
 628                 debug("%s: zero length writes not supported\n", __func__);
 629                 return I2C_NOK;
 630         }
 631
 632         rv = hsi2c_prepare_transaction
 633                 (i2c, chip, len + alen, false, issue_stop);
 634         if (rv != I2C_OK)
 635                 return rv;
 636
 637         /* Move address, if any, and the data, if any, into the FIFO. */
 638         for (i = 0; i < alen; i++) {
 639                 rv = hsi2c_poll_fifo(i2c, false);
 640                 if (rv != I2C_OK) {
 641                         debug("%s: address write failed\n", __func__);
 642                         goto write_error;
 643                 }
 644                 writel(addr[i], &i2c->usi_txdata);
 645         }
 646
 647         for (i = 0; i < len; i++) {
 648                 rv = hsi2c_poll_fifo(i2c, false);
 649                 if (rv != I2C_OK) {
 650                         debug("%s: data write failed\n", __func__);
 651                         goto write_error;
 652                 }
 653                 writel(data[i], &i2c->usi_txdata);
 654         }
 655
 656         rv = hsi2c_wait_for_trx(i2c);
 657
 658  write_error:
 659         if (issue_stop) {
 660                 int tmp_ret = hsi2c_wait_while_busy(i2c);
 661                 if (rv == I2C_OK)
 662                         rv = tmp_ret;
 663         }
 664
 665         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 666         return rv;
 667 }
 668
 669 static int hsi2c_read(struct exynos5_hsi2c *i2c,
 670                       unsigned char chip,
 671                       unsigned char addr[],
 672                       unsigned char alen,
 673                       unsigned char data[],
 674                       unsigned short len)
 675 {
 676         int i, rv, tmp_ret;
 677         bool drop_data = false;
 678
 679         if (!len) {
 680                 /* Reads of zero length not supported in auto mode. */
 681                 debug("%s: zero length read adjusted\n", __func__);
 682                 drop_data = true;
 683                 len = 1;
 684         }
 685
 686         if (alen) {
 687                 /* Internal register adress needs to be written first. */
 688                 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
 689                 if (rv != I2C_OK)
 690                         return rv;
 691         }
 692
 693         rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
 694
 695         if (rv != I2C_OK)
 696                 return rv;
 697
 698         for (i = 0; i < len; i++) {
 699                 rv = hsi2c_poll_fifo(i2c, true);
 700                 if (rv != I2C_OK)
 701                         goto read_err;
 702                 if (drop_data)
 703                         continue;
 704                 data[i] = readl(&i2c->usi_rxdata);
 705         }
 706
 707         rv = hsi2c_wait_for_trx(i2c);
 708
 709  read_err:
 710         tmp_ret = hsi2c_wait_while_busy(i2c);
 711         if (rv == I2C_OK)
 712                 rv = tmp_ret;
 713
 714         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 715         return rv;
 716 }
 717
 718 #ifdef CONFIG_SYS_I2C
 719 static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
 720                                               unsigned int speed)
 721 #else
 722 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 723 #endif
 724 {
 725         struct s3c24x0_i2c_bus *i2c_bus;
 726
 727 #ifdef CONFIG_SYS_I2C
 728         i2c_bus = get_bus(adap->hwadapnr);
 729         if (!i2c_bus)
 730                 return -EFAULT;
 731 #else
 732         i2c_bus = dev_get_priv(dev);
 733 #endif
 734         i2c_bus->clock_frequency = speed;
 735
 736         if (i2c_bus->is_highspeed) {
 737                 if (hsi2c_get_clk_details(i2c_bus))
 738                         return -EFAULT;
 739                 hsi2c_ch_init(i2c_bus);
 740         } else {
 741                 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
 742                             CONFIG_SYS_I2C_S3C24X0_SLAVE);
 743         }
 744
 745         return 0;
 746 }
 747
 748 /*
 749  * cmd_type is 0 for write, 1 for read.
 750  *
 751  * addr_len can take any value from 0-255, it is only limited
 752  * by the char, we could make it larger if needed. If it is
 753  * 0 we skip the address write cycle.
 754  */
 755 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 756                         unsigned char cmd_type,
 757                         unsigned char chip,
 758                         unsigned char addr[],
 759                         unsigned char addr_len,
 760                         unsigned char data[],
 761                         unsigned short data_len)
 762 {
 763         int i = 0, result;
 764         ulong start_time = get_timer(0);
 765
 766         if (data == 0 || data_len == 0) {
 767                 /*Don't support data transfer of no length or to address 0 */
 768                 debug("i2c_transfer: bad call\n");
 769                 return I2C_NOK;
 770         }
 771
 772         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
 773                 if (get_timer(start_time) > I2C_TIMEOUT_MS)
 774                         return I2C_NOK_TOUT;
 775         }
 776
 777         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 778
 779         /* Get the slave chip address going */
 780         writel(chip, &i2c->iicds);
 781         if ((cmd_type == I2C_WRITE) || (addr && addr_len))
 782                 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 783                        &i2c->iicstat);
 784         else
 785                 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 786                        &i2c->iicstat);
 787
 788         /* Wait for chip address to transmit. */
 789         result = WaitForXfer(i2c);
 790         if (result != I2C_OK)
 791                 goto bailout;
 792
 793         /* If register address needs to be transmitted - do it now. */
 794         if (addr && addr_len) {
 795                 while ((i < addr_len) && (result == I2C_OK)) {
 796                         writel(addr[i++], &i2c->iicds);
 797                         ReadWriteByte(i2c);
 798                         result = WaitForXfer(i2c);
 799                 }
 800                 i = 0;
 801                 if (result != I2C_OK)
 802                         goto bailout;
 803         }
 804
 805         switch (cmd_type) {
 806         case I2C_WRITE:
 807                 while ((i < data_len) && (result == I2C_OK)) {
 808                         writel(data[i++], &i2c->iicds);
 809                         ReadWriteByte(i2c);
 810                         result = WaitForXfer(i2c);
 811                 }
 812                 break;
 813
 814         case I2C_READ:
 815                 if (addr && addr_len) {
 816                         /*
 817                          * Register address has been sent, now send slave chip
 818                          * address again to start the actual read transaction.
 819                          */
 820                         writel(chip, &i2c->iicds);
 821
 822                         /* Generate a re-START. */
 823                         writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 824                                 &i2c->iicstat);
 825                         ReadWriteByte(i2c);
 826                         result = WaitForXfer(i2c);
 827
 828                         if (result != I2C_OK)
 829                                 goto bailout;
 830                 }
 831
 832                 while ((i < data_len) && (result == I2C_OK)) {
 833                         /* disable ACK for final READ */
 834                         if (i == data_len - 1)
 835                                 writel(readl(&i2c->iiccon)
 836                                        & ~I2CCON_ACKGEN,
 837                                        &i2c->iiccon);
 838                         ReadWriteByte(i2c);
 839                         result = WaitForXfer(i2c);
 840                         data[i++] = readl(&i2c->iicds);
 841                 }
 842                 if (result == I2C_NACK)
 843                         result = I2C_OK; /* Normal terminated read. */
 844                 break;
 845
 846         default:
 847                 debug("i2c_transfer: bad call\n");
 848                 result = I2C_NOK;
 849                 break;
 850         }
 851
 852 bailout:
 853         /* Send STOP. */
 854         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 855         ReadWriteByte(i2c);
 856
 857         return result;
 858 }
 859
 860 #ifdef CONFIG_SYS_I2C
 861 static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
 862 #else
 863 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
 864 #endif
 865 {
 866         struct s3c24x0_i2c_bus *i2c_bus;
 867         uchar buf[1];
 868         int ret;
 869
 870 #ifdef CONFIG_SYS_I2C
 871         i2c_bus = get_bus(adap->hwadapnr);
 872         if (!i2c_bus)
 873                 return -EFAULT;
 874 #else
 875         i2c_bus = dev_get_priv(dev);
 876 #endif
 877         buf[0] = 0;
 878
 879         /*
 880          * What is needed is to send the chip address and verify that the
 881          * address was <ACK>ed (i.e. there was a chip at that address which
 882          * drove the data line low).
 883          */
 884         if (i2c_bus->is_highspeed) {
 885                 ret = hsi2c_read(i2c_bus->hsregs,
 886                                 chip, 0, 0, buf, 1);
 887         } else {
 888                 ret = i2c_transfer(i2c_bus->regs,
 889                                 I2C_READ, chip << 1, 0, 0, buf, 1);
 890         }
 891
 892         return ret != I2C_OK;
 893 }
 894
 895 #ifdef CONFIG_SYS_I2C
 896 static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 897                             int alen, uchar *buffer, int len)
 898 {
 899         struct s3c24x0_i2c_bus *i2c_bus;
 900         uchar xaddr[4];
 901         int ret;
 902
 903         i2c_bus = get_bus(adap->hwadapnr);
 904         if (!i2c_bus)
 905                 return -EFAULT;
 906
 907         if (alen > 4) {
 908                 debug("I2C read: addr len %d not supported\n", alen);
 909                 return -EADDRNOTAVAIL;
 910         }
 911
 912         if (alen > 0) {
 913                 xaddr[0] = (addr >> 24) & 0xFF;
 914                 xaddr[1] = (addr >> 16) & 0xFF;
 915                 xaddr[2] = (addr >> 8) & 0xFF;
 916                 xaddr[3] = addr & 0xFF;
 917         }
 918
 919 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 920         /*
 921          * EEPROM chips that implement "address overflow" are ones
 922          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 923          * address and the extra bits end up in the "chip address"
 924          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 925          * four 256 byte chips.
 926          *
 927          * Note that we consider the length of the address field to
 928          * still be one byte because the extra address bits are
 929          * hidden in the chip address.
 930          */
 931         if (alen > 0)
 932                 chip |= ((addr >> (alen * 8)) &
 933                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 934 #endif
 935         if (i2c_bus->is_highspeed)
 936                 ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
 937                                  alen, buffer, len);
 938         else
 939                 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1,
 940                                 &xaddr[4 - alen], alen, buffer, len);
 941
 942         if (ret) {
 943                 if (i2c_bus->is_highspeed)
 944                         exynos5_i2c_reset(i2c_bus);
 945                 debug("I2c read failed %d\n", ret);
 946                 return -EIO;
 947         }
 948         return 0;
 949 }
 950
 951 static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 952                          int alen, uchar *buffer, int len)
 953 {
 954         struct s3c24x0_i2c_bus *i2c_bus;
 955         uchar xaddr[4];
 956         int ret;
 957
 958         i2c_bus = get_bus(adap->hwadapnr);
 959         if (!i2c_bus)
 960                 return -EFAULT;
 961
 962         if (alen > 4) {
 963                 debug("I2C write: addr len %d not supported\n", alen);
 964                 return -EINVAL;
 965         }
 966
 967         if (alen > 0) {
 968                 xaddr[0] = (addr >> 24) & 0xFF;
 969                 xaddr[1] = (addr >> 16) & 0xFF;
 970                 xaddr[2] = (addr >> 8) & 0xFF;
 971                 xaddr[3] = addr & 0xFF;
 972         }
 973 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 974         /*
 975          * EEPROM chips that implement "address overflow" are ones
 976          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 977          * address and the extra bits end up in the "chip address"
 978          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 979          * four 256 byte chips.
 980          *
 981          * Note that we consider the length of the address field to
 982          * still be one byte because the extra address bits are
 983          * hidden in the chip address.
 984          */
 985         if (alen > 0)
 986                 chip |= ((addr >> (alen * 8)) &
 987                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 988 #endif
 989         if (i2c_bus->is_highspeed)
 990                 ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
 991                                   alen, buffer, len, true);
 992         else
 993                 ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1,
 994                                 &xaddr[4 - alen], alen, buffer, len);
 995
 996         if (ret != 0) {
 997                 if (i2c_bus->is_highspeed)
 998                         exynos5_i2c_reset(i2c_bus);
 999                 return 1;
1000         } else {
1001                 return 0;
1002         }
1003 }
1004
1005 #ifdef CONFIG_OF_CONTROL
1006 static void process_nodes(const void *blob, int node_list[], int count,
1007                          int is_highspeed)
1008 {
1009         struct s3c24x0_i2c_bus *bus;
1010         int i, flags;
1011
1012         for (i = 0; i < count; i++) {
1013                 int node = node_list[i];
1014
1015                 if (node <= 0)
1016                         continue;
1017
1018                 bus = &i2c_bus[i];
1019                 bus->active = true;
1020                 bus->is_highspeed = is_highspeed;
1021
1022                 if (is_highspeed) {
1023                         flags = PINMUX_FLAG_HS_MODE;
1024                         bus->hsregs = (struct exynos5_hsi2c *)
1025                                         fdtdec_get_addr(blob, node, "reg");
1026                 } else {
1027                         flags = 0;
1028                         bus->regs = (struct s3c24x0_i2c *)
1029                                         fdtdec_get_addr(blob, node, "reg");
1030                 }
1031
1032                 bus->id = pinmux_decode_periph_id(blob, node);
1033                 bus->clock_frequency = fdtdec_get_int(blob, node,
1034                                                 "clock-frequency",
1035                                                 CONFIG_SYS_I2C_S3C24X0_SPEED);
1036                 bus->node = node;
1037                 bus->bus_num = i;
1038                 exynos_pinmux_config(PERIPH_ID_I2C0 + bus->id, flags);
1039
1040                 /* Mark position as used */
1041                 node_list[i] = -1;
1042         }
1043 }
1044
1045 void board_i2c_init(const void *blob)
1046 {
1047         int node_list[CONFIG_MAX_I2C_NUM];
1048         int count;
1049
1050         /* First get the normal i2c ports */
1051         count = fdtdec_find_aliases_for_id(blob, "i2c",
1052                 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
1053                 CONFIG_MAX_I2C_NUM);
1054         process_nodes(blob, node_list, count, 0);
1055
1056         /* Now look for high speed i2c ports */
1057         count = fdtdec_find_aliases_for_id(blob, "i2c",
1058                 COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
1059                 CONFIG_MAX_I2C_NUM);
1060         process_nodes(blob, node_list, count, 1);
1061 }
1062
1063 int i2c_get_bus_num_fdt(int node)
1064 {
1065         int i;
1066
1067         for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
1068                 if (node == i2c_bus[i].node)
1069                         return i;
1070         }
1071
1072         debug("%s: Can't find any matched I2C bus\n", __func__);
1073         return -EINVAL;
1074 }
1075
1076 int i2c_reset_port_fdt(const void *blob, int node)
1077 {
1078         struct s3c24x0_i2c_bus *i2c_bus;
1079         int bus;
1080
1081         bus = i2c_get_bus_num_fdt(node);
1082         if (bus < 0) {
1083                 debug("could not get bus for node %d\n", node);
1084                 return bus;
1085         }
1086
1087         i2c_bus = get_bus(bus);
1088         if (!i2c_bus) {
1089                 debug("get_bus() failed for node %d\n", node);
1090                 return -EFAULT;
1091         }
1092
1093         if (i2c_bus->is_highspeed) {
1094                 if (hsi2c_get_clk_details(i2c_bus))
1095                         return -EINVAL;
1096                 hsi2c_ch_init(i2c_bus);
1097         } else {
1098                 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
1099                             CONFIG_SYS_I2C_S3C24X0_SLAVE);
1100         }
1101
1102         return 0;
1103 }
1104 #endif /* CONFIG_OF_CONTROL */
1105
1106 #ifdef CONFIG_EXYNOS5
1107 static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
1108 {
1109         /* This will override the speed selected in the fdt for that port */
1110         debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
1111         if (i2c_set_bus_speed(speed))
1112                 error("i2c_init: failed to init bus for speed = %d", speed);
1113 }
1114 #endif /* CONFIG_EXYNOS5 */
1115
1116 /*
1117  * Register s3c24x0 i2c adapters
1118  */
1119 #if defined(CONFIG_EXYNOS5420)
1120 U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1121                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1122                         s3c24x0_i2c_set_bus_speed,
1123                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1124                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
1125 U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1126                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1127                         s3c24x0_i2c_set_bus_speed,
1128                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1129                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
1130 U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1131                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1132                         s3c24x0_i2c_set_bus_speed,
1133                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1134                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
1135 U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
1136                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1137                         s3c24x0_i2c_set_bus_speed,
1138                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1139                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
1140 U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
1141                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1142                         s3c24x0_i2c_set_bus_speed,
1143                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1144                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
1145 U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
1146                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1147                         s3c24x0_i2c_set_bus_speed,
1148                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1149                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
1150 U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
1151                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1152                         s3c24x0_i2c_set_bus_speed,
1153                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1154                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
1155 U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
1156                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1157                         s3c24x0_i2c_set_bus_speed,
1158                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1159                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
1160 U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
1161                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1162                         s3c24x0_i2c_set_bus_speed,
1163                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1164                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
1165 U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
1166                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1167                         s3c24x0_i2c_set_bus_speed,
1168                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1169                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
1170 U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
1171                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1172                         s3c24x0_i2c_set_bus_speed,
1173                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1174                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
1175 #elif defined(CONFIG_EXYNOS5250)
1176 U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
1177                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1178                         s3c24x0_i2c_set_bus_speed,
1179                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1180                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
1181 U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
1182                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1183                         s3c24x0_i2c_set_bus_speed,
1184                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1185                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
1186 U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
1187                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1188                         s3c24x0_i2c_set_bus_speed,
1189                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1190                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
1191 U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
1192                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1193                         s3c24x0_i2c_set_bus_speed,
1194                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1195                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
1196 U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1197                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1198                         s3c24x0_i2c_set_bus_speed,
1199                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1200                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
1201 U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1202                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1203                         s3c24x0_i2c_set_bus_speed,
1204                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1205                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
1206 U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1207                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1208                         s3c24x0_i2c_set_bus_speed,
1209                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1210                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
1211 U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1212                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1213                         s3c24x0_i2c_set_bus_speed,
1214                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1215                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
1216 U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1217                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1218                         s3c24x0_i2c_set_bus_speed,
1219                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1220                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
1221 U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1222                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1223                         s3c24x0_i2c_set_bus_speed,
1224                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1225                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
1226 U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1227                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1228                         s3c24x0_i2c_set_bus_speed,
1229                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1230                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
1231 #elif defined(CONFIG_EXYNOS4)
1232 U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1233                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1234                         s3c24x0_i2c_set_bus_speed,
1235                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1236                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
1237 U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1238                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1239                         s3c24x0_i2c_set_bus_speed,
1240                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1241                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
1242 U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1243                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1244                         s3c24x0_i2c_set_bus_speed,
1245                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1246                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
1247 U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1248                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1249                         s3c24x0_i2c_set_bus_speed,
1250                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1251                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
1252 U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1253                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1254                         s3c24x0_i2c_set_bus_speed,
1255                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1256                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
1257 U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1258                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1259                         s3c24x0_i2c_set_bus_speed,
1260                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1261                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
1262 U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1263                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1264                         s3c24x0_i2c_set_bus_speed,
1265                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1266                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
1267 U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1268                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1269                         s3c24x0_i2c_set_bus_speed,
1270                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1271                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
1272 U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1273                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1274                         s3c24x0_i2c_set_bus_speed,
1275                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1276                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
1277 #else
1278 U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1279                         s3c24x0_i2c_read, s3c24x0_i2c_write,
1280                         s3c24x0_i2c_set_bus_speed,
1281                         CONFIG_SYS_I2C_S3C24X0_SPEED,
1282                         CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
1283 #endif
1284 #endif /* CONFIG_SYS_I2C */
1285
1286 #ifdef CONFIG_DM_I2C
1287 static int i2c_write_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip,
1288                           uchar *buffer, int len, bool end_with_repeated_start)
1289 {
1290         int ret;
1291
1292         if (i2c_bus->is_highspeed) {
1293                 ret = hsi2c_write(i2c_bus->hsregs, chip, 0, 0,
1294                                   buffer, len, true);
1295                 if (ret)
1296                         exynos5_i2c_reset(i2c_bus);
1297         } else {
1298                 ret = i2c_transfer(i2c_bus->regs, I2C_WRITE,
1299                                    chip << 1, 0, 0, buffer, len);
1300         }
1301
1302         return ret != I2C_OK;
1303 }
1304
1305 static int i2c_read_data(struct s3c24x0_i2c_bus  *i2c_bus, uchar chip,
1306                          uchar *buffer, int len)
1307 {
1308         int ret;
1309
1310         if (i2c_bus->is_highspeed) {
1311                 ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buffer, len);
1312                 if (ret)
1313                         exynos5_i2c_reset(i2c_bus);
1314         } else {
1315                 ret = i2c_transfer(i2c_bus->regs, I2C_READ,
1316                                    chip << 1, 0, 0, buffer, len);
1317         }
1318
1319         return ret != I2C_OK;
1320 }
1321
1322 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
1323                             int nmsgs)
1324 {
1325         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
1326         int ret;
1327
1328         for (; nmsgs > 0; nmsgs--, msg++) {
1329                 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
1330
1331                 if (msg->flags & I2C_M_RD) {
1332                         ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1333                                             msg->len);
1334                 } else {
1335                         ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1336                                              msg->len, next_is_read);
1337                 }
1338                 if (ret)
1339                         return -EREMOTEIO;
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
1346 {
1347         const void *blob = gd->fdt_blob;
1348         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
1349         int node, flags;
1350
1351         i2c_bus->is_highspeed = dev_get_driver_data(dev);
1352         node = dev->of_offset;
1353
1354         if (i2c_bus->is_highspeed) {
1355                 flags = PINMUX_FLAG_HS_MODE;
1356                 i2c_bus->hsregs = (struct exynos5_hsi2c *)
1357                                 fdtdec_get_addr(blob, node, "reg");
1358         } else {
1359                 flags = 0;
1360                 i2c_bus->regs = (struct s3c24x0_i2c *)
1361                                 fdtdec_get_addr(blob, node, "reg");
1362         }
1363
1364         i2c_bus->id = pinmux_decode_periph_id(blob, node);
1365
1366         i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
1367                                                 "clock-frequency",
1368                                                 CONFIG_SYS_I2C_S3C24X0_SPEED);
1369         i2c_bus->node = node;
1370         i2c_bus->bus_num = dev->seq;
1371
1372         exynos_pinmux_config(i2c_bus->id, flags);
1373
1374         i2c_bus->active = true;
1375
1376         return 0;
1377 }
1378
1379 static const struct dm_i2c_ops s3c_i2c_ops = {
1380         .xfer           = s3c24x0_i2c_xfer,
1381         .probe_chip     = s3c24x0_i2c_probe,
1382         .set_bus_speed  = s3c24x0_i2c_set_bus_speed,
1383 };
1384
1385 static const struct udevice_id s3c_i2c_ids[] = {
1386         { .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD },
1387         { .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
1388         { }
1389 };
1390
1391 U_BOOT_DRIVER(i2c_s3c) = {
1392         .name   = "i2c_s3c",
1393         .id     = UCLASS_I2C,
1394         .of_match = s3c_i2c_ids,
1395         .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
1396         .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
1397         .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
1398         .ops    = &s3c_i2c_ops,
1399 };
1400 #endif /* CONFIG_DM_I2C */