3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/pinmux.h>
20 #include <asm/arch/s3c24x0_cpu.h>
24 #include "s3c24x0_i2c.h"
26 #ifdef CONFIG_HARD_I2C
34 #define I2C_NOK_LA 3 /* Lost arbitration */
35 #define I2C_NOK_TOUT 4 /* time out */
37 #define I2CSTAT_BSY 0x20 /* Busy bit */
38 #define I2CSTAT_NACK 0x01 /* Nack bit */
39 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
40 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
41 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
42 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
43 #define I2C_START_STOP 0x20 /* START / STOP */
44 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
46 #define I2C_TIMEOUT 1 /* 1 second */
50 * For SPL boot some boards need i2c before SDRAM is initialised so force
51 * variables to live in SRAM
53 static unsigned int g_current_bus __attribute__((section(".data")));
54 #ifdef CONFIG_OF_CONTROL
55 static int i2c_busses __attribute__((section(".data")));
56 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
57 __attribute__((section(".data")));
60 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
61 static int GetI2CSDA(void)
63 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
66 return (readl(&gpio->gpedat) & 0x8000) >> 15;
69 return (readl(&gpio->pgdat) & 0x0020) >> 5;
73 static void SetI2CSCL(int x)
75 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
78 writel((readl(&gpio->gpedat) & ~0x4000) |
79 (x & 1) << 14, &gpio->gpedat);
82 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
87 static int WaitForXfer(struct s3c24x0_i2c *i2c)
91 i = I2C_TIMEOUT * 10000;
92 while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
97 return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
100 static int IsACK(struct s3c24x0_i2c *i2c)
102 return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
105 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
107 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
110 static struct s3c24x0_i2c *get_base_i2c(void)
112 #ifdef CONFIG_EXYNOS4
113 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
114 + (EXYNOS4_I2C_SPACING
117 #elif defined CONFIG_EXYNOS5
118 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
119 + (EXYNOS5_I2C_SPACING
123 return s3c24x0_get_base_i2c();
127 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
129 ulong freq, pres = 16, div;
130 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
131 freq = get_i2c_clk();
135 /* calculate prescaler and divisor values */
136 if ((freq / pres / (16 + 1)) > speed)
137 /* set prescaler to 512 */
141 while ((freq / pres / (div + 1)) > speed)
144 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
145 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
147 /* init to SLAVE REVEIVE and set slaveaddr */
148 writel(0, &i2c->iicstat);
149 writel(slaveadd, &i2c->iicadd);
150 /* program Master Transmit (and implicit STOP) */
151 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
155 * MULTI BUS I2C support
158 #ifdef CONFIG_I2C_MULTI_BUS
159 int i2c_set_bus_num(unsigned int bus)
161 struct s3c24x0_i2c *i2c;
163 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
164 debug("Bad bus: %d\n", bus);
169 i2c = get_base_i2c();
170 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
175 unsigned int i2c_get_bus_num(void)
177 return g_current_bus;
181 void i2c_init(int speed, int slaveadd)
183 struct s3c24x0_i2c *i2c;
184 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
185 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
189 /* By default i2c channel 0 is the current bus */
191 i2c = get_base_i2c();
193 /* wait for some time to give previous transfer a chance to finish */
194 i = I2C_TIMEOUT * 1000;
195 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
200 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
201 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
202 #ifdef CONFIG_S3C2410
203 ulong old_gpecon = readl(&gpio->gpecon);
205 #ifdef CONFIG_S3C2400
206 ulong old_gpecon = readl(&gpio->pgcon);
208 /* bus still busy probably by (most) previously interrupted
211 #ifdef CONFIG_S3C2410
212 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
213 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
216 #ifdef CONFIG_S3C2400
217 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
218 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
222 /* toggle I2CSCL until bus idle */
226 while ((i > 0) && (GetI2CSDA() != 1)) {
236 /* restore pin functions */
237 #ifdef CONFIG_S3C2410
238 writel(old_gpecon, &gpio->gpecon);
240 #ifdef CONFIG_S3C2400
241 writel(old_gpecon, &gpio->pgcon);
244 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
245 i2c_ch_init(i2c, speed, slaveadd);
249 * cmd_type is 0 for write, 1 for read.
251 * addr_len can take any value from 0-255, it is only limited
252 * by the char, we could make it larger if needed. If it is
253 * 0 we skip the address write cycle.
255 static int i2c_transfer(struct s3c24x0_i2c *i2c,
256 unsigned char cmd_type,
258 unsigned char addr[],
259 unsigned char addr_len,
260 unsigned char data[],
261 unsigned short data_len)
265 if (data == 0 || data_len == 0) {
266 /*Don't support data transfer of no length or to address 0 */
267 debug("i2c_transfer: bad call\n");
271 /* Check I2C bus idle */
272 i = I2C_TIMEOUT * 1000;
273 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
278 if (readl(&i2c->iicstat) & I2CSTAT_BSY)
281 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
286 if (addr && addr_len) {
287 writel(chip, &i2c->iicds);
289 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
292 while ((i < addr_len) && (result == I2C_OK)) {
293 result = WaitForXfer(i2c);
294 writel(addr[i], &i2c->iicds);
299 while ((i < data_len) && (result == I2C_OK)) {
300 result = WaitForXfer(i2c);
301 writel(data[i], &i2c->iicds);
306 writel(chip, &i2c->iicds);
308 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
311 while ((i < data_len) && (result == I2C_OK)) {
312 result = WaitForXfer(i2c);
313 writel(data[i], &i2c->iicds);
319 if (result == I2C_OK)
320 result = WaitForXfer(i2c);
323 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
328 if (addr && addr_len) {
329 writel(chip, &i2c->iicds);
331 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
333 result = WaitForXfer(i2c);
336 while ((i < addr_len) && (result == I2C_OK)) {
337 writel(addr[i], &i2c->iicds);
339 result = WaitForXfer(i2c);
343 writel(chip, &i2c->iicds);
345 writel(I2C_MODE_MR | I2C_TXRX_ENA |
346 I2C_START_STOP, &i2c->iicstat);
348 result = WaitForXfer(i2c);
350 while ((i < data_len) && (result == I2C_OK)) {
351 /* disable ACK for final READ */
352 if (i == data_len - 1)
353 writel(readl(&i2c->iiccon)
357 result = WaitForXfer(i2c);
358 data[i] = readl(&i2c->iicds);
366 writel(chip, &i2c->iicds);
368 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
370 result = WaitForXfer(i2c);
374 while ((i < data_len) && (result == I2C_OK)) {
375 /* disable ACK for final READ */
376 if (i == data_len - 1)
377 writel(readl(&i2c->iiccon) &
381 result = WaitForXfer(i2c);
382 data[i] = readl(&i2c->iicds);
391 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
396 debug("i2c_transfer: bad call\n");
404 int i2c_probe(uchar chip)
406 struct s3c24x0_i2c *i2c;
409 i2c = get_base_i2c();
413 * What is needed is to send the chip address and verify that the
414 * address was <ACK>ed (i.e. there was a chip at that address which
415 * drove the data line low).
417 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
420 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
422 struct s3c24x0_i2c *i2c;
427 debug("I2C read: addr len %d not supported\n", alen);
432 xaddr[0] = (addr >> 24) & 0xFF;
433 xaddr[1] = (addr >> 16) & 0xFF;
434 xaddr[2] = (addr >> 8) & 0xFF;
435 xaddr[3] = addr & 0xFF;
438 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
440 * EEPROM chips that implement "address overflow" are ones
441 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
442 * address and the extra bits end up in the "chip address"
443 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
444 * four 256 byte chips.
446 * Note that we consider the length of the address field to
447 * still be one byte because the extra address bits are
448 * hidden in the chip address.
451 chip |= ((addr >> (alen * 8)) &
452 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
454 i2c = get_base_i2c();
455 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
458 debug("I2c read: failed %d\n", ret);
464 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
466 struct s3c24x0_i2c *i2c;
470 debug("I2C write: addr len %d not supported\n", alen);
475 xaddr[0] = (addr >> 24) & 0xFF;
476 xaddr[1] = (addr >> 16) & 0xFF;
477 xaddr[2] = (addr >> 8) & 0xFF;
478 xaddr[3] = addr & 0xFF;
480 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
482 * EEPROM chips that implement "address overflow" are ones
483 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
484 * address and the extra bits end up in the "chip address"
485 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
486 * four 256 byte chips.
488 * Note that we consider the length of the address field to
489 * still be one byte because the extra address bits are
490 * hidden in the chip address.
493 chip |= ((addr >> (alen * 8)) &
494 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
496 i2c = get_base_i2c();
498 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
502 #ifdef CONFIG_OF_CONTROL
503 void board_i2c_init(const void *blob)
506 int node_list[CONFIG_MAX_I2C_NUM];
509 count = fdtdec_find_aliases_for_id(blob, "i2c",
510 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
513 for (i = 0; i < count; i++) {
514 struct s3c24x0_i2c_bus *bus;
515 int node = node_list[i];
520 bus->regs = (struct s3c24x0_i2c *)
521 fdtdec_get_addr(blob, node, "reg");
522 bus->id = pinmux_decode_periph_id(blob, node);
524 bus->bus_num = i2c_busses++;
525 exynos_pinmux_config(bus->id, 0);
529 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
531 if (bus_idx < i2c_busses)
532 return &i2c_bus[bus_idx];
534 debug("Undefined bus: %d\n", bus_idx);
538 int i2c_get_bus_num_fdt(int node)
542 for (i = 0; i < i2c_busses; i++) {
543 if (node == i2c_bus[i].node)
547 debug("%s: Can't find any matched I2C bus\n", __func__);
551 int i2c_reset_port_fdt(const void *blob, int node)
553 struct s3c24x0_i2c_bus *i2c;
556 bus = i2c_get_bus_num_fdt(node);
558 debug("could not get bus for node %d\n", node);
564 debug("get_bus() failed for node node %d\n", node);
568 i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
574 #endif /* CONFIG_HARD_I2C */