2 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
3 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * NOTE: This driver should be converted to driver model before June 2017.
8 * Please see doc/driver-model/i2c-howto.txt for instructions.
15 DECLARE_GLOBAL_DATA_PTR;
17 /* Every register is 32bit aligned, but only 8bits in size */
18 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
30 #define SH_I2C_ICCR_ICE (1 << 7)
31 #define SH_I2C_ICCR_RACK (1 << 6)
32 #define SH_I2C_ICCR_RTS (1 << 4)
33 #define SH_I2C_ICCR_BUSY (1 << 2)
34 #define SH_I2C_ICCR_SCP (1 << 0)
37 #define SH_IC_BUSY (1 << 4)
38 #define SH_IC_TACK (1 << 2)
39 #define SH_IC_WAIT (1 << 1)
40 #define SH_IC_DTE (1 << 0)
42 #ifdef CONFIG_SH_I2C_8BIT
43 /* store 8th bit of iccl and icch in ICIC register */
44 #define SH_I2C_ICIC_ICCLB8 (1 << 7)
45 #define SH_I2C_ICIC_ICCHB8 (1 << 6)
48 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
49 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
50 #ifdef CONFIG_SYS_I2C_SH_BASE1
51 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
53 #ifdef CONFIG_SYS_I2C_SH_BASE2
54 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
56 #ifdef CONFIG_SYS_I2C_SH_BASE3
57 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
59 #ifdef CONFIG_SYS_I2C_SH_BASE4
60 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
64 static u16 iccl, icch;
68 static void sh_irq_dte(struct sh_i2c *dev)
72 for (i = 0; i < IRQ_WAIT; i++) {
73 if (SH_IC_DTE & readb(&dev->icsr))
79 static int sh_irq_dte_with_tack(struct sh_i2c *dev)
83 for (i = 0; i < IRQ_WAIT; i++) {
84 if (SH_IC_DTE & readb(&dev->icsr))
86 if (SH_IC_TACK & readb(&dev->icsr))
93 static void sh_irq_busy(struct sh_i2c *dev)
97 for (i = 0; i < IRQ_WAIT; i++) {
98 if (!(SH_IC_BUSY & readb(&dev->icsr)))
104 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
106 u8 icic = SH_IC_TACK;
108 debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
109 __func__, chip, addr, iccl, icch);
110 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
111 setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
113 writeb(iccl & 0xff, &dev->iccl);
114 writeb(icch & 0xff, &dev->icch);
115 #ifdef CONFIG_SH_I2C_8BIT
117 icic |= SH_I2C_ICIC_ICCLB8;
119 icic |= SH_I2C_ICIC_ICCHB8;
121 writeb(icic, &dev->icic);
123 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
126 clrbits_8(&dev->icsr, SH_IC_TACK);
127 writeb(chip << 1, &dev->icdr);
128 if (sh_irq_dte_with_tack(dev) != 0)
131 writeb(addr, &dev->icdr);
133 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
135 if (sh_irq_dte_with_tack(dev) != 0)
140 static void sh_i2c_finish(struct sh_i2c *dev)
142 writeb(0, &dev->icsr);
143 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
147 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
150 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
154 writeb(val, &dev->icdr);
155 if (sh_irq_dte_with_tack(dev) != 0)
158 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
159 if (sh_irq_dte_with_tack(dev) != 0)
169 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
173 #if defined(CONFIG_SH73A0)
174 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
177 if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
182 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
185 writeb(chip << 1 | 0x01, &dev->icdr);
186 if (sh_irq_dte_with_tack(dev) != 0)
189 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
190 if (sh_irq_dte_with_tack(dev) != 0)
193 ret = readb(&dev->icdr) & 0xff;
195 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
196 readb(&dev->icdr); /* Dummy read */
206 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
210 /* No i2c support prior to relocation */
211 if (!(gd->flags & GD_FLG_RELOC))
215 * Calculate the value for iccl. From the data sheet:
216 * iccl = (p-clock / transfer-rate) * (L / (L + H))
217 * where L and H are the SCL low and high ratio.
219 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
220 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
221 tmp = num * 10 / denom;
223 iccl = (u16)((num/denom) + 1);
225 iccl = (u16)(num/denom);
227 /* Calculate the value for icch. From the data sheet:
228 icch = (p clock / transfer rate) * (H / (L + H)) */
229 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
230 tmp = num * 10 / denom;
232 icch = (u16)((num/denom) + 1);
234 icch = (u16)(num/denom);
236 debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
237 CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
240 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
241 uint addr, int alen, u8 *data, int len)
244 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
246 for (i = 0; i < len; i++) {
247 ret = sh_i2c_raw_read(dev, chip, addr + i);
251 data[i] = ret & 0xff;
252 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
258 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
259 int alen, u8 *data, int len)
261 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
264 for (i = 0; i < len; i++) {
265 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
266 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
273 sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
277 return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
280 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
283 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
286 sh_i2c_init(adap, speed, 0);
292 * Register RCAR i2c adapters
294 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
295 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
296 #ifdef CONFIG_SYS_I2C_SH_BASE1
297 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
298 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
300 #ifdef CONFIG_SYS_I2C_SH_BASE2
301 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
302 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
304 #ifdef CONFIG_SYS_I2C_SH_BASE3
305 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
306 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
308 #ifdef CONFIG_SYS_I2C_SH_BASE4
309 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
310 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)