2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* Every register is 32bit aligned, but only 8bits in size */
25 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
36 static struct sh_i2c *base;
39 #define SH_I2C_ICCR_ICE (1 << 7)
40 #define SH_I2C_ICCR_RACK (1 << 6)
41 #define SH_I2C_ICCR_RTS (1 << 4)
42 #define SH_I2C_ICCR_BUSY (1 << 2)
43 #define SH_I2C_ICCR_SCP (1 << 0)
46 #define SH_IC_BUSY (1 << 4)
47 #define SH_IC_TACK (1 << 2)
48 #define SH_IC_WAIT (1 << 1)
49 #define SH_IC_DTE (1 << 0)
51 #ifdef CONFIG_SH_I2C_8BIT
52 /* store 8th bit of iccl and icch in ICIC register */
53 #define SH_I2C_ICIC_ICCLB8 (1 << 7)
54 #define SH_I2C_ICIC_ICCHB8 (1 << 6)
57 static u16 iccl, icch;
61 static void irq_dte(struct sh_i2c *base)
65 for (i = 0 ; i < IRQ_WAIT ; i++) {
66 if (SH_IC_DTE & readb(&base->icsr))
72 static int irq_dte_with_tack(struct sh_i2c *base)
76 for (i = 0 ; i < IRQ_WAIT ; i++) {
77 if (SH_IC_DTE & readb(&base->icsr))
79 if (SH_IC_TACK & readb(&base->icsr))
86 static void irq_busy(struct sh_i2c *base)
90 for (i = 0 ; i < IRQ_WAIT ; i++) {
91 if (!(SH_IC_BUSY & readb(&base->icsr)))
97 static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
101 clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
102 setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
104 writeb(iccl & 0xff, &base->iccl);
105 writeb(icch & 0xff, &base->icch);
106 #ifdef CONFIG_SH_I2C_8BIT
108 icic |= SH_I2C_ICIC_ICCLB8;
110 icic |= SH_I2C_ICIC_ICCHB8;
112 writeb(icic, &base->icic);
114 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
117 clrbits_8(&base->icsr, SH_IC_TACK);
118 writeb(id << 1, &base->icdr);
119 if (irq_dte_with_tack(base) != 0)
122 writeb(reg, &base->icdr);
124 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
126 if (irq_dte_with_tack(base) != 0)
131 static void i2c_finish(struct sh_i2c *base)
133 writeb(0, &base->icsr);
134 clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
137 static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
140 if (i2c_set_addr(base, id, reg, 0) != 0)
144 writeb(val, &base->icdr);
145 if (irq_dte_with_tack(base) != 0)
148 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
149 if (irq_dte_with_tack(base) != 0)
158 static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
162 #if defined(CONFIG_SH73A0)
163 if (i2c_set_addr(base, id, reg, 0) != 0)
166 if (i2c_set_addr(base, id, reg, 1) != 0)
171 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
174 writeb(id << 1 | 0x01, &base->icdr);
175 if (irq_dte_with_tack(base) != 0)
178 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
179 if (irq_dte_with_tack(base) != 0)
182 ret = readb(&base->icdr) & 0xff;
184 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
185 readb(&base->icdr); /* Dummy read */
193 #ifdef CONFIG_I2C_MULTI_BUS
194 static unsigned int current_bus;
197 * i2c_set_bus_num - change active I2C bus
198 * @bus: bus index, zero based
199 * @returns: 0 on success, non-0 on failure
201 int i2c_set_bus_num(unsigned int bus)
203 if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
204 printf("Bad bus: %d\n", bus);
210 base = (void *)CONFIG_SH_I2C_BASE0;
213 base = (void *)CONFIG_SH_I2C_BASE1;
215 #ifdef CONFIG_SH_I2C_BASE2
217 base = (void *)CONFIG_SH_I2C_BASE2;
220 #ifdef CONFIG_SH_I2C_BASE3
222 base = (void *)CONFIG_SH_I2C_BASE3;
225 #ifdef CONFIG_SH_I2C_BASE4
227 base = (void *)CONFIG_SH_I2C_BASE4;
239 * i2c_get_bus_num - returns index of active I2C bus
241 unsigned int i2c_get_bus_num(void)
247 #define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
248 ((clk / rate) * (t_low / t_low + t_high))
249 #define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
250 ((clk / rate) * (t_high / t_low + t_high))
252 void i2c_init(int speed, int slaveaddr)
256 #ifdef CONFIG_I2C_MULTI_BUS
259 base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
262 * Calculate the value for iccl. From the data sheet:
263 * iccl = (p-clock / transfer-rate) * (L / (L + H))
264 * where L and H are the SCL low and high ratio.
266 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
267 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
268 tmp = num * 10 / denom;
270 iccl = (u16)((num/denom) + 1);
272 iccl = (u16)(num/denom);
274 /* Calculate the value for icch. From the data sheet:
275 icch = (p clock / transfer rate) * (H / (L + H)) */
276 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
277 tmp = num * 10 / denom;
279 icch = (u16)((num/denom) + 1);
281 icch = (u16)(num/denom);
285 * i2c_read: - Read multiple bytes from an i2c device
287 * The higher level routines take into account that this function is only
288 * called with len < page length of the device (see configuration file)
290 * @chip: address of the chip which is to be read
291 * @addr: i2c data address within the chip
292 * @alen: length of the i2c data address (1..2 bytes)
293 * @buffer: where to write the data
294 * @len: how much byte do we want to read
295 * @return: 0 in case of success
297 int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
301 for (i = 0 ; i < len ; i++) {
302 ret = i2c_raw_read(base, chip, addr + i);
305 buffer[i] = ret & 0xff;
311 * i2c_write: - Write multiple bytes to an i2c device
313 * The higher level routines take into account that this function is only
314 * called with len < page length of the device (see configuration file)
316 * @chip: address of the chip which is to be written
317 * @addr: i2c data address within the chip
318 * @alen: length of the i2c data address (1..2 bytes)
319 * @buffer: where to find the data to be written
320 * @len: how much byte do we want to read
321 * @return: 0 in case of success
323 int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
326 for (i = 0; i < len ; i++)
327 if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
333 * i2c_probe: - Test if a chip answers for a given i2c address
335 * @chip: address of the chip which is searched for
336 * @return: 0 if a chip was found, -1 otherwhise
338 int i2c_probe(u8 chip)
342 ret = i2c_set_addr(base, chip, 0, 1);