2 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
3 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 DECLARE_GLOBAL_DATA_PTR;
14 /* Every register is 32bit aligned, but only 8bits in size */
15 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
27 #define SH_I2C_ICCR_ICE (1 << 7)
28 #define SH_I2C_ICCR_RACK (1 << 6)
29 #define SH_I2C_ICCR_RTS (1 << 4)
30 #define SH_I2C_ICCR_BUSY (1 << 2)
31 #define SH_I2C_ICCR_SCP (1 << 0)
34 #define SH_IC_BUSY (1 << 4)
35 #define SH_IC_TACK (1 << 2)
36 #define SH_IC_WAIT (1 << 1)
37 #define SH_IC_DTE (1 << 0)
39 #ifdef CONFIG_SH_I2C_8BIT
40 /* store 8th bit of iccl and icch in ICIC register */
41 #define SH_I2C_ICIC_ICCLB8 (1 << 7)
42 #define SH_I2C_ICIC_ICCHB8 (1 << 6)
45 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
46 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
47 #ifdef CONFIG_SYS_I2C_SH_BASE1
48 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
50 #ifdef CONFIG_SYS_I2C_SH_BASE2
51 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
53 #ifdef CONFIG_SYS_I2C_SH_BASE3
54 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
56 #ifdef CONFIG_SYS_I2C_SH_BASE4
57 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
61 static u16 iccl, icch;
65 static void sh_irq_dte(struct sh_i2c *dev)
69 for (i = 0; i < IRQ_WAIT; i++) {
70 if (SH_IC_DTE & readb(&dev->icsr))
76 static int sh_irq_dte_with_tack(struct sh_i2c *dev)
80 for (i = 0; i < IRQ_WAIT; i++) {
81 if (SH_IC_DTE & readb(&dev->icsr))
83 if (SH_IC_TACK & readb(&dev->icsr))
90 static void sh_irq_busy(struct sh_i2c *dev)
94 for (i = 0; i < IRQ_WAIT; i++) {
95 if (!(SH_IC_BUSY & readb(&dev->icsr)))
101 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
103 u8 icic = SH_IC_TACK;
105 debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
106 __func__, chip, addr, iccl, icch);
107 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
108 setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
110 writeb(iccl & 0xff, &dev->iccl);
111 writeb(icch & 0xff, &dev->icch);
112 #ifdef CONFIG_SH_I2C_8BIT
114 icic |= SH_I2C_ICIC_ICCLB8;
116 icic |= SH_I2C_ICIC_ICCHB8;
118 writeb(icic, &dev->icic);
120 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
123 clrbits_8(&dev->icsr, SH_IC_TACK);
124 writeb(chip << 1, &dev->icdr);
125 if (sh_irq_dte_with_tack(dev) != 0)
128 writeb(addr, &dev->icdr);
130 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
132 if (sh_irq_dte_with_tack(dev) != 0)
137 static void sh_i2c_finish(struct sh_i2c *dev)
139 writeb(0, &dev->icsr);
140 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
144 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
147 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
151 writeb(val, &dev->icdr);
152 if (sh_irq_dte_with_tack(dev) != 0)
155 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
156 if (sh_irq_dte_with_tack(dev) != 0)
166 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
170 #if defined(CONFIG_SH73A0)
171 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
174 if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
179 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
182 writeb(chip << 1 | 0x01, &dev->icdr);
183 if (sh_irq_dte_with_tack(dev) != 0)
186 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
187 if (sh_irq_dte_with_tack(dev) != 0)
190 ret = readb(&dev->icdr) & 0xff;
192 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
193 readb(&dev->icdr); /* Dummy read */
203 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
207 /* No i2c support prior to relocation */
208 if (!(gd->flags & GD_FLG_RELOC))
212 * Calculate the value for iccl. From the data sheet:
213 * iccl = (p-clock / transfer-rate) * (L / (L + H))
214 * where L and H are the SCL low and high ratio.
216 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
217 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
218 tmp = num * 10 / denom;
220 iccl = (u16)((num/denom) + 1);
222 iccl = (u16)(num/denom);
224 /* Calculate the value for icch. From the data sheet:
225 icch = (p clock / transfer rate) * (H / (L + H)) */
226 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
227 tmp = num * 10 / denom;
229 icch = (u16)((num/denom) + 1);
231 icch = (u16)(num/denom);
233 debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
234 CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
237 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
238 uint addr, int alen, u8 *data, int len)
241 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
243 for (i = 0; i < len; i++) {
244 ret = sh_i2c_raw_read(dev, chip, addr + i);
248 data[i] = ret & 0xff;
249 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
255 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
256 int alen, u8 *data, int len)
258 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
261 for (i = 0; i < len; i++) {
262 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
263 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
270 sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
272 return sh_i2c_read(adap, dev, 0, 0, NULL, 0);
275 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
278 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
281 sh_i2c_init(adap, speed, 0);
287 * Register RCAR i2c adapters
289 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
290 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
291 #ifdef CONFIG_SYS_I2C_SH_BASE1
292 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
293 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
295 #ifdef CONFIG_SYS_I2C_SH_BASE2
296 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
297 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
299 #ifdef CONFIG_SYS_I2C_SH_BASE3
300 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
301 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
303 #ifdef CONFIG_SYS_I2C_SH_BASE4
304 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
305 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)