git.sur5r.net Git - u-boot/blob - drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <reset.h>
  11
  12 #include <dm/device.h>
  13 #include <linux/io.h>
  14
  15 /* STM32 I2C registers */
  16 struct stm32_i2c_regs {
  17         u32 cr1;        /* I2C control register 1 */
  18         u32 cr2;        /* I2C control register 2 */
  19         u32 oar1;       /* I2C own address 1 register */
  20         u32 oar2;       /* I2C own address 2 register */
  21         u32 timingr;    /* I2C timing register */
  22         u32 timeoutr;   /* I2C timeout register */
  23         u32 isr;        /* I2C interrupt and status register */
  24         u32 icr;        /* I2C interrupt clear register */
  25         u32 pecr;       /* I2C packet error checking register */
  26         u32 rxdr;       /* I2C receive data register */
  27         u32 txdr;       /* I2C transmit data register */
  28 };
  29
  30 #define STM32_I2C_CR1                           0x00
  31 #define STM32_I2C_CR2                           0x04
  32 #define STM32_I2C_TIMINGR                       0x10
  33 #define STM32_I2C_ISR                           0x18
  34 #define STM32_I2C_ICR                           0x1C
  35 #define STM32_I2C_RXDR                          0x24
  36 #define STM32_I2C_TXDR                          0x28
  37
  38 /* STM32 I2C control 1 */
  39 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  40 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  41 #define STM32_I2C_CR1_TCIE                      BIT(6)
  42 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  43 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  44 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  45 #define STM32_I2C_CR1_RXIE                      BIT(2)
  46 #define STM32_I2C_CR1_TXIE                      BIT(1)
  47 #define STM32_I2C_CR1_PE                        BIT(0)
  48
  49 /* STM32 I2C control 2 */
  50 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  51 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  52 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  53 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  54 #define STM32_I2C_CR2_NACK                      BIT(15)
  55 #define STM32_I2C_CR2_STOP                      BIT(14)
  56 #define STM32_I2C_CR2_START                     BIT(13)
  57 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  58 #define STM32_I2C_CR2_ADD10                     BIT(11)
  59 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  60 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  61 #define STM32_I2C_CR2_SADD10(n)                 ((n & STM32_I2C_CR2_SADD10_MASK))
  62 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  63 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  64 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  65                                                 | STM32_I2C_CR2_NBYTES_MASK \
  66                                                 | STM32_I2C_CR2_SADD7_MASK \
  67                                                 | STM32_I2C_CR2_RELOAD \
  68                                                 | STM32_I2C_CR2_RD_WRN)
  69
  70 /* STM32 I2C Interrupt Status */
  71 #define STM32_I2C_ISR_BUSY                      BIT(15)
  72 #define STM32_I2C_ISR_ARLO                      BIT(9)
  73 #define STM32_I2C_ISR_BERR                      BIT(8)
  74 #define STM32_I2C_ISR_TCR                       BIT(7)
  75 #define STM32_I2C_ISR_TC                        BIT(6)
  76 #define STM32_I2C_ISR_STOPF                     BIT(5)
  77 #define STM32_I2C_ISR_NACKF                     BIT(4)
  78 #define STM32_I2C_ISR_ADDR                      BIT(3)
  79 #define STM32_I2C_ISR_RXNE                      BIT(2)
  80 #define STM32_I2C_ISR_TXIS                      BIT(1)
  81 #define STM32_I2C_ISR_TXE                       BIT(0)
  82 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  83                                                 | STM32_I2C_ISR_ARLO)
  84
  85 /* STM32 I2C Interrupt Clear */
  86 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  87 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  88 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  89 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  90
  91 /* STM32 I2C Timing */
  92 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  93 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
  94 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
  95 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
  96 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
  97
  98 #define STM32_I2C_MAX_LEN                       0xff
  99
 100 #define STM32_I2C_DNF_DEFAULT                   0
 101 #define STM32_I2C_DNF_MAX                       16
 102
 103 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 104 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 105 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 106
 107 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 108 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 109
 110 #define STM32_PRESC_MAX                         BIT(4)
 111 #define STM32_SCLDEL_MAX                        BIT(4)
 112 #define STM32_SDADEL_MAX                        BIT(4)
 113 #define STM32_SCLH_MAX                          BIT(8)
 114 #define STM32_SCLL_MAX                          BIT(8)
 115
 116 #define STM32_NSEC_PER_SEC                      1000000000L
 117
 118 #define STANDARD_RATE                           100000
 119 #define FAST_RATE                               400000
 120 #define FAST_PLUS_RATE                          1000000
 121
 122 enum stm32_i2c_speed {
 123         STM32_I2C_SPEED_STANDARD, /* 100 kHz */
 124         STM32_I2C_SPEED_FAST, /* 400 kHz */
 125         STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
 126         STM32_I2C_SPEED_END,
 127 };
 128
 129 /**
 130  * struct stm32_i2c_spec - private i2c specification timing
 131  * @rate: I2C bus speed (Hz)
 132  * @rate_min: 80% of I2C bus speed (Hz)
 133  * @rate_max: 120% of I2C bus speed (Hz)
 134  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 135  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 136  * @hddat_min: Min data hold time (ns)
 137  * @vddat_max: Max data valid time (ns)
 138  * @sudat_min: Min data setup time (ns)
 139  * @l_min: Min low period of the SCL clock (ns)
 140  * @h_min: Min high period of the SCL clock (ns)
 141  */
 142
 143 struct stm32_i2c_spec {
 144         u32 rate;
 145         u32 rate_min;
 146         u32 rate_max;
 147         u32 fall_max;
 148         u32 rise_max;
 149         u32 hddat_min;
 150         u32 vddat_max;
 151         u32 sudat_min;
 152         u32 l_min;
 153         u32 h_min;
 154 };
 155
 156 /**
 157  * struct stm32_i2c_setup - private I2C timing setup parameters
 158  * @speed: I2C speed mode (standard, Fast Plus)
 159  * @speed_freq: I2C speed frequency  (Hz)
 160  * @clock_src: I2C clock source frequency (Hz)
 161  * @rise_time: Rise time (ns)
 162  * @fall_time: Fall time (ns)
 163  * @dnf: Digital filter coefficient (0-16)
 164  * @analog_filter: Analog filter delay (On/Off)
 165  */
 166 struct stm32_i2c_setup {
 167         enum stm32_i2c_speed speed;
 168         u32 speed_freq;
 169         u32 clock_src;
 170         u32 rise_time;
 171         u32 fall_time;
 172         u8 dnf;
 173         bool analog_filter;
 174 };
 175
 176 /**
 177  * struct stm32_i2c_timings - private I2C output parameters
 178  * @prec: Prescaler value
 179  * @scldel: Data setup time
 180  * @sdadel: Data hold time
 181  * @sclh: SCL high period (master mode)
 182  * @sclh: SCL low period (master mode)
 183  */
 184 struct stm32_i2c_timings {
 185         struct list_head node;
 186         u8 presc;
 187         u8 scldel;
 188         u8 sdadel;
 189         u8 sclh;
 190         u8 scll;
 191 };
 192
 193 struct stm32_i2c_priv {
 194         struct stm32_i2c_regs *regs;
 195         struct clk clk;
 196         struct stm32_i2c_setup *setup;
 197         int speed;
 198 };
 199
 200 static struct stm32_i2c_spec i2c_specs[] = {
 201         [STM32_I2C_SPEED_STANDARD] = {
 202                 .rate = STANDARD_RATE,
 203                 .rate_min = 8000,
 204                 .rate_max = 120000,
 205                 .fall_max = 300,
 206                 .rise_max = 1000,
 207                 .hddat_min = 0,
 208                 .vddat_max = 3450,
 209                 .sudat_min = 250,
 210                 .l_min = 4700,
 211                 .h_min = 4000,
 212         },
 213         [STM32_I2C_SPEED_FAST] = {
 214                 .rate = FAST_RATE,
 215                 .rate_min = 320000,
 216                 .rate_max = 480000,
 217                 .fall_max = 300,
 218                 .rise_max = 300,
 219                 .hddat_min = 0,
 220                 .vddat_max = 900,
 221                 .sudat_min = 100,
 222                 .l_min = 1300,
 223                 .h_min = 600,
 224         },
 225         [STM32_I2C_SPEED_FAST_PLUS] = {
 226                 .rate = FAST_PLUS_RATE,
 227                 .rate_min = 800000,
 228                 .rate_max = 1200000,
 229                 .fall_max = 100,
 230                 .rise_max = 120,
 231                 .hddat_min = 0,
 232                 .vddat_max = 450,
 233                 .sudat_min = 50,
 234                 .l_min = 500,
 235                 .h_min = 260,
 236         },
 237 };
 238
 239 static struct stm32_i2c_setup stm32f7_setup = {
 240         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 241         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 242         .dnf = STM32_I2C_DNF_DEFAULT,
 243         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 244 };
 245
 246 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 247 {
 248         struct stm32_i2c_regs *regs = i2c_priv->regs;
 249         u32 status = readl(&regs->isr);
 250
 251         if (status & STM32_I2C_ISR_BUSY)
 252                 return -EBUSY;
 253
 254         return 0;
 255 }
 256
 257 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 258                                       struct i2c_msg *msg, bool stop)
 259 {
 260         struct stm32_i2c_regs *regs = i2c_priv->regs;
 261         u32 cr2 = readl(&regs->cr2);
 262
 263         /* Set transfer direction */
 264         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 265         if (msg->flags & I2C_M_RD)
 266                 cr2 |= STM32_I2C_CR2_RD_WRN;
 267
 268         /* Set slave address */
 269         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 270         if (msg->flags & I2C_M_TEN) {
 271                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 272                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 273                 cr2 |= STM32_I2C_CR2_ADD10;
 274         } else {
 275                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 276                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 277         }
 278
 279         /* Set nb bytes to transfer and reload or autoend bits */
 280         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 281                  STM32_I2C_CR2_AUTOEND);
 282         if (msg->len > STM32_I2C_MAX_LEN) {
 283                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 284                 cr2 |= STM32_I2C_CR2_RELOAD;
 285         } else {
 286                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 287         }
 288
 289         /* Write configurations register */
 290         writel(cr2, &regs->cr2);
 291
 292         /* START/ReSTART generation */
 293         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 294 }
 295
 296 /*
 297  * RELOAD mode must be selected if total number of data bytes to be
 298  * sent is greater than MAX_LEN
 299  */
 300
 301 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 302                                       struct i2c_msg *msg, bool stop)
 303 {
 304         struct stm32_i2c_regs *regs = i2c_priv->regs;
 305         u32 cr2 = readl(&regs->cr2);
 306
 307         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 308
 309         if (msg->len > STM32_I2C_MAX_LEN) {
 310                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 311         } else {
 312                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 313                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 314         }
 315
 316         writel(cr2, &regs->cr2);
 317 }
 318
 319 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 320                                   u32 flags, u32 *status)
 321 {
 322         struct stm32_i2c_regs *regs = i2c_priv->regs;
 323         u32 time_start = get_timer(0);
 324
 325         *status = readl(&regs->isr);
 326         while (!(*status & flags)) {
 327                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 328                         debug("%s: i2c timeout\n", __func__);
 329                         return -ETIMEDOUT;
 330                 }
 331
 332                 *status = readl(&regs->isr);
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 339 {
 340         struct stm32_i2c_regs *regs = i2c_priv->regs;
 341         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 342                    STM32_I2C_ISR_STOPF;
 343         u32 status;
 344         int ret;
 345
 346         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 347         if (ret)
 348                 return ret;
 349
 350         if (status & STM32_I2C_ISR_BERR) {
 351                 debug("%s: Bus error\n", __func__);
 352
 353                 /* Clear BERR flag */
 354                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 355
 356                 return -EIO;
 357         }
 358
 359         if (status & STM32_I2C_ISR_ARLO) {
 360                 debug("%s: Arbitration lost\n", __func__);
 361
 362                 /* Clear ARLO flag */
 363                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 364
 365                 return -EAGAIN;
 366         }
 367
 368         if (status & STM32_I2C_ISR_NACKF) {
 369                 debug("%s: Receive NACK\n", __func__);
 370
 371                 /* Clear NACK flag */
 372                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 373
 374                 /* Wait until STOPF flag is set */
 375                 mask = STM32_I2C_ISR_STOPF;
 376                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 377                 if (ret)
 378                         return ret;
 379
 380                 ret = -EIO;
 381         }
 382
 383         if (status & STM32_I2C_ISR_STOPF) {
 384                 /* Clear STOP flag */
 385                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 386
 387                 /* Clear control register 2 */
 388                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 389         }
 390
 391         return ret;
 392 }
 393
 394 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 395                                     struct i2c_msg *msg, bool stop)
 396 {
 397         struct stm32_i2c_regs *regs = i2c_priv->regs;
 398         u32 status;
 399         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 400                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 401         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 402                           STM32_I2C_MAX_LEN : msg->len;
 403         int ret = 0;
 404
 405         /* Add errors */
 406         mask |= STM32_I2C_ISR_ERRORS;
 407
 408         stm32_i2c_message_start(i2c_priv, msg, stop);
 409
 410         while (msg->len) {
 411                 /*
 412                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 413                  * RXNE/BERR/ARLO flags are set
 414                  */
 415                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 416                 if (ret)
 417                         break;
 418
 419                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 420                         break;
 421
 422                 if (status & STM32_I2C_ISR_RXNE) {
 423                         *msg->buf++ = readb(&regs->rxdr);
 424                         msg->len--;
 425                         bytes_to_rw--;
 426                 }
 427
 428                 if (status & STM32_I2C_ISR_TXIS) {
 429                         writeb(*msg->buf++, &regs->txdr);
 430                         msg->len--;
 431                         bytes_to_rw--;
 432                 }
 433
 434                 if (!bytes_to_rw && msg->len) {
 435                         /* Wait until TCR flag is set */
 436                         mask = STM32_I2C_ISR_TCR;
 437                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 438                         if (ret)
 439                                 break;
 440
 441                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 442                                       STM32_I2C_MAX_LEN : msg->len;
 443                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 444                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 445
 446                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 447                 } else if (!bytes_to_rw) {
 448                         /* Wait until TC flag is set */
 449                         mask = STM32_I2C_ISR_TC;
 450                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 451                         if (ret)
 452                                 break;
 453
 454                         if (!stop)
 455                                 /* Message sent, new message has to be sent */
 456                                 return 0;
 457                 }
 458         }
 459
 460         /* End of transfer, send stop condition */
 461         mask = STM32_I2C_CR2_STOP;
 462         setbits_le32(&regs->cr2, mask);
 463
 464         return stm32_i2c_check_end_of_message(i2c_priv);
 465 }
 466
 467 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 468                             int nmsgs)
 469 {
 470         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 471         int ret;
 472
 473         ret = stm32_i2c_check_device_busy(i2c_priv);
 474         if (ret)
 475                 return ret;
 476
 477         for (; nmsgs > 0; nmsgs--, msg++) {
 478                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 479                 if (ret)
 480                         return ret;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 487                                        struct list_head *solutions)
 488 {
 489         struct stm32_i2c_timings *v;
 490         u32 p_prev = STM32_PRESC_MAX;
 491         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 492                                        setup->clock_src);
 493         u32 af_delay_min, af_delay_max;
 494         u16 p, l, a;
 495         int sdadel_min, sdadel_max, scldel_min;
 496         int ret = 0;
 497
 498         af_delay_min = setup->analog_filter ?
 499                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 500         af_delay_max = setup->analog_filter ?
 501                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 502
 503         sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
 504                      af_delay_min - (setup->dnf + 3) * i2cclk;
 505
 506         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 507                      af_delay_max - (setup->dnf + 4) * i2cclk;
 508
 509         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 510
 511         if (sdadel_min < 0)
 512                 sdadel_min = 0;
 513         if (sdadel_max < 0)
 514                 sdadel_max = 0;
 515
 516         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 517               sdadel_min, sdadel_max, scldel_min);
 518
 519         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 520         for (p = 0; p < STM32_PRESC_MAX; p++) {
 521                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 522                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 523
 524                         if (scldel < scldel_min)
 525                                 continue;
 526
 527                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 528                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 529
 530                                 if (((sdadel >= sdadel_min) &&
 531                                      (sdadel <= sdadel_max)) &&
 532                                     (p != p_prev)) {
 533                                         v = calloc(1, sizeof(*v));
 534                                         if (!v)
 535                                                 return -ENOMEM;
 536
 537                                         v->presc = p;
 538                                         v->scldel = l;
 539                                         v->sdadel = a;
 540                                         p_prev = p;
 541
 542                                         list_add_tail(&v->node, solutions);
 543                                 }
 544                         }
 545                 }
 546         }
 547
 548         if (list_empty(solutions)) {
 549                 pr_err("%s: no Prescaler solution\n", __func__);
 550                 ret = -EPERM;
 551         }
 552
 553         return ret;
 554 }
 555
 556 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 557                                      struct list_head *solutions,
 558                                      struct stm32_i2c_timings *s)
 559 {
 560         struct stm32_i2c_timings *v;
 561         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 562                                        setup->speed_freq);
 563         u32 clk_error_prev = i2cbus;
 564         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 565                                        setup->clock_src);
 566         u32 clk_min, clk_max;
 567         u32 af_delay_min;
 568         u32 dnf_delay;
 569         u32 tsync;
 570         u16 l, h;
 571         bool sol_found = false;
 572         int ret = 0;
 573
 574         af_delay_min = setup->analog_filter ?
 575                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 576         dnf_delay = setup->dnf * i2cclk;
 577
 578         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 579         clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 580         clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 581
 582         /*
 583          * Among Prescaler possibilities discovered above figures out SCL Low
 584          * and High Period. Provided:
 585          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 586          *   defined by I2C Specification. I2C Clock has to be lower than
 587          *   (SCL Low Period - Analog/Digital filters) / 4.
 588          * - SCL High Period has to be lower than High Period of the SCL Clock
 589          *   defined by I2C Specification
 590          * - I2C Clock has to be lower than SCL High Period
 591          */
 592         list_for_each_entry(v, solutions, node) {
 593                 u32 prescaler = (v->presc + 1) * i2cclk;
 594
 595                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 596                         u32 tscl_l = (l + 1) * prescaler + tsync;
 597                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 598                             (i2cclk >=
 599                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 600                                 continue;
 601                         }
 602
 603                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 604                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 605                                 u32 tscl = tscl_l + tscl_h +
 606                                            setup->rise_time + setup->fall_time;
 607
 608                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 609                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 610                                     (i2cclk < tscl_h)) {
 611                                         int clk_error = tscl - i2cbus;
 612
 613                                         if (clk_error < 0)
 614                                                 clk_error = -clk_error;
 615
 616                                         if (clk_error < clk_error_prev) {
 617                                                 clk_error_prev = clk_error;
 618                                                 v->scll = l;
 619                                                 v->sclh = h;
 620                                                 sol_found = true;
 621                                                 memcpy(s, v, sizeof(*s));
 622                                         }
 623                                 }
 624                         }
 625                 }
 626         }
 627
 628         if (!sol_found) {
 629                 pr_err("%s: no solution at all\n", __func__);
 630                 ret = -EPERM;
 631         }
 632
 633         return ret;
 634 }
 635
 636 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 637                                       struct stm32_i2c_setup *setup,
 638                                       struct stm32_i2c_timings *output)
 639 {
 640         struct stm32_i2c_timings *v, *_v;
 641         struct list_head solutions;
 642         int ret;
 643
 644         if (setup->speed >= STM32_I2C_SPEED_END) {
 645                 pr_err("%s: speed out of bound {%d/%d}\n", __func__,
 646                       setup->speed, STM32_I2C_SPEED_END - 1);
 647                 return -EINVAL;
 648         }
 649
 650         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 651             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 652                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 653                       __func__,
 654                       setup->rise_time, i2c_specs[setup->speed].rise_max,
 655                       setup->fall_time, i2c_specs[setup->speed].fall_max);
 656                 return -EINVAL;
 657         }
 658
 659         if (setup->dnf > STM32_I2C_DNF_MAX) {
 660                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 661                       setup->dnf, STM32_I2C_DNF_MAX);
 662                 return -EINVAL;
 663         }
 664
 665         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 666                 pr_err("%s: Freq {%d/%d}\n", __func__,
 667                       setup->speed_freq, i2c_specs[setup->speed].rate);
 668                 return -EINVAL;
 669         }
 670
 671         INIT_LIST_HEAD(&solutions);
 672         ret = stm32_i2c_compute_solutions(setup, &solutions);
 673         if (ret)
 674                 goto exit;
 675
 676         ret = stm32_i2c_choose_solution(setup, &solutions, output);
 677         if (ret)
 678                 goto exit;
 679
 680         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 681               __func__, output->presc,
 682               output->scldel, output->sdadel,
 683               output->scll, output->sclh);
 684
 685 exit:
 686         /* Release list and memory */
 687         list_for_each_entry_safe(v, _v, &solutions, node) {
 688                 list_del(&v->node);
 689                 free(v);
 690         }
 691
 692         return ret;
 693 }
 694
 695 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 696                                     struct stm32_i2c_timings *timing)
 697 {
 698         struct stm32_i2c_setup *setup = i2c_priv->setup;
 699         int ret = 0;
 700
 701         setup->speed = i2c_priv->speed;
 702         setup->speed_freq = i2c_specs[setup->speed].rate;
 703         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 704
 705         if (!setup->clock_src) {
 706                 pr_err("%s: clock rate is 0\n", __func__);
 707                 return -EINVAL;
 708         }
 709
 710         do {
 711                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 712                 if (ret) {
 713                         debug("%s: failed to compute I2C timings.\n",
 714                               __func__);
 715                         if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) {
 716                                 i2c_priv->speed--;
 717                                 setup->speed = i2c_priv->speed;
 718                                 setup->speed_freq =
 719                                         i2c_specs[setup->speed].rate;
 720                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 721                                       __func__, i2c_specs[setup->speed].rate);
 722                         } else {
 723                                 break;
 724                         }
 725                 }
 726         } while (ret);
 727
 728         if (ret) {
 729                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 730                 return ret;
 731         }
 732
 733         debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
 734               setup->speed, setup->speed_freq, setup->clock_src);
 735         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 736               setup->rise_time, setup->fall_time);
 737         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 738               setup->analog_filter ? "On" : "Off", setup->dnf);
 739
 740         return 0;
 741 }
 742
 743 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 744 {
 745         struct stm32_i2c_regs *regs = i2c_priv->regs;
 746         struct stm32_i2c_timings t;
 747         int ret;
 748         u32 timing = 0;
 749
 750         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 751         if (ret)
 752                 return ret;
 753
 754         /* Disable I2C */
 755         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 756
 757         /* Timing settings */
 758         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 759         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 760         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 761         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 762         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 763         writel(timing, &regs->timingr);
 764
 765         /* Enable I2C */
 766         if (i2c_priv->setup->analog_filter)
 767                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 768         else
 769                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 770         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 771
 772         return 0;
 773 }
 774
 775 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 776 {
 777         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 778
 779         switch (speed) {
 780         case STANDARD_RATE:
 781                 i2c_priv->speed = STM32_I2C_SPEED_STANDARD;
 782                 break;
 783         case FAST_RATE:
 784                 i2c_priv->speed = STM32_I2C_SPEED_FAST;
 785                 break;
 786         case FAST_PLUS_RATE:
 787                 i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS;
 788                 break;
 789         default:
 790                 debug("%s: Speed %d not supported\n", __func__, speed);
 791                 return -EINVAL;
 792         }
 793
 794         return stm32_i2c_hw_config(i2c_priv);
 795 }
 796
 797 static int stm32_i2c_probe(struct udevice *dev)
 798 {
 799         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 800         struct reset_ctl reset_ctl;
 801         fdt_addr_t addr;
 802         int ret;
 803
 804         addr = dev_read_addr(dev);
 805         if (addr == FDT_ADDR_T_NONE)
 806                 return -EINVAL;
 807
 808         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 809
 810         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 811         if (ret)
 812                 return ret;
 813
 814         ret = clk_enable(&i2c_priv->clk);
 815         if (ret)
 816                 goto clk_free;
 817
 818         ret = reset_get_by_index(dev, 0, &reset_ctl);
 819         if (ret)
 820                 goto clk_disable;
 821
 822         reset_assert(&reset_ctl);
 823         udelay(2);
 824         reset_deassert(&reset_ctl);
 825
 826         return 0;
 827
 828 clk_disable:
 829         clk_disable(&i2c_priv->clk);
 830 clk_free:
 831         clk_free(&i2c_priv->clk);
 832
 833         return ret;
 834 }
 835
 836 static int stm32_ofdata_to_platdata(struct udevice *dev)
 837 {
 838         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 839         u32 rise_time, fall_time;
 840
 841         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 842         if (!i2c_priv->setup)
 843                 return -EINVAL;
 844
 845         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 846         if (rise_time)
 847                 i2c_priv->setup->rise_time = rise_time;
 848
 849         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 850         if (fall_time)
 851                 i2c_priv->setup->fall_time = fall_time;
 852
 853         return 0;
 854 }
 855
 856 static const struct dm_i2c_ops stm32_i2c_ops = {
 857         .xfer = stm32_i2c_xfer,
 858         .set_bus_speed = stm32_i2c_set_bus_speed,
 859 };
 860
 861 static const struct udevice_id stm32_i2c_of_match[] = {
 862         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 863         {}
 864 };
 865
 866 U_BOOT_DRIVER(stm32f7_i2c) = {
 867         .name = "stm32f7-i2c",
 868         .id = UCLASS_I2C,
 869         .of_match = stm32_i2c_of_match,
 870         .ofdata_to_platdata = stm32_ofdata_to_platdata,
 871         .probe = stm32_i2c_probe,
 872         .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
 873         .ops = &stm32_i2c_ops,
 874 };