2 * (C) Copyright 2017 STMicroelectronics
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <dm/device.h>
16 /* STM32 I2C registers */
17 struct stm32_i2c_regs {
18 u32 cr1; /* I2C control register 1 */
19 u32 cr2; /* I2C control register 2 */
20 u32 oar1; /* I2C own address 1 register */
21 u32 oar2; /* I2C own address 2 register */
22 u32 timingr; /* I2C timing register */
23 u32 timeoutr; /* I2C timeout register */
24 u32 isr; /* I2C interrupt and status register */
25 u32 icr; /* I2C interrupt clear register */
26 u32 pecr; /* I2C packet error checking register */
27 u32 rxdr; /* I2C receive data register */
28 u32 txdr; /* I2C transmit data register */
31 #define STM32_I2C_CR1 0x00
32 #define STM32_I2C_CR2 0x04
33 #define STM32_I2C_TIMINGR 0x10
34 #define STM32_I2C_ISR 0x18
35 #define STM32_I2C_ICR 0x1C
36 #define STM32_I2C_RXDR 0x24
37 #define STM32_I2C_TXDR 0x28
39 /* STM32 I2C control 1 */
40 #define STM32_I2C_CR1_ANFOFF BIT(12)
41 #define STM32_I2C_CR1_ERRIE BIT(7)
42 #define STM32_I2C_CR1_TCIE BIT(6)
43 #define STM32_I2C_CR1_STOPIE BIT(5)
44 #define STM32_I2C_CR1_NACKIE BIT(4)
45 #define STM32_I2C_CR1_ADDRIE BIT(3)
46 #define STM32_I2C_CR1_RXIE BIT(2)
47 #define STM32_I2C_CR1_TXIE BIT(1)
48 #define STM32_I2C_CR1_PE BIT(0)
50 /* STM32 I2C control 2 */
51 #define STM32_I2C_CR2_AUTOEND BIT(25)
52 #define STM32_I2C_CR2_RELOAD BIT(24)
53 #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
54 #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
55 #define STM32_I2C_CR2_NACK BIT(15)
56 #define STM32_I2C_CR2_STOP BIT(14)
57 #define STM32_I2C_CR2_START BIT(13)
58 #define STM32_I2C_CR2_HEAD10R BIT(12)
59 #define STM32_I2C_CR2_ADD10 BIT(11)
60 #define STM32_I2C_CR2_RD_WRN BIT(10)
61 #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
62 #define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK))
63 #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
64 #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
65 #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
66 | STM32_I2C_CR2_NBYTES_MASK \
67 | STM32_I2C_CR2_SADD7_MASK \
68 | STM32_I2C_CR2_RELOAD \
69 | STM32_I2C_CR2_RD_WRN)
71 /* STM32 I2C Interrupt Status */
72 #define STM32_I2C_ISR_BUSY BIT(15)
73 #define STM32_I2C_ISR_ARLO BIT(9)
74 #define STM32_I2C_ISR_BERR BIT(8)
75 #define STM32_I2C_ISR_TCR BIT(7)
76 #define STM32_I2C_ISR_TC BIT(6)
77 #define STM32_I2C_ISR_STOPF BIT(5)
78 #define STM32_I2C_ISR_NACKF BIT(4)
79 #define STM32_I2C_ISR_ADDR BIT(3)
80 #define STM32_I2C_ISR_RXNE BIT(2)
81 #define STM32_I2C_ISR_TXIS BIT(1)
82 #define STM32_I2C_ISR_TXE BIT(0)
83 #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
86 /* STM32 I2C Interrupt Clear */
87 #define STM32_I2C_ICR_ARLOCF BIT(9)
88 #define STM32_I2C_ICR_BERRCF BIT(8)
89 #define STM32_I2C_ICR_STOPCF BIT(5)
90 #define STM32_I2C_ICR_NACKCF BIT(4)
92 /* STM32 I2C Timing */
93 #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
94 #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
95 #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
96 #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
97 #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
99 #define STM32_I2C_MAX_LEN 0xff
101 #define STM32_I2C_DNF_DEFAULT 0
102 #define STM32_I2C_DNF_MAX 16
104 #define STM32_I2C_ANALOG_FILTER_ENABLE 1
105 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
106 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
108 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
109 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
111 #define STM32_PRESC_MAX BIT(4)
112 #define STM32_SCLDEL_MAX BIT(4)
113 #define STM32_SDADEL_MAX BIT(4)
114 #define STM32_SCLH_MAX BIT(8)
115 #define STM32_SCLL_MAX BIT(8)
117 #define STM32_NSEC_PER_SEC 1000000000L
119 #define STANDARD_RATE 100000
120 #define FAST_RATE 400000
121 #define FAST_PLUS_RATE 1000000
123 enum stm32_i2c_speed {
124 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
125 STM32_I2C_SPEED_FAST, /* 400 kHz */
126 STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
131 * struct stm32_i2c_spec - private i2c specification timing
132 * @rate: I2C bus speed (Hz)
133 * @rate_min: 80% of I2C bus speed (Hz)
134 * @rate_max: 120% of I2C bus speed (Hz)
135 * @fall_max: Max fall time of both SDA and SCL signals (ns)
136 * @rise_max: Max rise time of both SDA and SCL signals (ns)
137 * @hddat_min: Min data hold time (ns)
138 * @vddat_max: Max data valid time (ns)
139 * @sudat_min: Min data setup time (ns)
140 * @l_min: Min low period of the SCL clock (ns)
141 * @h_min: Min high period of the SCL clock (ns)
144 struct stm32_i2c_spec {
158 * struct stm32_i2c_setup - private I2C timing setup parameters
159 * @speed: I2C speed mode (standard, Fast Plus)
160 * @speed_freq: I2C speed frequency (Hz)
161 * @clock_src: I2C clock source frequency (Hz)
162 * @rise_time: Rise time (ns)
163 * @fall_time: Fall time (ns)
164 * @dnf: Digital filter coefficient (0-16)
165 * @analog_filter: Analog filter delay (On/Off)
167 struct stm32_i2c_setup {
168 enum stm32_i2c_speed speed;
178 * struct stm32_i2c_timings - private I2C output parameters
179 * @prec: Prescaler value
180 * @scldel: Data setup time
181 * @sdadel: Data hold time
182 * @sclh: SCL high period (master mode)
183 * @sclh: SCL low period (master mode)
185 struct stm32_i2c_timings {
186 struct list_head node;
194 struct stm32_i2c_priv {
195 struct stm32_i2c_regs *regs;
197 struct stm32_i2c_setup *setup;
201 static struct stm32_i2c_spec i2c_specs[] = {
202 [STM32_I2C_SPEED_STANDARD] = {
203 .rate = STANDARD_RATE,
214 [STM32_I2C_SPEED_FAST] = {
226 [STM32_I2C_SPEED_FAST_PLUS] = {
227 .rate = FAST_PLUS_RATE,
240 static struct stm32_i2c_setup stm32f7_setup = {
241 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
242 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
243 .dnf = STM32_I2C_DNF_DEFAULT,
244 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
247 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
249 struct stm32_i2c_regs *regs = i2c_priv->regs;
250 u32 status = readl(®s->isr);
252 if (status & STM32_I2C_ISR_BUSY)
258 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
259 struct i2c_msg *msg, bool stop)
261 struct stm32_i2c_regs *regs = i2c_priv->regs;
262 u32 cr2 = readl(®s->cr2);
264 /* Set transfer direction */
265 cr2 &= ~STM32_I2C_CR2_RD_WRN;
266 if (msg->flags & I2C_M_RD)
267 cr2 |= STM32_I2C_CR2_RD_WRN;
269 /* Set slave address */
270 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
271 if (msg->flags & I2C_M_TEN) {
272 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
273 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
274 cr2 |= STM32_I2C_CR2_ADD10;
276 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
277 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
280 /* Set nb bytes to transfer and reload or autoend bits */
281 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
282 STM32_I2C_CR2_AUTOEND);
283 if (msg->len > STM32_I2C_MAX_LEN) {
284 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
285 cr2 |= STM32_I2C_CR2_RELOAD;
287 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
290 /* Write configurations register */
291 writel(cr2, ®s->cr2);
293 /* START/ReSTART generation */
294 setbits_le32(®s->cr2, STM32_I2C_CR2_START);
298 * RELOAD mode must be selected if total number of data bytes to be
299 * sent is greater than MAX_LEN
302 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
303 struct i2c_msg *msg, bool stop)
305 struct stm32_i2c_regs *regs = i2c_priv->regs;
306 u32 cr2 = readl(®s->cr2);
308 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
310 if (msg->len > STM32_I2C_MAX_LEN) {
311 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
313 cr2 &= ~STM32_I2C_CR2_RELOAD;
314 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
317 writel(cr2, ®s->cr2);
320 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
321 u32 flags, u32 *status)
323 struct stm32_i2c_regs *regs = i2c_priv->regs;
324 u32 time_start = get_timer(0);
326 *status = readl(®s->isr);
327 while (!(*status & flags)) {
328 if (get_timer(time_start) > CONFIG_SYS_HZ) {
329 debug("%s: i2c timeout\n", __func__);
333 *status = readl(®s->isr);
339 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
341 struct stm32_i2c_regs *regs = i2c_priv->regs;
342 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
347 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
351 if (status & STM32_I2C_ISR_BERR) {
352 debug("%s: Bus error\n", __func__);
354 /* Clear BERR flag */
355 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF);
360 if (status & STM32_I2C_ISR_ARLO) {
361 debug("%s: Arbitration lost\n", __func__);
363 /* Clear ARLO flag */
364 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF);
369 if (status & STM32_I2C_ISR_NACKF) {
370 debug("%s: Receive NACK\n", __func__);
372 /* Clear NACK flag */
373 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF);
375 /* Wait until STOPF flag is set */
376 mask = STM32_I2C_ISR_STOPF;
377 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
384 if (status & STM32_I2C_ISR_STOPF) {
385 /* Clear STOP flag */
386 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF);
388 /* Clear control register 2 */
389 setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK);
395 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
396 struct i2c_msg *msg, bool stop)
398 struct stm32_i2c_regs *regs = i2c_priv->regs;
400 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
401 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
402 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
403 STM32_I2C_MAX_LEN : msg->len;
407 mask |= STM32_I2C_ISR_ERRORS;
409 stm32_i2c_message_start(i2c_priv, msg, stop);
413 * Wait until TXIS/NACKF/BERR/ARLO flags or
414 * RXNE/BERR/ARLO flags are set
416 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
420 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
423 if (status & STM32_I2C_ISR_RXNE) {
424 *msg->buf++ = readb(®s->rxdr);
429 if (status & STM32_I2C_ISR_TXIS) {
430 writeb(*msg->buf++, ®s->txdr);
435 if (!bytes_to_rw && msg->len) {
436 /* Wait until TCR flag is set */
437 mask = STM32_I2C_ISR_TCR;
438 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
442 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
443 STM32_I2C_MAX_LEN : msg->len;
444 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
445 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
447 stm32_i2c_handle_reload(i2c_priv, msg, stop);
448 } else if (!bytes_to_rw) {
449 /* Wait until TC flag is set */
450 mask = STM32_I2C_ISR_TC;
451 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
456 /* Message sent, new message has to be sent */
461 /* End of transfer, send stop condition */
462 mask = STM32_I2C_CR2_STOP;
463 setbits_le32(®s->cr2, mask);
465 return stm32_i2c_check_end_of_message(i2c_priv);
468 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
471 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
474 ret = stm32_i2c_check_device_busy(i2c_priv);
478 for (; nmsgs > 0; nmsgs--, msg++) {
479 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
487 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
488 struct list_head *solutions)
490 struct stm32_i2c_timings *v;
491 u32 p_prev = STM32_PRESC_MAX;
492 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
494 u32 af_delay_min, af_delay_max;
496 int sdadel_min, sdadel_max, scldel_min;
499 af_delay_min = setup->analog_filter ?
500 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
501 af_delay_max = setup->analog_filter ?
502 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
504 sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
505 af_delay_min - (setup->dnf + 3) * i2cclk;
507 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
508 af_delay_max - (setup->dnf + 4) * i2cclk;
510 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
517 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
518 sdadel_min, sdadel_max, scldel_min);
520 /* Compute possible values for PRESC, SCLDEL and SDADEL */
521 for (p = 0; p < STM32_PRESC_MAX; p++) {
522 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
523 u32 scldel = (l + 1) * (p + 1) * i2cclk;
525 if (scldel < scldel_min)
528 for (a = 0; a < STM32_SDADEL_MAX; a++) {
529 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
531 if (((sdadel >= sdadel_min) &&
532 (sdadel <= sdadel_max)) &&
534 v = calloc(1, sizeof(*v));
543 list_add_tail(&v->node, solutions);
549 if (list_empty(solutions)) {
550 pr_err("%s: no Prescaler solution\n", __func__);
557 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
558 struct list_head *solutions,
559 struct stm32_i2c_timings *s)
561 struct stm32_i2c_timings *v;
562 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
564 u32 clk_error_prev = i2cbus;
565 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
567 u32 clk_min, clk_max;
572 bool sol_found = false;
575 af_delay_min = setup->analog_filter ?
576 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
577 dnf_delay = setup->dnf * i2cclk;
579 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
580 clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
581 clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
584 * Among Prescaler possibilities discovered above figures out SCL Low
585 * and High Period. Provided:
586 * - SCL Low Period has to be higher than Low Period of the SCL Clock
587 * defined by I2C Specification. I2C Clock has to be lower than
588 * (SCL Low Period - Analog/Digital filters) / 4.
589 * - SCL High Period has to be lower than High Period of the SCL Clock
590 * defined by I2C Specification
591 * - I2C Clock has to be lower than SCL High Period
593 list_for_each_entry(v, solutions, node) {
594 u32 prescaler = (v->presc + 1) * i2cclk;
596 for (l = 0; l < STM32_SCLL_MAX; l++) {
597 u32 tscl_l = (l + 1) * prescaler + tsync;
598 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
600 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
604 for (h = 0; h < STM32_SCLH_MAX; h++) {
605 u32 tscl_h = (h + 1) * prescaler + tsync;
606 u32 tscl = tscl_l + tscl_h +
607 setup->rise_time + setup->fall_time;
609 if ((tscl >= clk_min) && (tscl <= clk_max) &&
610 (tscl_h >= i2c_specs[setup->speed].h_min) &&
612 int clk_error = tscl - i2cbus;
615 clk_error = -clk_error;
617 if (clk_error < clk_error_prev) {
618 clk_error_prev = clk_error;
622 memcpy(s, v, sizeof(*s));
630 pr_err("%s: no solution at all\n", __func__);
637 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
638 struct stm32_i2c_setup *setup,
639 struct stm32_i2c_timings *output)
641 struct stm32_i2c_timings *v, *_v;
642 struct list_head solutions;
645 if (setup->speed >= STM32_I2C_SPEED_END) {
646 pr_err("%s: speed out of bound {%d/%d}\n", __func__,
647 setup->speed, STM32_I2C_SPEED_END - 1);
651 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
652 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
653 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
655 setup->rise_time, i2c_specs[setup->speed].rise_max,
656 setup->fall_time, i2c_specs[setup->speed].fall_max);
660 if (setup->dnf > STM32_I2C_DNF_MAX) {
661 pr_err("%s: DNF out of bound %d/%d\n", __func__,
662 setup->dnf, STM32_I2C_DNF_MAX);
666 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
667 pr_err("%s: Freq {%d/%d}\n", __func__,
668 setup->speed_freq, i2c_specs[setup->speed].rate);
672 INIT_LIST_HEAD(&solutions);
673 ret = stm32_i2c_compute_solutions(setup, &solutions);
677 ret = stm32_i2c_choose_solution(setup, &solutions, output);
681 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
682 __func__, output->presc,
683 output->scldel, output->sdadel,
684 output->scll, output->sclh);
687 /* Release list and memory */
688 list_for_each_entry_safe(v, _v, &solutions, node) {
696 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
697 struct stm32_i2c_timings *timing)
699 struct stm32_i2c_setup *setup = i2c_priv->setup;
702 setup->speed = i2c_priv->speed;
703 setup->speed_freq = i2c_specs[setup->speed].rate;
704 setup->clock_src = clk_get_rate(&i2c_priv->clk);
706 if (!setup->clock_src) {
707 pr_err("%s: clock rate is 0\n", __func__);
712 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
714 debug("%s: failed to compute I2C timings.\n",
716 if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) {
718 setup->speed = i2c_priv->speed;
720 i2c_specs[setup->speed].rate;
721 debug("%s: downgrade I2C Speed Freq to (%i)\n",
722 __func__, i2c_specs[setup->speed].rate);
730 pr_err("%s: impossible to compute I2C timings.\n", __func__);
734 debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
735 setup->speed, setup->speed_freq, setup->clock_src);
736 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
737 setup->rise_time, setup->fall_time);
738 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
739 setup->analog_filter ? "On" : "Off", setup->dnf);
744 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
746 struct stm32_i2c_regs *regs = i2c_priv->regs;
747 struct stm32_i2c_timings t;
751 ret = stm32_i2c_setup_timing(i2c_priv, &t);
756 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE);
758 /* Timing settings */
759 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
760 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
761 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
762 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
763 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
764 writel(timing, ®s->timingr);
767 if (i2c_priv->setup->analog_filter)
768 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
770 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
771 setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
776 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
778 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
782 i2c_priv->speed = STM32_I2C_SPEED_STANDARD;
785 i2c_priv->speed = STM32_I2C_SPEED_FAST;
788 i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS;
791 debug("%s: Speed %d not supported\n", __func__, speed);
795 return stm32_i2c_hw_config(i2c_priv);
798 static int stm32_i2c_probe(struct udevice *dev)
800 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
801 struct reset_ctl reset_ctl;
805 addr = dev_read_addr(dev);
806 if (addr == FDT_ADDR_T_NONE)
809 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
811 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
815 ret = clk_enable(&i2c_priv->clk);
819 ret = reset_get_by_index(dev, 0, &reset_ctl);
823 reset_assert(&reset_ctl);
825 reset_deassert(&reset_ctl);
830 clk_disable(&i2c_priv->clk);
832 clk_free(&i2c_priv->clk);
837 static int stm32_ofdata_to_platdata(struct udevice *dev)
839 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
840 u32 rise_time, fall_time;
842 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
843 if (!i2c_priv->setup)
846 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
848 i2c_priv->setup->rise_time = rise_time;
850 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
852 i2c_priv->setup->fall_time = fall_time;
857 static const struct dm_i2c_ops stm32_i2c_ops = {
858 .xfer = stm32_i2c_xfer,
859 .set_bus_speed = stm32_i2c_set_bus_speed,
862 static const struct udevice_id stm32_i2c_of_match[] = {
863 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
867 U_BOOT_DRIVER(stm32f7_i2c) = {
868 .name = "stm32f7-i2c",
870 .of_match = stm32_i2c_of_match,
871 .ofdata_to_platdata = stm32_ofdata_to_platdata,
872 .probe = stm32_i2c_probe,
873 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
874 .ops = &stm32_i2c_ops,