2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
16 #ifndef CONFIG_TEGRA186
17 #include <asm/arch/clock.h>
18 #include <asm/arch/funcmux.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch-tegra/tegra_i2c.h>
29 /* Information about i2c controller */
32 struct reset_ctl reset_ctl;
36 struct i2c_control *control;
37 struct i2c_ctlr *regs;
39 int inited; /* bus is inited */
42 static void set_packet_mode(struct i2c_bus *i2c_bus)
46 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
48 if (i2c_bus->type == TYPE_DVC) {
49 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
51 writel(config, &dvc->cnfg);
53 writel(config, &i2c_bus->regs->cnfg);
55 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
56 * issues, i.e., some slaves may be wrongly detected.
58 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
62 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
64 /* Reset I2C controller. */
65 reset_assert(&i2c_bus->reset_ctl);
67 reset_deassert(&i2c_bus->reset_ctl);
70 /* re-program config register to packet mode */
71 set_packet_mode(i2c_bus);
74 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
78 ret = reset_assert(&i2c_bus->reset_ctl);
81 ret = clk_enable(&i2c_bus->clk);
84 ret = clk_set_rate(&i2c_bus->clk, rate);
85 if (IS_ERR_VALUE(ret))
87 ret = reset_deassert(&i2c_bus->reset_ctl);
94 static void i2c_init_controller(struct i2c_bus *i2c_bus)
98 debug("%s: speed=%d\n", __func__, i2c_bus->speed);
100 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
101 * here, in section 23.3.1, but in fact we seem to need a factor of
102 * 16 to get the right frequency.
104 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
106 if (i2c_bus->type == TYPE_114) {
108 * T114 I2C went to a single clock source for standard/fast and
109 * HS clock speeds. The new clock rate setting calculation is:
110 * SCL = CLK_SOURCE.I2C /
111 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
112 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
114 * NOTE: We do this here, after the initial clock/pll start,
115 * because if we read the clk_div reg before the controller
116 * is running, we hang, and we need it for the new calc.
118 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
119 unsigned rate = CLK_MULT_STD_FAST_MODE *
120 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
121 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
122 clk_div_stdfst_mode);
124 i2c_init_clock(i2c_bus, rate);
127 /* Reset I2C controller. */
128 i2c_reset_controller(i2c_bus);
130 /* Configure I2C controller. */
131 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
132 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
134 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
137 #ifndef CONFIG_TEGRA186
138 funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
142 static void send_packet_headers(
143 struct i2c_bus *i2c_bus,
144 struct i2c_trans_info *trans,
146 bool end_with_repeated_start)
150 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
151 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
152 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
153 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
154 writel(data, &i2c_bus->control->tx_fifo);
155 debug("pkt header 1 sent (0x%x)\n", data);
157 /* prepare header2 */
158 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
159 writel(data, &i2c_bus->control->tx_fifo);
160 debug("pkt header 2 sent (0x%x)\n", data);
162 /* prepare IO specific header: configure the slave address */
163 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
165 /* Enable Read if it is not a write transaction */
166 if (!(trans->flags & I2C_IS_WRITE))
167 data |= PKT_HDR3_READ_MODE_MASK;
168 if (end_with_repeated_start)
169 data |= PKT_HDR3_REPEAT_START_MASK;
171 /* Write I2C specific header */
172 writel(data, &i2c_bus->control->tx_fifo);
173 debug("pkt header 3 sent (0x%x)\n", data);
176 static int wait_for_tx_fifo_empty(struct i2c_control *control)
179 int timeout_us = I2C_TIMEOUT_USEC;
181 while (timeout_us >= 0) {
182 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
183 >> TX_FIFO_EMPTY_CNT_SHIFT;
184 if (count == I2C_FIFO_DEPTH)
193 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
196 int timeout_us = I2C_TIMEOUT_USEC;
198 while (timeout_us >= 0) {
199 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
200 >> TX_FIFO_FULL_CNT_SHIFT;
210 static int wait_for_transfer_complete(struct i2c_control *control)
213 int timeout_us = I2C_TIMEOUT_USEC;
215 while (timeout_us >= 0) {
216 int_status = readl(&control->int_status);
217 if (int_status & I2C_INT_NO_ACK_MASK)
219 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
221 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
231 static int send_recv_packets(struct i2c_bus *i2c_bus,
232 struct i2c_trans_info *trans)
234 struct i2c_control *control = i2c_bus->control;
241 int is_write = trans->flags & I2C_IS_WRITE;
243 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
244 int_status = readl(&control->int_status);
245 writel(int_status, &control->int_status);
247 send_packet_headers(i2c_bus, trans, 1,
248 trans->flags & I2C_USE_REPEATED_START);
250 words = DIV_ROUND_UP(trans->num_bytes, 4);
251 last_bytes = trans->num_bytes & 3;
255 u32 *wptr = (u32 *)dptr;
258 /* deal with word alignment */
259 if ((words == 1) && last_bytes) {
261 memcpy(&local, dptr, last_bytes);
262 } else if ((unsigned long)dptr & 3) {
263 memcpy(&local, dptr, sizeof(u32));
267 writel(local, &control->tx_fifo);
268 debug("pkt data sent (0x%x)\n", local);
269 if (!wait_for_tx_fifo_empty(control)) {
274 if (!wait_for_rx_fifo_notempty(control)) {
279 * for the last word, we read into our local buffer,
280 * in case that caller did not provide enough buffer.
282 local = readl(&control->rx_fifo);
283 if ((words == 1) && last_bytes)
284 memcpy(dptr, (char *)&local, last_bytes);
285 else if ((unsigned long)dptr & 3)
286 memcpy(dptr, &local, sizeof(u32));
289 debug("pkt data received (0x%x)\n", local);
295 if (wait_for_transfer_complete(control)) {
301 /* error, reset the controller. */
302 i2c_reset_controller(i2c_bus);
307 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
308 u32 len, bool end_with_repeated_start)
311 struct i2c_trans_info trans_info;
313 trans_info.address = addr;
314 trans_info.buf = data;
315 trans_info.flags = I2C_IS_WRITE;
316 if (end_with_repeated_start)
317 trans_info.flags |= I2C_USE_REPEATED_START;
318 trans_info.num_bytes = len;
319 trans_info.is_10bit_address = 0;
321 error = send_recv_packets(i2c_bus, &trans_info);
323 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
328 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
332 struct i2c_trans_info trans_info;
334 trans_info.address = addr | 1;
335 trans_info.buf = data;
336 trans_info.flags = 0;
337 trans_info.num_bytes = len;
338 trans_info.is_10bit_address = 0;
340 error = send_recv_packets(i2c_bus, &trans_info);
342 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
347 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
349 struct i2c_bus *i2c_bus = dev_get_priv(dev);
351 i2c_bus->speed = speed;
352 i2c_init_controller(i2c_bus);
357 static int tegra_i2c_probe(struct udevice *dev)
359 struct i2c_bus *i2c_bus = dev_get_priv(dev);
363 i2c_bus->id = dev->seq;
364 i2c_bus->type = dev_get_driver_data(dev);
365 i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
366 if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
367 debug("%s: Cannot get regs address\n", __func__);
371 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
373 pr_err("reset_get_by_name() failed: %d\n", ret);
376 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
378 pr_err("clk_get_by_name() failed: %d\n", ret);
382 #ifndef CONFIG_TEGRA186
384 * We don't have a binding for pinmux yet. Leave it out for now. So
385 * far no one needs anything other than the default.
387 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
390 * We can't specify the pinmux config in the fdt, so I2C2 will not
391 * work on Seaboard. It normally has no devices on it anyway.
392 * You could add in this little hack if you need to use it.
393 * The correct solution is a pinmux binding in the fdt.
395 * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
396 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
400 is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
403 &((struct dvc_ctlr *)i2c_bus->regs)->control;
405 i2c_bus->control = &i2c_bus->regs->control;
407 i2c_init_controller(i2c_bus);
408 debug("%s: controller bus %d at %p, speed %d: ",
409 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
414 /* i2c write version without the register address */
415 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
416 int len, bool end_with_repeated_start)
420 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
421 debug("write_data: ");
422 /* use rc for counter */
423 for (rc = 0; rc < len; ++rc)
424 debug(" 0x%02x", buffer[rc]);
427 /* Shift 7-bit address over for lower-level i2c functions */
428 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
429 end_with_repeated_start);
431 debug("i2c_write_data(): rc=%d\n", rc);
436 /* i2c read version without the register address */
437 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
442 debug("inside i2c_read_data():\n");
443 /* Shift 7-bit address over for lower-level i2c functions */
444 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
446 debug("i2c_read_data(): rc=%d\n", rc);
450 debug("i2c_read_data: ");
451 /* reuse rc for counter*/
452 for (rc = 0; rc < len; ++rc)
453 debug(" 0x%02x", buffer[rc]);
459 /* Probe to see if a chip is present. */
460 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
463 struct i2c_bus *i2c_bus = dev_get_priv(bus);
467 /* Shift 7-bit address over for lower-level i2c functions */
468 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg),
474 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
477 struct i2c_bus *i2c_bus = dev_get_priv(bus);
480 debug("i2c_xfer: %d messages\n", nmsgs);
481 for (; nmsgs > 0; nmsgs--, msg++) {
482 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
484 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
485 if (msg->flags & I2C_M_RD) {
486 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
489 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
490 msg->len, next_is_read);
493 debug("i2c_write: error sending\n");
501 int tegra_i2c_get_dvc_bus(struct udevice **busp)
505 for (uclass_first_device(UCLASS_I2C, &bus);
507 uclass_next_device(&bus)) {
508 if (dev_get_driver_data(bus) == TYPE_DVC) {
517 static const struct dm_i2c_ops tegra_i2c_ops = {
518 .xfer = tegra_i2c_xfer,
519 .probe_chip = tegra_i2c_probe_chip,
520 .set_bus_speed = tegra_i2c_set_bus_speed,
523 static const struct udevice_id tegra_i2c_ids[] = {
524 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
525 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
526 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
530 U_BOOT_DRIVER(i2c_tegra) = {
533 .of_match = tegra_i2c_ids,
534 .probe = tegra_i2c_probe,
535 .priv_auto_alloc_size = sizeof(struct i2c_bus),
536 .ops = &tegra_i2c_ops,