2 * Driver for the Zynq-7000 PS I2C controller
3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * Author: Joe Hershberger <joe.hershberger@ni.com>
6 * Copyright (c) 2012 Joe Hershberger.
8 * Copyright (c) 2012-2013 Xilinx, Michal Simek
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/errno.h>
17 #include <asm/arch/hardware.h>
19 /* i2c register set */
20 struct zynq_i2c_registers {
31 u32 interrupt_disable;
34 /* Control register fields */
35 #define ZYNQ_I2C_CONTROL_RW 0x00000001
36 #define ZYNQ_I2C_CONTROL_MS 0x00000002
37 #define ZYNQ_I2C_CONTROL_NEA 0x00000004
38 #define ZYNQ_I2C_CONTROL_ACKEN 0x00000008
39 #define ZYNQ_I2C_CONTROL_HOLD 0x00000010
40 #define ZYNQ_I2C_CONTROL_SLVMON 0x00000020
41 #define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040
42 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8
43 #define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00
44 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14
45 #define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000
47 /* Status register values */
48 #define ZYNQ_I2C_STATUS_RXDV 0x00000020
49 #define ZYNQ_I2C_STATUS_TXDV 0x00000040
50 #define ZYNQ_I2C_STATUS_RXOVF 0x00000080
51 #define ZYNQ_I2C_STATUS_BA 0x00000100
53 /* Interrupt register fields */
54 #define ZYNQ_I2C_INTERRUPT_COMP 0x00000001
55 #define ZYNQ_I2C_INTERRUPT_DATA 0x00000002
56 #define ZYNQ_I2C_INTERRUPT_NACK 0x00000004
57 #define ZYNQ_I2C_INTERRUPT_TO 0x00000008
58 #define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010
59 #define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020
60 #define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040
61 #define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
62 #define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
64 #define ZYNQ_I2C_FIFO_DEPTH 16
65 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
67 #if defined(CONFIG_ZYNQ_I2C0)
68 # define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0
70 # define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1
73 static struct zynq_i2c_registers *zynq_i2c =
74 (struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
76 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
77 static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
80 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
81 writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
82 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
84 /* Enable master mode, ack, and 7-bit addressing */
85 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
86 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
90 static void zynq_i2c_debug_status(void)
94 int_status = readl(&zynq_i2c->interrupt_status);
96 status = readl(&zynq_i2c->status);
97 if (int_status || status) {
99 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
101 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
103 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
105 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
107 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
109 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
111 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
115 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
117 if (status & ZYNQ_I2C_STATUS_RXDV)
119 if (status & ZYNQ_I2C_STATUS_TXDV)
121 if (status & ZYNQ_I2C_STATUS_RXOVF)
123 if (status & ZYNQ_I2C_STATUS_BA)
125 debug("TS%d ", readl(&zynq_i2c->transfer_size));
131 /* Wait for an interrupt */
132 static u32 zynq_i2c_wait(u32 mask)
134 int timeout, int_status;
136 for (timeout = 0; timeout < 100; timeout++) {
138 int_status = readl(&zynq_i2c->interrupt_status);
139 if (int_status & mask)
143 zynq_i2c_debug_status();
145 /* Clear interrupt status flags */
146 writel(int_status & mask, &zynq_i2c->interrupt_status);
148 return int_status & mask;
152 * I2C probe called by cmd_i2c when doing 'i2c probe'.
153 * Begin read, nak data byte, end.
155 static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
157 /* Attempt to read a byte */
158 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
159 ZYNQ_I2C_CONTROL_RW);
160 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
161 writel(0xFF, &zynq_i2c->interrupt_status);
162 writel(dev, &zynq_i2c->address);
163 writel(1, &zynq_i2c->transfer_size);
165 return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
166 ZYNQ_I2C_INTERRUPT_NACK) &
167 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
171 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
172 * Begin write, send address byte(s), begin read, receive data bytes, end.
174 static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
175 int alen, u8 *data, int length)
181 /* Check the hardware can handle the requested bytes */
182 if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
185 /* Write the register address */
186 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
187 ZYNQ_I2C_CONTROL_HOLD);
189 * Temporarily disable restart (by clearing hold)
190 * It doesn't seem to work.
192 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
193 ZYNQ_I2C_CONTROL_HOLD);
194 writel(0xFF, &zynq_i2c->interrupt_status);
196 writel(addr >> (8*alen), &zynq_i2c->data);
197 writel(dev, &zynq_i2c->address);
199 /* Wait for the address to be sent */
200 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
201 /* Release the bus */
202 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
205 debug("Device acked address\n");
207 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
208 ZYNQ_I2C_CONTROL_RW);
209 /* Start reading data */
210 writel(dev, &zynq_i2c->address);
211 writel(length, &zynq_i2c->transfer_size);
215 status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
216 ZYNQ_I2C_INTERRUPT_DATA);
218 /* Release the bus */
219 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
222 debug("Read %d bytes\n",
223 length - readl(&zynq_i2c->transfer_size));
224 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
225 *(cur_data++) = readl(&zynq_i2c->data);
226 } while (readl(&zynq_i2c->transfer_size) != 0);
227 /* All done... release the bus */
228 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
231 zynq_i2c_debug_status();
237 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
238 * Begin write, send address byte(s), send data bytes, end.
240 static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
241 int alen, u8 *data, int length)
245 /* Write the register address */
246 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
247 ZYNQ_I2C_CONTROL_HOLD);
248 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
249 writel(0xFF, &zynq_i2c->interrupt_status);
251 writel(addr >> (8*alen), &zynq_i2c->data);
252 /* Start the tranfer */
253 writel(dev, &zynq_i2c->address);
254 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
255 /* Release the bus */
256 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
260 debug("Device acked address\n");
262 writel(*(cur_data++), &zynq_i2c->data);
263 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
264 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
265 /* Release the bus */
266 clrbits_le32(&zynq_i2c->control,
267 ZYNQ_I2C_CONTROL_HOLD);
273 /* All done... release the bus */
274 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
275 /* Wait for the address and data to be sent */
276 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP))
281 static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
284 if (speed != 1000000)
290 U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
291 zynq_i2c_write, zynq_i2c_set_bus_speed,
292 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,