2 * Driver for the Zynq-7000 PS I2C controller
3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * Author: Joe Hershberger <joe.hershberger@ni.com>
6 * Copyright (c) 2012 Joe Hershberger.
8 * Copyright (c) 2012-2013 Xilinx, Michal Simek
10 * SPDX-License-Identifier: GPL-2.0+
12 * NOTE: This driver should be converted to driver model before June 2017.
13 * Please see doc/driver-model/i2c-howto.txt for instructions.
19 #include <linux/errno.h>
20 #include <asm/arch/hardware.h>
22 /* i2c register set */
23 struct zynq_i2c_registers {
34 u32 interrupt_disable;
37 /* Control register fields */
38 #define ZYNQ_I2C_CONTROL_RW 0x00000001
39 #define ZYNQ_I2C_CONTROL_MS 0x00000002
40 #define ZYNQ_I2C_CONTROL_NEA 0x00000004
41 #define ZYNQ_I2C_CONTROL_ACKEN 0x00000008
42 #define ZYNQ_I2C_CONTROL_HOLD 0x00000010
43 #define ZYNQ_I2C_CONTROL_SLVMON 0x00000020
44 #define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040
45 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8
46 #define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00
47 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14
48 #define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000
50 /* Status register values */
51 #define ZYNQ_I2C_STATUS_RXDV 0x00000020
52 #define ZYNQ_I2C_STATUS_TXDV 0x00000040
53 #define ZYNQ_I2C_STATUS_RXOVF 0x00000080
54 #define ZYNQ_I2C_STATUS_BA 0x00000100
56 /* Interrupt register fields */
57 #define ZYNQ_I2C_INTERRUPT_COMP 0x00000001
58 #define ZYNQ_I2C_INTERRUPT_DATA 0x00000002
59 #define ZYNQ_I2C_INTERRUPT_NACK 0x00000004
60 #define ZYNQ_I2C_INTERRUPT_TO 0x00000008
61 #define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010
62 #define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020
63 #define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040
64 #define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
65 #define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
67 #define ZYNQ_I2C_FIFO_DEPTH 16
68 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
70 static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
72 return adap->hwadapnr ?
74 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
76 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
79 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
80 static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
83 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
85 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
86 writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
87 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
89 /* Enable master mode, ack, and 7-bit addressing */
90 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
91 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
95 static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
99 int_status = readl(&zynq_i2c->interrupt_status);
101 status = readl(&zynq_i2c->status);
102 if (int_status || status) {
104 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
106 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
108 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
110 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
112 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
114 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
116 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
118 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
120 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
122 if (status & ZYNQ_I2C_STATUS_RXDV)
124 if (status & ZYNQ_I2C_STATUS_TXDV)
126 if (status & ZYNQ_I2C_STATUS_RXOVF)
128 if (status & ZYNQ_I2C_STATUS_BA)
130 debug("TS%d ", readl(&zynq_i2c->transfer_size));
136 /* Wait for an interrupt */
137 static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
139 int timeout, int_status;
141 for (timeout = 0; timeout < 100; timeout++) {
143 int_status = readl(&zynq_i2c->interrupt_status);
144 if (int_status & mask)
148 zynq_i2c_debug_status(zynq_i2c);
150 /* Clear interrupt status flags */
151 writel(int_status & mask, &zynq_i2c->interrupt_status);
153 return int_status & mask;
157 * I2C probe called by cmd_i2c when doing 'i2c probe'.
158 * Begin read, nak data byte, end.
160 static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
162 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
164 /* Attempt to read a byte */
165 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
166 ZYNQ_I2C_CONTROL_RW);
167 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
168 writel(0xFF, &zynq_i2c->interrupt_status);
169 writel(dev, &zynq_i2c->address);
170 writel(1, &zynq_i2c->transfer_size);
172 return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
173 ZYNQ_I2C_INTERRUPT_NACK) &
174 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
178 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
179 * Begin write, send address byte(s), begin read, receive data bytes, end.
181 static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
182 int alen, u8 *data, int length)
187 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
189 /* Check the hardware can handle the requested bytes */
190 if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
193 /* Write the register address */
194 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
195 ZYNQ_I2C_CONTROL_HOLD);
197 * Temporarily disable restart (by clearing hold)
198 * It doesn't seem to work.
200 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
201 writel(0xFF, &zynq_i2c->interrupt_status);
203 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
204 writel(dev, &zynq_i2c->address);
206 writel(addr >> (8 * alen), &zynq_i2c->data);
208 /* Wait for the address to be sent */
209 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
210 /* Release the bus */
211 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
214 debug("Device acked address\n");
217 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
218 ZYNQ_I2C_CONTROL_RW);
219 /* Start reading data */
220 writel(dev, &zynq_i2c->address);
221 writel(length, &zynq_i2c->transfer_size);
225 status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
226 ZYNQ_I2C_INTERRUPT_DATA);
228 /* Release the bus */
229 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
232 debug("Read %d bytes\n",
233 length - readl(&zynq_i2c->transfer_size));
234 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
235 *(cur_data++) = readl(&zynq_i2c->data);
236 } while (readl(&zynq_i2c->transfer_size) != 0);
237 /* All done... release the bus */
238 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
241 zynq_i2c_debug_status(zynq_i2c);
247 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
248 * Begin write, send address byte(s), send data bytes, end.
250 static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
251 int alen, u8 *data, int length)
254 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
256 /* Write the register address */
257 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
258 ZYNQ_I2C_CONTROL_HOLD);
259 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
260 writel(0xFF, &zynq_i2c->interrupt_status);
261 writel(dev, &zynq_i2c->address);
264 writel(addr >> (8 * alen), &zynq_i2c->data);
265 /* Start the tranfer */
266 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
267 /* Release the bus */
268 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
271 debug("Device acked address\n");
275 writel(*(cur_data++), &zynq_i2c->data);
276 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
277 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
278 /* Release the bus */
279 clrbits_le32(&zynq_i2c->control,
280 ZYNQ_I2C_CONTROL_HOLD);
286 /* All done... release the bus */
287 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
288 /* Wait for the address and data to be sent */
289 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
294 static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
297 if (speed != 1000000)
303 #ifdef CONFIG_ZYNQ_I2C0
304 U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
305 zynq_i2c_write, zynq_i2c_set_bus_speed,
306 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
309 #ifdef CONFIG_ZYNQ_I2C1
310 U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
311 zynq_i2c_write, zynq_i2c_set_bus_speed,
312 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,