git.sur5r.net Git - u-boot/blob - drivers/i2c/zynq_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for the Zynq-7000 PS I2C controller
   4  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   5  *
   6  * Author: Joe Hershberger <joe.hershberger@ni.com>
   7  * Copyright (c) 2012 Joe Hershberger.
   8  *
   9  * Copyright (c) 2012-2013 Xilinx, Michal Simek
  10  *
  11  * NOTE: This driver should be converted to driver model before June 2017.
  12  * Please see doc/driver-model/i2c-howto.txt for instructions.
  13  */
  14
  15 #include <common.h>
  16 #include <asm/io.h>
  17 #include <i2c.h>
  18 #include <linux/errno.h>
  19 #include <asm/arch/hardware.h>
  20
  21 /* i2c register set */
  22 struct zynq_i2c_registers {
  23         u32 control;
  24         u32 status;
  25         u32 address;
  26         u32 data;
  27         u32 interrupt_status;
  28         u32 transfer_size;
  29         u32 slave_mon_pause;
  30         u32 time_out;
  31         u32 interrupt_mask;
  32         u32 interrupt_enable;
  33         u32 interrupt_disable;
  34 };
  35
  36 /* Control register fields */
  37 #define ZYNQ_I2C_CONTROL_RW             0x00000001
  38 #define ZYNQ_I2C_CONTROL_MS             0x00000002
  39 #define ZYNQ_I2C_CONTROL_NEA            0x00000004
  40 #define ZYNQ_I2C_CONTROL_ACKEN          0x00000008
  41 #define ZYNQ_I2C_CONTROL_HOLD           0x00000010
  42 #define ZYNQ_I2C_CONTROL_SLVMON         0x00000020
  43 #define ZYNQ_I2C_CONTROL_CLR_FIFO       0x00000040
  44 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT    8
  45 #define ZYNQ_I2C_CONTROL_DIV_B_MASK     0x00003F00
  46 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT    14
  47 #define ZYNQ_I2C_CONTROL_DIV_A_MASK     0x0000C000
  48
  49 /* Status register values */
  50 #define ZYNQ_I2C_STATUS_RXDV    0x00000020
  51 #define ZYNQ_I2C_STATUS_TXDV    0x00000040
  52 #define ZYNQ_I2C_STATUS_RXOVF   0x00000080
  53 #define ZYNQ_I2C_STATUS_BA      0x00000100
  54
  55 /* Interrupt register fields */
  56 #define ZYNQ_I2C_INTERRUPT_COMP         0x00000001
  57 #define ZYNQ_I2C_INTERRUPT_DATA         0x00000002
  58 #define ZYNQ_I2C_INTERRUPT_NACK         0x00000004
  59 #define ZYNQ_I2C_INTERRUPT_TO           0x00000008
  60 #define ZYNQ_I2C_INTERRUPT_SLVRDY       0x00000010
  61 #define ZYNQ_I2C_INTERRUPT_RXOVF        0x00000020
  62 #define ZYNQ_I2C_INTERRUPT_TXOVF        0x00000040
  63 #define ZYNQ_I2C_INTERRUPT_RXUNF        0x00000080
  64 #define ZYNQ_I2C_INTERRUPT_ARBLOST      0x00000200
  65
  66 #define ZYNQ_I2C_FIFO_DEPTH             16
  67 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX     255 /* Controller transfer limit */
  68
  69 static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
  70 {
  71         return adap->hwadapnr ?
  72                 /* Zynq PS I2C1 */
  73                 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
  74                 /* Zynq PS I2C0 */
  75                 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
  76 }
  77
  78 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  79 static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
  80                           int slaveadd)
  81 {
  82         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
  83
  84         /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
  85         writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
  86                 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
  87
  88         /* Enable master mode, ack, and 7-bit addressing */
  89         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
  90                 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
  91 }
  92
  93 #ifdef DEBUG
  94 static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
  95 {
  96         int int_status;
  97         int status;
  98         int_status = readl(&zynq_i2c->interrupt_status);
  99
 100         status = readl(&zynq_i2c->status);
 101         if (int_status || status) {
 102                 debug("Status: ");
 103                 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
 104                         debug("COMP ");
 105                 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
 106                         debug("DATA ");
 107                 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
 108                         debug("NACK ");
 109                 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
 110                         debug("TO ");
 111                 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
 112                         debug("SLVRDY ");
 113                 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
 114                         debug("RXOVF ");
 115                 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
 116                         debug("TXOVF ");
 117                 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
 118                         debug("RXUNF ");
 119                 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
 120                         debug("ARBLOST ");
 121                 if (status & ZYNQ_I2C_STATUS_RXDV)
 122                         debug("RXDV ");
 123                 if (status & ZYNQ_I2C_STATUS_TXDV)
 124                         debug("TXDV ");
 125                 if (status & ZYNQ_I2C_STATUS_RXOVF)
 126                         debug("RXOVF ");
 127                 if (status & ZYNQ_I2C_STATUS_BA)
 128                         debug("BA ");
 129                 debug("TS%d ", readl(&zynq_i2c->transfer_size));
 130                 debug("\n");
 131         }
 132 }
 133 #endif
 134
 135 /* Wait for an interrupt */
 136 static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
 137 {
 138         int timeout, int_status;
 139
 140         for (timeout = 0; timeout < 100; timeout++) {
 141                 udelay(100);
 142                 int_status = readl(&zynq_i2c->interrupt_status);
 143                 if (int_status & mask)
 144                         break;
 145         }
 146 #ifdef DEBUG
 147         zynq_i2c_debug_status(zynq_i2c);
 148 #endif
 149         /* Clear interrupt status flags */
 150         writel(int_status & mask, &zynq_i2c->interrupt_status);
 151
 152         return int_status & mask;
 153 }
 154
 155 /*
 156  * I2C probe called by cmd_i2c when doing 'i2c probe'.
 157  * Begin read, nak data byte, end.
 158  */
 159 static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
 160 {
 161         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 162
 163         /* Attempt to read a byte */
 164         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 165                 ZYNQ_I2C_CONTROL_RW);
 166         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 167         writel(0xFF, &zynq_i2c->interrupt_status);
 168         writel(dev, &zynq_i2c->address);
 169         writel(1, &zynq_i2c->transfer_size);
 170
 171         return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 172                 ZYNQ_I2C_INTERRUPT_NACK) &
 173                 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 174 }
 175
 176 /*
 177  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 178  * Begin write, send address byte(s), begin read, receive data bytes, end.
 179  */
 180 static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 181                          int alen, u8 *data, int length)
 182 {
 183         u32 status;
 184         u32 i = 0;
 185         u8 *cur_data = data;
 186         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 187
 188         /* Check the hardware can handle the requested bytes */
 189         if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
 190                 return -EINVAL;
 191
 192         /* Write the register address */
 193         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 194                 ZYNQ_I2C_CONTROL_HOLD);
 195         /*
 196          * Temporarily disable restart (by clearing hold)
 197          * It doesn't seem to work.
 198          */
 199         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 200         writel(0xFF, &zynq_i2c->interrupt_status);
 201         if (alen) {
 202                 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 203                 writel(dev, &zynq_i2c->address);
 204                 while (alen--)
 205                         writel(addr >> (8 * alen), &zynq_i2c->data);
 206
 207                 /* Wait for the address to be sent */
 208                 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 209                         /* Release the bus */
 210                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 211                         return -ETIMEDOUT;
 212                 }
 213                 debug("Device acked address\n");
 214         }
 215
 216         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 217                 ZYNQ_I2C_CONTROL_RW);
 218         /* Start reading data */
 219         writel(dev, &zynq_i2c->address);
 220         writel(length, &zynq_i2c->transfer_size);
 221
 222         /* Wait for data */
 223         do {
 224                 status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 225                         ZYNQ_I2C_INTERRUPT_DATA);
 226                 if (!status) {
 227                         /* Release the bus */
 228                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 229                         return -ETIMEDOUT;
 230                 }
 231                 debug("Read %d bytes\n",
 232                       length - readl(&zynq_i2c->transfer_size));
 233                 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
 234                         *(cur_data++) = readl(&zynq_i2c->data);
 235         } while (readl(&zynq_i2c->transfer_size) != 0);
 236         /* All done... release the bus */
 237         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 238
 239 #ifdef DEBUG
 240         zynq_i2c_debug_status(zynq_i2c);
 241 #endif
 242         return 0;
 243 }
 244
 245 /*
 246  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 247  * Begin write, send address byte(s), send data bytes, end.
 248  */
 249 static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 250                           int alen, u8 *data, int length)
 251 {
 252         u8 *cur_data = data;
 253         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 254
 255         /* Write the register address */
 256         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 257                 ZYNQ_I2C_CONTROL_HOLD);
 258         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 259         writel(0xFF, &zynq_i2c->interrupt_status);
 260         writel(dev, &zynq_i2c->address);
 261         if (alen) {
 262                 while (alen--)
 263                         writel(addr >> (8 * alen), &zynq_i2c->data);
 264                 /* Start the tranfer */
 265                 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 266                         /* Release the bus */
 267                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 268                         return -ETIMEDOUT;
 269                 }
 270                 debug("Device acked address\n");
 271         }
 272
 273         while (length--) {
 274                 writel(*(cur_data++), &zynq_i2c->data);
 275                 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
 276                         if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 277                                 /* Release the bus */
 278                                 clrbits_le32(&zynq_i2c->control,
 279                                              ZYNQ_I2C_CONTROL_HOLD);
 280                                 return -ETIMEDOUT;
 281                         }
 282                 }
 283         }
 284
 285         /* All done... release the bus */
 286         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 287         /* Wait for the address and data to be sent */
 288         if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
 289                 return -ETIMEDOUT;
 290         return 0;
 291 }
 292
 293 static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
 294                         unsigned int speed)
 295 {
 296         if (speed != 1000000)
 297                 return -EINVAL;
 298
 299         return 0;
 300 }
 301
 302 #ifdef CONFIG_ZYNQ_I2C0
 303 U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 304                          zynq_i2c_write, zynq_i2c_set_bus_speed,
 305                          CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 306                          0)
 307 #endif
 308 #ifdef CONFIG_ZYNQ_I2C1
 309 U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 310                          zynq_i2c_write, zynq_i2c_set_bus_speed,
 311                          CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 312                          1)
 313 #endif