1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for the Zynq-7000 PS I2C controller
4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
6 * Author: Joe Hershberger <joe.hershberger@ni.com>
7 * Copyright (c) 2012 Joe Hershberger.
9 * Copyright (c) 2012-2013 Xilinx, Michal Simek
11 * NOTE: This driver should be converted to driver model before June 2017.
12 * Please see doc/driver-model/i2c-howto.txt for instructions.
18 #include <linux/errno.h>
19 #include <asm/arch/hardware.h>
21 /* i2c register set */
22 struct zynq_i2c_registers {
33 u32 interrupt_disable;
36 /* Control register fields */
37 #define ZYNQ_I2C_CONTROL_RW 0x00000001
38 #define ZYNQ_I2C_CONTROL_MS 0x00000002
39 #define ZYNQ_I2C_CONTROL_NEA 0x00000004
40 #define ZYNQ_I2C_CONTROL_ACKEN 0x00000008
41 #define ZYNQ_I2C_CONTROL_HOLD 0x00000010
42 #define ZYNQ_I2C_CONTROL_SLVMON 0x00000020
43 #define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040
44 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8
45 #define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00
46 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14
47 #define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000
49 /* Status register values */
50 #define ZYNQ_I2C_STATUS_RXDV 0x00000020
51 #define ZYNQ_I2C_STATUS_TXDV 0x00000040
52 #define ZYNQ_I2C_STATUS_RXOVF 0x00000080
53 #define ZYNQ_I2C_STATUS_BA 0x00000100
55 /* Interrupt register fields */
56 #define ZYNQ_I2C_INTERRUPT_COMP 0x00000001
57 #define ZYNQ_I2C_INTERRUPT_DATA 0x00000002
58 #define ZYNQ_I2C_INTERRUPT_NACK 0x00000004
59 #define ZYNQ_I2C_INTERRUPT_TO 0x00000008
60 #define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010
61 #define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020
62 #define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040
63 #define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
64 #define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
66 #define ZYNQ_I2C_FIFO_DEPTH 16
67 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
69 static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
71 return adap->hwadapnr ?
73 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
75 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
78 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
79 static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
82 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
84 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
85 writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
86 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
88 /* Enable master mode, ack, and 7-bit addressing */
89 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
90 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
94 static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
98 int_status = readl(&zynq_i2c->interrupt_status);
100 status = readl(&zynq_i2c->status);
101 if (int_status || status) {
103 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
105 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
107 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
109 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
111 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
115 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
117 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
119 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
121 if (status & ZYNQ_I2C_STATUS_RXDV)
123 if (status & ZYNQ_I2C_STATUS_TXDV)
125 if (status & ZYNQ_I2C_STATUS_RXOVF)
127 if (status & ZYNQ_I2C_STATUS_BA)
129 debug("TS%d ", readl(&zynq_i2c->transfer_size));
135 /* Wait for an interrupt */
136 static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
138 int timeout, int_status;
140 for (timeout = 0; timeout < 100; timeout++) {
142 int_status = readl(&zynq_i2c->interrupt_status);
143 if (int_status & mask)
147 zynq_i2c_debug_status(zynq_i2c);
149 /* Clear interrupt status flags */
150 writel(int_status & mask, &zynq_i2c->interrupt_status);
152 return int_status & mask;
156 * I2C probe called by cmd_i2c when doing 'i2c probe'.
157 * Begin read, nak data byte, end.
159 static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
161 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
163 /* Attempt to read a byte */
164 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
165 ZYNQ_I2C_CONTROL_RW);
166 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
167 writel(0xFF, &zynq_i2c->interrupt_status);
168 writel(dev, &zynq_i2c->address);
169 writel(1, &zynq_i2c->transfer_size);
171 return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
172 ZYNQ_I2C_INTERRUPT_NACK) &
173 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
177 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
178 * Begin write, send address byte(s), begin read, receive data bytes, end.
180 static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
181 int alen, u8 *data, int length)
186 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
188 /* Check the hardware can handle the requested bytes */
189 if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
192 /* Write the register address */
193 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
194 ZYNQ_I2C_CONTROL_HOLD);
196 * Temporarily disable restart (by clearing hold)
197 * It doesn't seem to work.
199 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
200 writel(0xFF, &zynq_i2c->interrupt_status);
202 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
203 writel(dev, &zynq_i2c->address);
205 writel(addr >> (8 * alen), &zynq_i2c->data);
207 /* Wait for the address to be sent */
208 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
209 /* Release the bus */
210 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
213 debug("Device acked address\n");
216 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
217 ZYNQ_I2C_CONTROL_RW);
218 /* Start reading data */
219 writel(dev, &zynq_i2c->address);
220 writel(length, &zynq_i2c->transfer_size);
224 status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
225 ZYNQ_I2C_INTERRUPT_DATA);
227 /* Release the bus */
228 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
231 debug("Read %d bytes\n",
232 length - readl(&zynq_i2c->transfer_size));
233 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
234 *(cur_data++) = readl(&zynq_i2c->data);
235 } while (readl(&zynq_i2c->transfer_size) != 0);
236 /* All done... release the bus */
237 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
240 zynq_i2c_debug_status(zynq_i2c);
246 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
247 * Begin write, send address byte(s), send data bytes, end.
249 static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
250 int alen, u8 *data, int length)
253 struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
255 /* Write the register address */
256 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
257 ZYNQ_I2C_CONTROL_HOLD);
258 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
259 writel(0xFF, &zynq_i2c->interrupt_status);
260 writel(dev, &zynq_i2c->address);
263 writel(addr >> (8 * alen), &zynq_i2c->data);
264 /* Start the tranfer */
265 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
266 /* Release the bus */
267 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
270 debug("Device acked address\n");
274 writel(*(cur_data++), &zynq_i2c->data);
275 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
276 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
277 /* Release the bus */
278 clrbits_le32(&zynq_i2c->control,
279 ZYNQ_I2C_CONTROL_HOLD);
285 /* All done... release the bus */
286 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
287 /* Wait for the address and data to be sent */
288 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
293 static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
296 if (speed != 1000000)
302 #ifdef CONFIG_ZYNQ_I2C0
303 U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
304 zynq_i2c_write, zynq_i2c_set_bus_speed,
305 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
308 #ifdef CONFIG_ZYNQ_I2C1
309 U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
310 zynq_i2c_write, zynq_i2c_set_bus_speed,
311 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,