2 * Driver for the Zynq-7000 PS I2C controller
3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * Author: Joe Hershberger <joe.hershberger@ni.com>
6 * Copyright (c) 2012 Joe Hershberger.
8 * Copyright (c) 2012-2013 Xilinx, Michal Simek
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <asm/errno.h>
33 #include <asm/arch/hardware.h>
35 /* i2c register set */
36 struct zynq_i2c_registers {
47 u32 interrupt_disable;
50 /* Control register fields */
51 #define ZYNQ_I2C_CONTROL_RW 0x00000001
52 #define ZYNQ_I2C_CONTROL_MS 0x00000002
53 #define ZYNQ_I2C_CONTROL_NEA 0x00000004
54 #define ZYNQ_I2C_CONTROL_ACKEN 0x00000008
55 #define ZYNQ_I2C_CONTROL_HOLD 0x00000010
56 #define ZYNQ_I2C_CONTROL_SLVMON 0x00000020
57 #define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040
58 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8
59 #define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00
60 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14
61 #define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000
63 /* Status register values */
64 #define ZYNQ_I2C_STATUS_RXDV 0x00000020
65 #define ZYNQ_I2C_STATUS_TXDV 0x00000040
66 #define ZYNQ_I2C_STATUS_RXOVF 0x00000080
67 #define ZYNQ_I2C_STATUS_BA 0x00000100
69 /* Interrupt register fields */
70 #define ZYNQ_I2C_INTERRUPT_COMP 0x00000001
71 #define ZYNQ_I2C_INTERRUPT_DATA 0x00000002
72 #define ZYNQ_I2C_INTERRUPT_NACK 0x00000004
73 #define ZYNQ_I2C_INTERRUPT_TO 0x00000008
74 #define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010
75 #define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020
76 #define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040
77 #define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
78 #define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
80 #define ZYNQ_I2C_FIFO_DEPTH 16
81 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
83 #if defined(CONFIG_ZYNQ_I2C0)
84 # define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0
86 # define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1
89 static struct zynq_i2c_registers *zynq_i2c =
90 (struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
92 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
93 void i2c_init(int requested_speed, int slaveadd)
95 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
96 writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
97 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
99 /* Enable master mode, ack, and 7-bit addressing */
100 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
101 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
105 static void zynq_i2c_debug_status(void)
109 int_status = readl(&zynq_i2c->interrupt_status);
111 status = readl(&zynq_i2c->status);
112 if (int_status || status) {
114 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
116 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
118 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
120 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
122 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
124 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
126 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
128 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
130 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
132 if (status & ZYNQ_I2C_STATUS_RXDV)
134 if (status & ZYNQ_I2C_STATUS_TXDV)
136 if (status & ZYNQ_I2C_STATUS_RXOVF)
138 if (status & ZYNQ_I2C_STATUS_BA)
140 debug("TS%d ", readl(&zynq_i2c->transfer_size));
146 /* Wait for an interrupt */
147 static u32 zynq_i2c_wait(u32 mask)
149 int timeout, int_status;
151 for (timeout = 0; timeout < 100; timeout++) {
153 int_status = readl(&zynq_i2c->interrupt_status);
154 if (int_status & mask)
158 zynq_i2c_debug_status();
160 /* Clear interrupt status flags */
161 writel(int_status & mask, &zynq_i2c->interrupt_status);
163 return int_status & mask;
167 * I2C probe called by cmd_i2c when doing 'i2c probe'.
168 * Begin read, nak data byte, end.
170 int i2c_probe(u8 dev)
172 /* Attempt to read a byte */
173 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
174 ZYNQ_I2C_CONTROL_RW);
175 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
176 writel(0xFF, &zynq_i2c->interrupt_status);
177 writel(dev, &zynq_i2c->address);
178 writel(1, &zynq_i2c->transfer_size);
180 return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
181 ZYNQ_I2C_INTERRUPT_NACK) &
182 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
186 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
187 * Begin write, send address byte(s), begin read, receive data bytes, end.
189 int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
195 /* Check the hardware can handle the requested bytes */
196 if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
199 /* Write the register address */
200 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
201 ZYNQ_I2C_CONTROL_HOLD);
203 * Temporarily disable restart (by clearing hold)
204 * It doesn't seem to work.
206 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
207 ZYNQ_I2C_CONTROL_HOLD);
208 writel(0xFF, &zynq_i2c->interrupt_status);
210 writel(addr >> (8*alen), &zynq_i2c->data);
211 writel(dev, &zynq_i2c->address);
213 /* Wait for the address to be sent */
214 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
215 /* Release the bus */
216 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
219 debug("Device acked address\n");
221 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
222 ZYNQ_I2C_CONTROL_RW);
223 /* Start reading data */
224 writel(dev, &zynq_i2c->address);
225 writel(length, &zynq_i2c->transfer_size);
229 status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
230 ZYNQ_I2C_INTERRUPT_DATA);
232 /* Release the bus */
233 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
236 debug("Read %d bytes\n",
237 length - readl(&zynq_i2c->transfer_size));
238 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
239 *(cur_data++) = readl(&zynq_i2c->data);
240 } while (readl(&zynq_i2c->transfer_size) != 0);
241 /* All done... release the bus */
242 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
245 zynq_i2c_debug_status();
251 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
252 * Begin write, send address byte(s), send data bytes, end.
254 int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
258 /* Write the register address */
259 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
260 ZYNQ_I2C_CONTROL_HOLD);
261 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
262 writel(0xFF, &zynq_i2c->interrupt_status);
264 writel(addr >> (8*alen), &zynq_i2c->data);
265 /* Start the tranfer */
266 writel(dev, &zynq_i2c->address);
267 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
268 /* Release the bus */
269 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
273 debug("Device acked address\n");
275 writel(*(cur_data++), &zynq_i2c->data);
276 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
277 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
278 /* Release the bus */
279 clrbits_le32(&zynq_i2c->control,
280 ZYNQ_I2C_CONTROL_HOLD);
286 /* All done... release the bus */
287 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
288 /* Wait for the address and data to be sent */
289 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP))
294 int i2c_set_bus_num(unsigned int bus)
296 /* Only support bus 0 */
302 unsigned int i2c_get_bus_num(void)
304 /* Only support bus 0 */