git.sur5r.net Git - u-boot/blob - drivers/i2c/zynq_i2c.c

   1 /*
   2  * Driver for the Zynq-7000 PS I2C controller
   3  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   4  *
   5  * Author: Joe Hershberger <joe.hershberger@ni.com>
   6  * Copyright (c) 2012 Joe Hershberger.
   7  *
   8  * Copyright (c) 2012-2013 Xilinx, Michal Simek
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <i2c.h>
  16 #include <asm/errno.h>
  17 #include <asm/arch/hardware.h>
  18
  19 /* i2c register set */
  20 struct zynq_i2c_registers {
  21         u32 control;
  22         u32 status;
  23         u32 address;
  24         u32 data;
  25         u32 interrupt_status;
  26         u32 transfer_size;
  27         u32 slave_mon_pause;
  28         u32 time_out;
  29         u32 interrupt_mask;
  30         u32 interrupt_enable;
  31         u32 interrupt_disable;
  32 };
  33
  34 /* Control register fields */
  35 #define ZYNQ_I2C_CONTROL_RW             0x00000001
  36 #define ZYNQ_I2C_CONTROL_MS             0x00000002
  37 #define ZYNQ_I2C_CONTROL_NEA            0x00000004
  38 #define ZYNQ_I2C_CONTROL_ACKEN          0x00000008
  39 #define ZYNQ_I2C_CONTROL_HOLD           0x00000010
  40 #define ZYNQ_I2C_CONTROL_SLVMON         0x00000020
  41 #define ZYNQ_I2C_CONTROL_CLR_FIFO       0x00000040
  42 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT    8
  43 #define ZYNQ_I2C_CONTROL_DIV_B_MASK     0x00003F00
  44 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT    14
  45 #define ZYNQ_I2C_CONTROL_DIV_A_MASK     0x0000C000
  46
  47 /* Status register values */
  48 #define ZYNQ_I2C_STATUS_RXDV    0x00000020
  49 #define ZYNQ_I2C_STATUS_TXDV    0x00000040
  50 #define ZYNQ_I2C_STATUS_RXOVF   0x00000080
  51 #define ZYNQ_I2C_STATUS_BA      0x00000100
  52
  53 /* Interrupt register fields */
  54 #define ZYNQ_I2C_INTERRUPT_COMP         0x00000001
  55 #define ZYNQ_I2C_INTERRUPT_DATA         0x00000002
  56 #define ZYNQ_I2C_INTERRUPT_NACK         0x00000004
  57 #define ZYNQ_I2C_INTERRUPT_TO           0x00000008
  58 #define ZYNQ_I2C_INTERRUPT_SLVRDY       0x00000010
  59 #define ZYNQ_I2C_INTERRUPT_RXOVF        0x00000020
  60 #define ZYNQ_I2C_INTERRUPT_TXOVF        0x00000040
  61 #define ZYNQ_I2C_INTERRUPT_RXUNF        0x00000080
  62 #define ZYNQ_I2C_INTERRUPT_ARBLOST      0x00000200
  63
  64 #define ZYNQ_I2C_FIFO_DEPTH             16
  65 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX     255 /* Controller transfer limit */
  66
  67 #if defined(CONFIG_ZYNQ_I2C0)
  68 # define ZYNQ_I2C_BASE  ZYNQ_I2C_BASEADDR0
  69 #else
  70 # define ZYNQ_I2C_BASE  ZYNQ_I2C_BASEADDR1
  71 #endif
  72
  73 static struct zynq_i2c_registers *zynq_i2c =
  74         (struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
  75
  76 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  77 static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
  78                           int slaveadd)
  79 {
  80         /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
  81         writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
  82                 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
  83
  84         /* Enable master mode, ack, and 7-bit addressing */
  85         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
  86                 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
  87 }
  88
  89 #ifdef DEBUG
  90 static void zynq_i2c_debug_status(void)
  91 {
  92         int int_status;
  93         int status;
  94         int_status = readl(&zynq_i2c->interrupt_status);
  95
  96         status = readl(&zynq_i2c->status);
  97         if (int_status || status) {
  98                 debug("Status: ");
  99                 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
 100                         debug("COMP ");
 101                 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
 102                         debug("DATA ");
 103                 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
 104                         debug("NACK ");
 105                 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
 106                         debug("TO ");
 107                 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
 108                         debug("SLVRDY ");
 109                 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
 110                         debug("RXOVF ");
 111                 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
 112                         debug("TXOVF ");
 113                 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
 114                         debug("RXUNF ");
 115                 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
 116                         debug("ARBLOST ");
 117                 if (status & ZYNQ_I2C_STATUS_RXDV)
 118                         debug("RXDV ");
 119                 if (status & ZYNQ_I2C_STATUS_TXDV)
 120                         debug("TXDV ");
 121                 if (status & ZYNQ_I2C_STATUS_RXOVF)
 122                         debug("RXOVF ");
 123                 if (status & ZYNQ_I2C_STATUS_BA)
 124                         debug("BA ");
 125                 debug("TS%d ", readl(&zynq_i2c->transfer_size));
 126                 debug("\n");
 127         }
 128 }
 129 #endif
 130
 131 /* Wait for an interrupt */
 132 static u32 zynq_i2c_wait(u32 mask)
 133 {
 134         int timeout, int_status;
 135
 136         for (timeout = 0; timeout < 100; timeout++) {
 137                 udelay(100);
 138                 int_status = readl(&zynq_i2c->interrupt_status);
 139                 if (int_status & mask)
 140                         break;
 141         }
 142 #ifdef DEBUG
 143         zynq_i2c_debug_status();
 144 #endif
 145         /* Clear interrupt status flags */
 146         writel(int_status & mask, &zynq_i2c->interrupt_status);
 147
 148         return int_status & mask;
 149 }
 150
 151 /*
 152  * I2C probe called by cmd_i2c when doing 'i2c probe'.
 153  * Begin read, nak data byte, end.
 154  */
 155 static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
 156 {
 157         /* Attempt to read a byte */
 158         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 159                 ZYNQ_I2C_CONTROL_RW);
 160         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 161         writel(0xFF, &zynq_i2c->interrupt_status);
 162         writel(dev, &zynq_i2c->address);
 163         writel(1, &zynq_i2c->transfer_size);
 164
 165         return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
 166                 ZYNQ_I2C_INTERRUPT_NACK) &
 167                 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 168 }
 169
 170 /*
 171  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 172  * Begin write, send address byte(s), begin read, receive data bytes, end.
 173  */
 174 static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 175                          int alen, u8 *data, int length)
 176 {
 177         u32 status;
 178         u32 i = 0;
 179         u8 *cur_data = data;
 180
 181         /* Check the hardware can handle the requested bytes */
 182         if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
 183                 return -EINVAL;
 184
 185         /* Write the register address */
 186         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 187                 ZYNQ_I2C_CONTROL_HOLD);
 188         /*
 189          * Temporarily disable restart (by clearing hold)
 190          * It doesn't seem to work.
 191          */
 192         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 193         writel(0xFF, &zynq_i2c->interrupt_status);
 194         if (alen) {
 195                 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 196                 writel(dev, &zynq_i2c->address);
 197                 while (alen--)
 198                         writel(addr >> (8 * alen), &zynq_i2c->data);
 199
 200                 /* Wait for the address to be sent */
 201                 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
 202                         /* Release the bus */
 203                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 204                         return -ETIMEDOUT;
 205                 }
 206                 debug("Device acked address\n");
 207         }
 208
 209         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 210                 ZYNQ_I2C_CONTROL_RW);
 211         /* Start reading data */
 212         writel(dev, &zynq_i2c->address);
 213         writel(length, &zynq_i2c->transfer_size);
 214
 215         /* Wait for data */
 216         do {
 217                 status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
 218                         ZYNQ_I2C_INTERRUPT_DATA);
 219                 if (!status) {
 220                         /* Release the bus */
 221                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 222                         return -ETIMEDOUT;
 223                 }
 224                 debug("Read %d bytes\n",
 225                       length - readl(&zynq_i2c->transfer_size));
 226                 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
 227                         *(cur_data++) = readl(&zynq_i2c->data);
 228         } while (readl(&zynq_i2c->transfer_size) != 0);
 229         /* All done... release the bus */
 230         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 231
 232 #ifdef DEBUG
 233         zynq_i2c_debug_status();
 234 #endif
 235         return 0;
 236 }
 237
 238 /*
 239  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 240  * Begin write, send address byte(s), send data bytes, end.
 241  */
 242 static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 243                           int alen, u8 *data, int length)
 244 {
 245         u8 *cur_data = data;
 246
 247         /* Write the register address */
 248         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 249                 ZYNQ_I2C_CONTROL_HOLD);
 250         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 251         writel(0xFF, &zynq_i2c->interrupt_status);
 252         writel(dev, &zynq_i2c->address);
 253         if (alen) {
 254                 while (alen--)
 255                         writel(addr >> (8 * alen), &zynq_i2c->data);
 256                 /* Start the tranfer */
 257                 if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
 258                         /* Release the bus */
 259                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 260                         return -ETIMEDOUT;
 261                 }
 262                 debug("Device acked address\n");
 263         }
 264
 265         while (length--) {
 266                 writel(*(cur_data++), &zynq_i2c->data);
 267                 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
 268                         if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
 269                                 /* Release the bus */
 270                                 clrbits_le32(&zynq_i2c->control,
 271                                              ZYNQ_I2C_CONTROL_HOLD);
 272                                 return -ETIMEDOUT;
 273                         }
 274                 }
 275         }
 276
 277         /* All done... release the bus */
 278         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 279         /* Wait for the address and data to be sent */
 280         if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP))
 281                 return -ETIMEDOUT;
 282         return 0;
 283 }
 284
 285 static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
 286                         unsigned int speed)
 287 {
 288         if (speed != 1000000)
 289                 return -EINVAL;
 290
 291         return 0;
 292 }
 293
 294 U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 295                          zynq_i2c_write, zynq_i2c_set_bus_speed,
 296                          CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 297                          0)