2 * INCA-IP internal switch ethernet driver.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30 && defined(CONFIG_INCA_IP_SWITCH)
34 #include <asm/inca-ip.h>
35 #include <asm/addrspace.h>
38 #define NUM_RX_DESC PKTBUFSRX
40 #define TOUT_LOOP 1000000
43 #define DELAY udelay(10000)
45 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
46 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
47 #define SW_WRITE_REG(reg, value) \
48 *((volatile u32*)reg) = (u32)value;\
50 *((volatile u32*)reg) = (u32)value;
52 #define SW_READ_REG(reg, value) \
53 value = (u32)*((volatile u32*)reg);\
55 value = (u32)*((volatile u32*)reg);
57 #define INCA_DMA_TX_POLLING_TIME 0x07
58 #define INCA_DMA_RX_POLLING_TIME 0x07
60 #define INCA_DMA_TX_HOLD 0x80000000
61 #define INCA_DMA_TX_EOP 0x40000000
62 #define INCA_DMA_TX_SOP 0x20000000
63 #define INCA_DMA_TX_ICPT 0x10000000
64 #define INCA_DMA_TX_IEOP 0x08000000
66 #define INCA_DMA_RX_C 0x80000000
67 #define INCA_DMA_RX_SOP 0x40000000
68 #define INCA_DMA_RX_EOP 0x20000000
78 volatile u32 offset :3;
79 volatile u32 reserved0 :4;
86 volatile u32 nextRxDescPtr;
88 volatile u32 RxDataPtr;
95 volatile u32 reserved3 :12;
102 } inca_rx_descriptor_t;
109 volatile u32 HOLD :1;
112 volatile u32 ICpt :1;
113 volatile u32 IEop :1;
114 volatile u32 reserved0 :5;
115 volatile u32 NBA :22;
121 volatile u32 nextTxDescPtr;
123 volatile u32 TxDataPtr;
126 volatile u32 reserved3 :31;
128 } inca_tx_descriptor_t;
131 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
132 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
134 static int tx_new, rx_new, tx_hold, rx_hold;
135 static int tx_old_hold = -1;
136 static int initialized = 0;
139 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
140 static int inca_switch_send(struct eth_device *dev, volatile void *packet,
142 static int inca_switch_recv(struct eth_device *dev);
143 static void inca_switch_halt(struct eth_device *dev);
144 static void inca_init_switch_chip(void);
145 static void inca_dma_init(void);
148 int inca_switch_initialize(bd_t * bis)
150 struct eth_device *dev;
153 printf("Entered inca_switch_initialize()\n");
156 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
157 printf("Failed to allocate memory\n");
160 memset(dev, 0, sizeof(*dev));
164 inca_init_switch_chip();
166 sprintf(dev->name, "INCA-IP Switch");
167 dev->init = inca_switch_init;
168 dev->halt = inca_switch_halt;
169 dev->send = inca_switch_send;
170 dev->recv = inca_switch_recv;
175 printf("Leaving inca_switch_initialize()\n");
182 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
189 printf("Entering inca_switch_init()\n");
194 wTmp = (u16)dev->enetaddr[0];
195 regValue = (wTmp << 8) | dev->enetaddr[1];
197 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
199 wTmp = (u16)dev->enetaddr[2];
200 regValue = (wTmp << 8) | dev->enetaddr[3];
201 regValue = regValue << 16;
202 wTmp = (u16)dev->enetaddr[4];
203 regValue |= (wTmp<<8) | dev->enetaddr[5];
205 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
207 /* Initialize the descriptor rings.
209 for (i = 0; i < NUM_RX_DESC; i++)
211 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
212 memset(rx_desc, 0, sizeof(rx_ring[i]));
214 /* Set maximum size of receive buffer.
216 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
218 /* Set the offset of the receive buffer. Zero means
219 * that the offset mechanism is not used.
221 rx_desc->params.field.offset = 0;
223 /* Check if it is the last descriptor.
225 if (i == (NUM_RX_DESC - 1)) {
226 /* Let the last descriptor point to the first
229 rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
231 /* Set the address of the next descriptor.
233 rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
236 rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
240 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
241 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
244 for (i = 0; i < NUM_TX_DESC; i++) {
245 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
247 memset(tx_desc, 0, sizeof(tx_ring[i]));
249 tx_desc->params.word = 0;
250 tx_desc->params.field.HOLD = 1;
253 /* Check if it is the last descriptor.
255 if (i == (NUM_TX_DESC - 1)) {
256 /* Let the last descriptor point to the
259 tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
261 /* Set the address of the next descriptor.
263 tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
269 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
271 printf("RX status = 0x%08X\n", v);
274 /* Writing to the FRDA of CHANNEL.
276 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
278 /* Writing to the COMMAND REG.
280 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0,
281 INCA_IP_DMA_DMA_RXCCR0_INIT);
285 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
287 printf("TX status = 0x%08X\n", v);
290 /* Writing to the FRDA of CHANNEL.
292 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
296 tx_hold = NUM_TX_DESC - 1;
297 rx_hold = NUM_RX_DESC - 1;
300 rx_ring[rx_hold].params.field.HOLD = 1;
302 /* enable spanning tree forwarding, enable the CPU port */
304 * CPS (CPU port status) 0x3 (forwarding)
305 * LPS (LAN port status) 0x3 (forwarding)
306 * PPS (PC port status) 0x3 (forwarding)
308 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
311 printf("Leaving inca_switch_init()\n");
318 static int inca_switch_send(struct eth_device *dev, volatile void *packet,
325 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
328 printf("Entered inca_switch_send()\n");
332 printf ("%s: bad packet size: %d\n", dev->name, length);
336 for(i = 0; tx_desc->C == 0; i++) {
337 if (i >= TOUT_LOOP) {
338 printf("%s: tx error buffer not ready\n", dev->name);
343 if (tx_old_hold >= 0) {
344 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
346 tx_old_hold = tx_hold;
348 tx_desc->params.word =
349 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
352 tx_desc->TxDataPtr = (u32)packet;
353 tx_desc->params.field.NBA = length;
355 KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
358 tx_new = (tx_new + 1) % NUM_TX_DESC;
362 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
365 command = INCA_IP_DMA_DMA_TXCCR0_HR;
368 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
371 printf("regValue = 0x%x\n", regValue);
373 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
376 for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
377 if (i >= TOUT_LOOP) {
378 printf("%s: tx buffer not ready\n", dev->name);
386 printf("Leaving inca_switch_send()\n");
392 static int inca_switch_recv(struct eth_device *dev)
395 inca_rx_descriptor_t * rx_desc;
398 printf("Entered inca_switch_recv()\n");
402 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
404 if (rx_desc->status.field.C == 0) {
409 rx_ring[rx_new].params.field.HOLD = 1;
412 if (! rx_desc->status.field.Eop) {
413 printf("Partly received packet!!!\n");
417 length = rx_desc->status.field.NBT;
418 rx_desc->status.word &=
419 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
423 for (i=0;i<length - 4;i++) {
424 if (i % 16 == 0) printf("\n%04x: ", i);
425 printf("%02X ", NetRxPackets[rx_new][i]);
433 printf("Received %d bytes\n", length);
435 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]),
439 printf("Zero length!!!\n");
444 KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
448 rx_new = (rx_new + 1) % NUM_RX_DESC;
452 printf("Leaving inca_switch_recv()\n");
459 static void inca_switch_halt(struct eth_device *dev)
462 printf("Entered inca_switch_halt()\n");
469 /* Disable forwarding to the CPU port.
471 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
473 /* Close RxDMA channel.
475 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
477 /* Close TxDMA channel.
479 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
484 printf("Leaving inca_switch_halt()\n");
489 static void inca_init_switch_chip(void)
493 /* To workaround a problem with collision counter
494 * (see Errata sheet).
496 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
497 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
500 /* init MDIO configuration:
501 * MDS (Poll speed): 0x01 (4ms)
504 * UEP (Use External PHY): 0x00 (Internal PHY is used)
505 * PS (Port Select): 0x00 (PT/UMM for LAN)
506 * PT (PHY Test): 0x00 (no test mode)
507 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
509 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
512 * SL (Auto Neg. Speed for LAN)
513 * SP (Auto Neg. Speed for PC)
514 * LL (Link Status for LAN)
515 * LP (Link Status for PC)
516 * DL (Duplex Status for LAN)
517 * DP (Duplex Status for PC)
518 * PL (Auto Neg. Pause Status for LAN)
519 * PP (Auto Neg. Pause Status for PC)
521 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
524 * RA (Request/Ack) 0x01 (Request)
525 * RW (Read/Write) 0x01 (Write)
527 * REG_ADDR 0x00 (PHY_BCR: basic control register)
529 * Reset - software reset
530 * LB (loop back) - normal
531 * SS (speed select) - 10 Mbit/s
532 * ANE (auto neg. enable) - enable
533 * PD (power down) - normal
534 * ISO (isolate) - normal
535 * RAN (restart auto neg.) - normal
536 * DM (duplex mode) - half duplex
537 * CT (collision test) - enable
539 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
542 * RA (Request/Ack) 0x01 (Request)
543 * RW (Read/Write) 0x01 (Write)
544 * PHY_ADDR 0x06 (LAN)
545 * REG_ADDR 0x00 (PHY_BCR: basic control register)
547 * Reset - software reset
548 * LB (loop back) - normal
549 * SS (speed select) - 10 Mbit/s
550 * ANE (auto neg. enable) - enable
551 * PD (power down) - normal
552 * ISO (isolate) - normal
553 * RAN (restart auto neg.) - normal
554 * DM (duplex mode) - half duplex
555 * CT (collision test) - enable
557 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
561 /* Make sure the CPU port is disabled for now. We
562 * don't want packets to get stacked for us until
563 * we enable DMA and are prepared to receive them.
565 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
567 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
569 /* CRC GEN is enabled.
571 regValue |= 0x00000200;
572 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
574 /* ADD TAG is disabled.
576 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
577 regValue &= ~0x00000002;
578 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
582 static void inca_dma_init(void)
584 /* Switch off all DMA channels.
586 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
587 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
589 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
590 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
591 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
593 /* Setup TX channel polling time.
595 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
597 /* Setup RX channel polling time.
599 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
601 /* ERRATA: write reset value into the DMA RX IMR register.
603 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
605 /* Just in case: disable all transmit interrupts also.
607 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
609 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
610 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);