2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Altera Sysid support"
20 Select this to enable a sysid for Altera devices. Please find
21 details on the "Embedded Peripherals IP User Guide" of Altera.
24 bool "Support for Atmel ATSHA204A module"
27 Enable support for I2C connected Atmel's ATSHA204A
28 CryptoAuthentication module found for example on the Turris Omnia
32 bool "Rockchip e-fuse support"
35 Enable (read-only) access for the e-fuse block found in Rockchip
36 SoCs: accesses can either be made using byte addressing and a length
37 or through child-nodes that are generated based on the e-fuse map
38 retrieved from the DTS.
40 This driver currently supports the RK3399 only, but can easily be
41 extended (by porting the read function from the Linux kernel sources)
42 to support other recent Rockchip devices.
45 bool "Enable crosec command"
48 Enable command-line access to the Chrome OS EC (Embedded
49 Controller). This provides the 'crosec' command which has
50 a number of sub-commands for performing EC tasks such as
51 updating its flash, accessing a small saved context area
52 and talking to the I2C bus behind the EC (if there is one).
55 bool "Enable Chrome OS EC"
57 Enable access to the Chrome OS EC. This is a separate
58 microcontroller typically available on a SPI bus on Chromebooks. It
59 provides access to the keyboard, some internal storage and may
60 control access to the battery and main PMIC depending on the
61 device. You can use the 'crosec' command to access it.
64 bool "Enable Chrome OS EC I2C driver"
67 Enable I2C access to the Chrome OS EC. This is used on older
68 ARM Chromebooks such as snow and spring before the standard bus
69 changed to SPI. The EC will accept commands across the I2C using
70 a special message protocol, and provide responses.
73 bool "Enable Chrome OS EC LPC driver"
76 Enable I2C access to the Chrome OS EC. This is used on x86
77 Chromebooks such as link and falco. The keyboard is provided
78 through a legacy port interface, so on x86 machines the main
79 function of the EC is power and thermal management.
81 config CROS_EC_SANDBOX
82 bool "Enable Chrome OS EC sandbox driver"
83 depends on CROS_EC && SANDBOX
85 Enable a sandbox emulation of the Chrome OS EC. This supports
86 keyboard (use the -l flag to enable the LCD), verified boot context,
87 EC flash read/write/erase support and a few other things. It is
88 enough to perform a Chrome OS verified boot on sandbox.
91 bool "Enable Chrome OS EC SPI driver"
94 Enable SPI access to the Chrome OS EC. This is used on newer
95 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
96 provides a faster and more robust interface than I2C but the bugs
100 bool "Enable support for DS4510 CPU supervisor"
102 Enable support for the Maxim DS4510 CPU supervisor. It has an
103 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
104 and a configurable timer for the supervisor function. The device is
108 bool "Enable FSL SEC_MON Driver"
110 Freescale Security Monitor block is responsible for monitoring
112 Security Monitor can be transitioned on any security failures,
113 like software violations or hardware security violations.
116 bool "Enable MXC OCOTP Driver"
118 If you say Y here, you will get support for the One Time
119 Programmable memory pages that are stored on the some
120 Freescale i.MX processors.
122 config NUVOTON_NCT6102D
123 bool "Enable Nuvoton NCT6102D Super I/O driver"
125 If you say Y here, you will get support for the Nuvoton
126 NCT6102D Super I/O driver. This can be used to enable or
127 disable the legacy UART, the watchdog or other devices
128 in the Nuvoton Super IO chips on X86 platforms.
131 bool "Enable power-sequencing drivers"
134 Power-sequencing drivers provide support for controlling power for
135 devices. They are typically referenced by a phandle from another
136 device. When the device is started up, its power sequence can be
140 bool "Enable power-sequencing drivers for SPL"
143 Power-sequencing drivers provide support for controlling power for
144 devices. They are typically referenced by a phandle from another
145 device. When the device is started up, its power sequence can be
149 bool "Enable PCA9551 LED driver"
151 Enable driver for PCA9551 LED controller. This controller
152 is connected via I2C. So I2C needs to be enabled.
154 config PCA9551_I2C_ADDR
155 hex "I2C address of PCA9551 LED controller"
156 depends on PCA9551_LED
159 The I2C address of the PCA9551 LED controller.
162 bool "Enable RCC driver for the STM32 SoC's family"
163 depends on STM32 && MISC
165 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
166 block) is responsible of the management of the clock and reset
168 This driver is similar to an MFD driver in the Linux kernel.
171 bool "Enable support for the Tegra CAR driver"
172 depends on TEGRA_NO_BPMP
174 The Tegra CAR (Clock and Reset Controller) is a HW module that
175 controls almost all clocks and resets in a Tegra SoC.
178 bool "Enable support for the Tegra186 BPMP driver"
181 The Tegra BPMP (Boot and Power Management Processor) is a separate
182 auxiliary CPU embedded into Tegra to perform power management work,
183 and controls related features such as clocks, resets, power domains,
184 PMIC I2C bus, etc. This driver provides the core low-level
185 communication path by which feature-specific drivers (such as clock)
186 can make requests to the BPMP. This driver is similar to an MFD
187 driver in the Linux kernel.
189 config WINBOND_W83627
190 bool "Enable Winbond Super I/O driver"
192 If you say Y here, you will get support for the Winbond
193 W83627 Super I/O driver. This can be used to enable the
194 legacy UART or other devices in the Winbond Super IO chips
200 Hidden option to enable QEMU fw_cfg interface. This will be selected by
201 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
204 bool "Enable driver for generic I2C-attached EEPROMs"
207 Enable a generic driver for EEPROMs attached via I2C.
210 config SPL_I2C_EEPROM
211 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
212 depends on MISC && SPL && SPL_DM
214 This option is an SPL-variant of the I2C_EEPROM option.
215 See the help of I2C_EEPROM for details.
217 config ZYNQ_GEM_I2C_MAC_OFFSET
218 hex "Set the I2C MAC offset"
221 Set the MAC offset for i2C.
225 config SYS_I2C_EEPROM_ADDR
226 hex "Chip address of the EEPROM device"
229 config SYS_I2C_EEPROM_BUS
230 int "I2C bus of the EEPROM device."
233 config SYS_EEPROM_SIZE
234 int "Size in bytes of the EEPROM device"
237 config SYS_EEPROM_PAGE_WRITE_BITS
238 int "Number of bits used to address bytes in a single page"
241 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
242 A 64 byte page, for example would require six bits.
244 config SYS_EEPROM_PAGE_WRITE_DELAY_MS
245 int "Number of milliseconds to delay between page writes"
248 config SYS_I2C_EEPROM_ADDR_LEN
249 int "Length in bytes of the EEPROM memory array address"
252 Note: This is NOT the chip address length!
254 config SYS_I2C_EEPROM_ADDR_OVERFLOW
255 hex "EEPROM Address Overflow"
258 EEPROM chips that implement "address overflow" are ones
259 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
260 address and the extra bits end up in the "chip address" bit
261 slots. This makes a 24WC08 (1Kbyte) chip look like four 256