3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Based on sc520cdp.c from rolo 1.6:
10 *----------------------------------------------------------------------
12 * Sysgo Real-Time Solutions GmbH
13 * Klein-Winternheim, Germany
14 *----------------------------------------------------------------------
24 /* ALI M5123 Logical device numbers:
37 ************************************************************
38 * Some access primitives for the ALi chip: *
39 ************************************************************
42 static void ali_write(u8 index, u8 value)
44 /* write an arbirary register */
45 outb(index, ALI_INDEX);
46 outb(value, ALI_DATA);
50 static int ali_read(u8 index)
52 outb(index, ALI_INDEX);
58 outb(0x51, ALI_INDEX); \
65 /* Select a logical device */
66 #define ALI_SELDEV(dev) \
70 void ali512x_init(void)
74 ali_write(0x02, 0x01); /* soft reset */
75 ali_write(0x03, 0x03); /* disable access to CIOs */
76 ali_write(0x22, 0x00); /* disable direct powerdown */
77 ali_write(0x23, 0x00); /* disable auto powerdown */
78 ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
83 void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
88 ali_write(0x30, enabled?1:0);
90 ali_write(0x60, io >> 8);
91 ali_write(0x61, io & 0xff);
93 ali_write(0x74, dma_channel);
95 /* AT mode, no drive swap */
96 ali_write(0xf0, 0x08);
97 ali_write(0xf1, 0x00);
98 ali_write(0xf2, 0xff);
99 ali_write(0xf4, 0x00);
105 void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
110 ali_write(0x30, enabled?1:0);
112 ali_write(0x60, io >> 8);
113 ali_write(0x61, io & 0xff);
114 ali_write(0x70, irq);
115 ali_write(0x74, dma_channel);
117 /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
118 ali_write(0xf0, 0xbc);
119 /* 12 MHz, Burst DMA in ECP */
120 ali_write(0xf1, 0x05);
126 void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
129 ALI_SELDEV(index?5:4);
131 ali_write(0x30, enabled?1:0);
133 ali_write(0x60, io >> 8);
134 ali_write(0x61, io & 0xff);
135 ali_write(0x70, irq);
137 ali_write(0xf0, 0x00);
138 ali_write(0xf1, 0x00);
140 /* huh? write 0xf2 twice - a typo in rolo
141 * or some secret ali errata? Who knows?
144 ali_write(0xf2, 0x00);
146 ali_write(0xf2, 0x0c);
152 void ali512x_set_uart2_irda(int enabled)
157 ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
162 void ali512x_set_rtc(int enabled, u16 io, u8 irq)
167 ali_write(0x30, enabled?1:0);
169 ali_write(0x60, io >> 8);
170 ali_write(0x61, io & 0xff);
171 ali_write(0x70, irq);
173 ali_write(0xf0, 0x00);
178 void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
183 ali_write(0x30, enabled?1:0);
185 ali_write(0x70, kbc_irq);
186 ali_write(0x72, mouse_irq);
188 ali_write(0xf0, 0x00);
196 * (This descripotsion is base on several incompete sources
197 * since I have not been able to obtain any datasheet for the device
198 * there may be some mis-understandings burried in here.
199 * -- Daniel daniel@omicron.se)
201 * There are 22 CIO pins numbered
206 * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
210 * CIO Pin Function Decription
211 * =======================================================
212 * CIO10 IRQIN1 Interrupt input 1?
213 * CIO11 IRQIN2 Interrupt input 2?
214 * CIO12 IRRX IrDa Receive
215 * CIO13 IRTX IrDa Transmit
216 * CIO14 P21 KBC P21 fucntion
217 * CIO15 P20 KBC P21 fucntion
218 * CIO16 I2C_CLK I2C Clock
219 * CIO17 I2C_DAT I2C Data
228 * CIO30 KBC_CLK Keybaord Clock
229 * CIO31 CS0J General Chip Select decoder CS0J
230 * CIO32 CS1J General Chip Select decoder CS1J
231 * CIO33 ALT_KCLK Alternative Keyboard Clock
232 * CIO34 ALT_KDAT Alternative Keyboard Data
233 * CIO35 ALT_MCLK Alternative Mouse Clock
234 * CIO36 ALT_MDAT Alternative Mouse Data
235 * CIO37 ALT_KBC Alternative KBC select
237 * The CIO use an indirect address scheme.
239 * Reigster 3 in the SIO is used to select the index and data
240 * port addresses where the CIO I/O registers show up.
241 * The function selection registers are accessible under
244 * SIO reigster 3 (CIO Address Selection) bit definitions:
245 * bit 7 CIO index and data registers enabled
246 * bit 1-0 CIO indirect registers port address select
247 * 0 index = 0xE0 data = 0xE1
248 * 1 index = 0xE2 data = 0xE3
249 * 2 index = 0xE4 data = 0xE5
250 * 3 index = 0xEA data = 0xEB
252 * There are three CIO I/O register accessed via CIO index port and CIO data port
253 * 0x01 CIO 10-17 data
254 * 0x02 CIO 20-25 data (bits 7-6 unused)
255 * 0x03 CIO 30-37 data
258 * The pin function is accessed through normal
259 * SIO registers, each register have the same format:
262 * 0 Input/output 1=input
263 * 1 Polarity of signal 1=inverted
265 * 3 Function (normal or special) 1=special
296 #define ALI_CIO_PORT_SEL 0x83
297 #define ALI_CIO_INDEX 0xea
298 #define ALI_CIO_DATA 0xeb
300 void ali512x_set_cio(int enabled)
307 ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */
309 ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
314 ali_write(0x30, enabled?1:0);
316 /* set all pins to input to start with */
317 for (i=0xe0;i<0xee;i++) {
321 for (i=0xf5;i<0xfe;i++) {
329 void ali512x_cio_function(int pin, int special, int inv, int input)
334 /* valid pins are 10-17, 20-25 and 30-37 */
335 if (pin >= 10 && pin <= 17) {
337 } else if (pin >= 20 && pin <= 25) {
339 } else if (pin >= 30 && pin <= 37) {
362 ali_write(addr, data);
367 void ali512x_cio_out(int pin, int value)
377 outb(reg, ALI_CIO_INDEX); /* select I/O register */
378 data = inb(ALI_CIO_DATA);
384 outb(data, ALI_CIO_DATA);
387 int ali512x_cio_in(int pin)
393 /* valid pins are 10-17, 20-25 and 30-37 */
398 outb(reg, ALI_CIO_INDEX); /* select I/O register */
399 data = inb(ALI_CIO_DATA);