2 * bcm2835 sdhost driver.
4 * The 2835 has two SD controllers: The Arasan sdhci controller
5 * (supported by the iproc driver) and a custom sdhost controller
6 * (supported by this driver).
8 * The sdhci controller supports both sdcard and sdio. The sdhost
9 * controller supports the sdcard only, but has better performance.
10 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
11 * the sdhost controller allows to use the sdhci controller for wifi
14 * The configuration is done by devicetree via pin muxing. Both
15 * SD controller are available on the same pins (2 pin groups = pin 22
16 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
17 * at the same time with different pin groups.
19 * This code was ported to U-Boot by
20 * Alexander Graf <agraf@suse.de>
21 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
22 * Phil Elwell <phil@raspberrypi.org>
23 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
25 * mmc-bcm2835.c by Gellert Weisz
26 * which is, in turn, based on
27 * sdhci-bcm2708.c by Broadcom
28 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
29 * sdhci.c and sdhci-pci.c by Pierre Ossman
31 * SPDX-License-Identifier: GPL-2.0
37 #include <asm/arch/msg.h>
38 #include <asm/arch/mbox.h>
39 #include <asm/unaligned.h>
40 #include <linux/compat.h>
42 #include <linux/iopoll.h>
43 #include <linux/sizes.h>
44 #include <mach/gpio.h>
45 #include <power/regulator.h>
47 #define msleep(a) udelay(a * 1000)
49 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
50 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
51 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
52 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
53 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
54 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
55 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
56 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
57 #define SDHSTS 0x20 /* SD host status - 11 R/W */
58 #define SDVDD 0x30 /* SD card power control - 1 R/W */
59 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
60 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
61 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
62 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
63 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
65 #define SDCMD_NEW_FLAG 0x8000
66 #define SDCMD_FAIL_FLAG 0x4000
67 #define SDCMD_BUSYWAIT 0x800
68 #define SDCMD_NO_RESPONSE 0x400
69 #define SDCMD_LONG_RESPONSE 0x200
70 #define SDCMD_WRITE_CMD 0x80
71 #define SDCMD_READ_CMD 0x40
72 #define SDCMD_CMD_MASK 0x3f
74 #define SDCDIV_MAX_CDIV 0x7ff
76 #define SDHSTS_BUSY_IRPT 0x400
77 #define SDHSTS_BLOCK_IRPT 0x200
78 #define SDHSTS_SDIO_IRPT 0x100
79 #define SDHSTS_REW_TIME_OUT 0x80
80 #define SDHSTS_CMD_TIME_OUT 0x40
81 #define SDHSTS_CRC16_ERROR 0x20
82 #define SDHSTS_CRC7_ERROR 0x10
83 #define SDHSTS_FIFO_ERROR 0x08
84 #define SDHSTS_DATA_FLAG 0x01
86 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
89 SDHSTS_REW_TIME_OUT | \
90 SDHSTS_CMD_TIME_OUT | \
91 SDHSTS_CRC16_ERROR | \
95 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
96 SDHSTS_CRC16_ERROR | \
97 SDHSTS_REW_TIME_OUT | \
100 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
101 SDHSTS_TRANSFER_ERROR_MASK)
103 #define SDHCFG_BUSY_IRPT_EN BIT(10)
104 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
105 #define SDHCFG_SDIO_IRPT_EN BIT(5)
106 #define SDHCFG_DATA_IRPT_EN BIT(4)
107 #define SDHCFG_SLOW_CARD BIT(3)
108 #define SDHCFG_WIDE_EXT_BUS BIT(2)
109 #define SDHCFG_WIDE_INT_BUS BIT(1)
110 #define SDHCFG_REL_CMD_LINE BIT(0)
112 #define SDVDD_POWER_OFF 0
113 #define SDVDD_POWER_ON 1
115 #define SDEDM_FORCE_DATA_MODE BIT(19)
116 #define SDEDM_CLOCK_PULSE BIT(20)
117 #define SDEDM_BYPASS BIT(21)
119 #define SDEDM_FIFO_FILL_SHIFT 4
120 #define SDEDM_FIFO_FILL_MASK 0x1f
121 static u32 edm_fifo_fill(u32 edm)
123 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
126 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
127 #define SDEDM_READ_THRESHOLD_SHIFT 14
128 #define SDEDM_THRESHOLD_MASK 0x1f
130 #define SDEDM_FSM_MASK 0xf
131 #define SDEDM_FSM_IDENTMODE 0x0
132 #define SDEDM_FSM_DATAMODE 0x1
133 #define SDEDM_FSM_READDATA 0x2
134 #define SDEDM_FSM_WRITEDATA 0x3
135 #define SDEDM_FSM_READWAIT 0x4
136 #define SDEDM_FSM_READCRC 0x5
137 #define SDEDM_FSM_WRITECRC 0x6
138 #define SDEDM_FSM_WRITEWAIT1 0x7
139 #define SDEDM_FSM_POWERDOWN 0x8
140 #define SDEDM_FSM_POWERUP 0x9
141 #define SDEDM_FSM_WRITESTART1 0xa
142 #define SDEDM_FSM_WRITESTART2 0xb
143 #define SDEDM_FSM_GENPULSES 0xc
144 #define SDEDM_FSM_WRITEWAIT2 0xd
145 #define SDEDM_FSM_STARTPOWDOWN 0xf
147 #define SDDATA_FIFO_WORDS 16
149 #define FIFO_READ_THRESHOLD 4
150 #define FIFO_WRITE_THRESHOLD 4
151 #define SDDATA_FIFO_PIO_BURST 8
153 #define SDHST_TIMEOUT_MAX_USEC 100000
155 struct bcm2835_plat {
156 struct mmc_config cfg;
160 struct bcm2835_host {
161 void __iomem *ioaddr;
164 int clock; /* Current clock speed */
165 unsigned int max_clk; /* Max possible freq */
166 unsigned int blocks; /* remaining PIO blocks */
167 int irq; /* Device IRQ */
169 u32 ns_per_fifo_word;
171 /* cached registers */
175 struct mmc_cmd *cmd; /* Current command */
176 struct mmc_data *data; /* Current data request */
177 bool data_complete:1;/* Data finished before cmd */
178 bool use_busy:1; /* Wait for busy interrupt */
179 bool wait_data_complete:1; /* Wait for data */
181 /* for threaded irq handler */
188 struct bcm2835_plat *plat;
191 static void bcm2835_dumpregs(struct bcm2835_host *host)
193 dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
194 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
195 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
196 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
197 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
198 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
199 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
200 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
201 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
202 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
203 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
204 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
205 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
206 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
207 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
208 dev_dbg(dev, "===========================================\n");
211 static void bcm2835_reset_internal(struct bcm2835_host *host)
215 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
216 writel(0, host->ioaddr + SDCMD);
217 writel(0, host->ioaddr + SDARG);
218 /* Set timeout to a big enough value so we don't hit it */
219 writel(0xf00000, host->ioaddr + SDTOUT);
220 writel(0, host->ioaddr + SDCDIV);
221 /* Clear status register */
222 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
223 writel(0, host->ioaddr + SDHCFG);
224 writel(0, host->ioaddr + SDHBCT);
225 writel(0, host->ioaddr + SDHBLC);
227 /* Limit fifo usage due to silicon bug */
228 temp = readl(host->ioaddr + SDEDM);
229 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
230 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
231 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
232 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
233 writel(temp, host->ioaddr + SDEDM);
234 /* Wait for FIFO threshold to populate */
236 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
237 /* Wait for all components to go through power on cycle */
240 writel(host->hcfg, host->ioaddr + SDHCFG);
241 writel(host->cdiv, host->ioaddr + SDCDIV);
244 static int bcm2835_finish_command(struct bcm2835_host *host);
246 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
251 alternate_idle = (host->data->flags & MMC_DATA_READ) ?
252 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
259 edm = readl(host->ioaddr + SDEDM);
260 fsm = edm & SDEDM_FSM_MASK;
262 if ((fsm == SDEDM_FSM_IDENTMODE) ||
263 (fsm == SDEDM_FSM_DATAMODE))
265 if (fsm == alternate_idle) {
266 writel(edm | SDEDM_FORCE_DATA_MODE,
267 host->ioaddr + SDEDM);
271 /* Error out after 100000 register reads (~1s) */
272 if (timediff++ == 100000) {
274 "wait_transfer_complete - still waiting after %d retries\n",
276 bcm2835_dumpregs(host);
282 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
284 struct mmc_data *data = host->data;
285 size_t blksize = data->blocksize;
290 if (blksize % sizeof(u32))
293 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
296 data->dest += blksize;
298 data->src += blksize;
300 copy_words = blksize / sizeof(u32);
303 * Copy all contents from/to the FIFO as far as it reaches,
304 * then wait for it to fill/empty again and rewind.
307 int burst_words, words;
310 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
311 edm = readl(host->ioaddr + SDEDM);
313 words = edm_fifo_fill(edm);
315 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
317 if (words < burst_words) {
318 int fsm_state = (edm & SDEDM_FSM_MASK);
321 (fsm_state != SDEDM_FSM_READDATA &&
322 fsm_state != SDEDM_FSM_READWAIT &&
323 fsm_state != SDEDM_FSM_READCRC)) ||
325 (fsm_state != SDEDM_FSM_WRITEDATA &&
326 fsm_state != SDEDM_FSM_WRITESTART1 &&
327 fsm_state != SDEDM_FSM_WRITESTART2))) {
328 hsts = readl(host->ioaddr + SDHSTS);
329 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
330 if (hsts & SDHSTS_ERROR_MASK)
335 } else if (words > copy_words) {
341 /* Copy current chunk to/from the FIFO */
344 *(buf++) = readl(host->ioaddr + SDDATA);
346 writel(*(buf++), host->ioaddr + SDDATA);
354 static int bcm2835_transfer_pio(struct bcm2835_host *host)
360 is_read = (host->data->flags & MMC_DATA_READ) != 0;
361 ret = bcm2835_transfer_block_pio(host, is_read);
363 if (host->wait_data_complete)
364 bcm2835_wait_transfer_complete(host);
366 sdhsts = readl(host->ioaddr + SDHSTS);
367 if (sdhsts & (SDHSTS_CRC16_ERROR |
369 SDHSTS_FIFO_ERROR)) {
370 printf("%s transfer error - HSTS %08x\n",
371 is_read ? "read" : "write", sdhsts);
373 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
374 SDHSTS_REW_TIME_OUT))) {
375 printf("%s timeout error - HSTS %08x\n",
376 is_read ? "read" : "write", sdhsts);
383 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
385 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
388 host->hcfg = (host->hcfg & ~all_irqs) |
389 SDHCFG_DATA_IRPT_EN |
392 writel(host->hcfg, host->ioaddr + SDHCFG);
396 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
397 struct mmc_data *data)
405 host->wait_data_complete = cmd->cmdidx != MMC_CMD_READ_MULTIPLE_BLOCK;
406 host->data_complete = false;
409 host->blocks = data->blocks;
411 bcm2835_set_transfer_irqs(host);
413 writel(data->blocksize, host->ioaddr + SDHBCT);
414 writel(data->blocks, host->ioaddr + SDHBLC);
417 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
421 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
423 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
424 !(value & SDCMD_NEW_FLAG), timeout_us);
425 if (ret == -ETIMEDOUT)
426 printf("%s: timeout (%d us)\n", __func__, timeout_us);
431 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
432 struct mmc_data *data)
438 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
439 printf("unsupported response type!\n");
443 sdcmd = bcm2835_read_wait_sdcmd(host);
444 if (sdcmd & SDCMD_NEW_FLAG) {
445 printf("previous command never completed.\n");
446 bcm2835_dumpregs(host);
452 /* Clear any error flags */
453 sdhsts = readl(host->ioaddr + SDHSTS);
454 if (sdhsts & SDHSTS_ERROR_MASK)
455 writel(sdhsts, host->ioaddr + SDHSTS);
457 bcm2835_prepare_data(host, cmd, data);
459 writel(cmd->cmdarg, host->ioaddr + SDARG);
461 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
463 host->use_busy = false;
464 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
465 sdcmd |= SDCMD_NO_RESPONSE;
467 if (cmd->resp_type & MMC_RSP_136)
468 sdcmd |= SDCMD_LONG_RESPONSE;
469 if (cmd->resp_type & MMC_RSP_BUSY) {
470 sdcmd |= SDCMD_BUSYWAIT;
471 host->use_busy = true;
476 if (data->flags & MMC_DATA_WRITE)
477 sdcmd |= SDCMD_WRITE_CMD;
478 if (data->flags & MMC_DATA_READ)
479 sdcmd |= SDCMD_READ_CMD;
482 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
487 static int bcm2835_transfer_complete(struct bcm2835_host *host)
491 WARN_ON(!host->data_complete);
498 static void bcm2835_finish_data(struct bcm2835_host *host)
500 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
501 writel(host->hcfg, host->ioaddr + SDHCFG);
503 host->data_complete = true;
506 /* Data managed to finish before the
507 * command completed. Make sure we do
508 * things in the proper order.
510 dev_dbg(dev, "Finished early - HSTS %08x\n",
511 readl(host->ioaddr + SDHSTS));
513 bcm2835_transfer_complete(host);
517 static int bcm2835_finish_command(struct bcm2835_host *host)
519 struct mmc_cmd *cmd = host->cmd;
523 sdcmd = bcm2835_read_wait_sdcmd(host);
525 /* Check for errors */
526 if (sdcmd & SDCMD_NEW_FLAG) {
527 printf("command never completed.\n");
528 bcm2835_dumpregs(host);
530 } else if (sdcmd & SDCMD_FAIL_FLAG) {
531 u32 sdhsts = readl(host->ioaddr + SDHSTS);
533 /* Clear the errors */
534 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
536 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
537 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
538 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
541 printf("unexpected command %d error\n",
543 bcm2835_dumpregs(host);
551 if (cmd->resp_type & MMC_RSP_PRESENT) {
552 if (cmd->resp_type & MMC_RSP_136) {
555 for (i = 0; i < 4; i++) {
556 cmd->response[3 - i] =
557 readl(host->ioaddr + SDRSP0 + i * 4);
560 cmd->response[0] = readl(host->ioaddr + SDRSP0);
564 /* Processed actual command. */
566 if (host->data && host->data_complete)
567 ret = bcm2835_transfer_complete(host);
572 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
576 if (!(intmask & SDHSTS_ERROR_MASK))
582 printf("sdhost_busy_irq: intmask %08x\n", intmask);
583 if (intmask & SDHSTS_CRC7_ERROR) {
585 } else if (intmask & (SDHSTS_CRC16_ERROR |
586 SDHSTS_FIFO_ERROR)) {
588 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
591 bcm2835_dumpregs(host);
595 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
601 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
603 if (intmask & SDHSTS_REW_TIME_OUT)
607 printf("%s:%d %d\n", __func__, __LINE__, ret);
612 static void bcm2835_busy_irq(struct bcm2835_host *host)
614 if (WARN_ON(!host->cmd)) {
615 bcm2835_dumpregs(host);
619 if (WARN_ON(!host->use_busy)) {
620 bcm2835_dumpregs(host);
623 host->use_busy = false;
625 bcm2835_finish_command(host);
628 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
633 * There are no dedicated data/space available interrupt
634 * status bits, so it is necessary to use the single shared
635 * data/space available FIFO status bits. It is therefore not
636 * an error to get here when there is no data transfer in
642 ret = bcm2835_check_data_error(host, intmask);
646 if (host->data->flags & MMC_DATA_WRITE) {
647 /* Use the block interrupt for writes after the first block */
648 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
649 host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
650 writel(host->hcfg, host->ioaddr + SDHCFG);
651 bcm2835_transfer_pio(host);
653 bcm2835_transfer_pio(host);
655 if ((host->blocks == 0))
661 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
662 writel(host->hcfg, host->ioaddr + SDHCFG);
665 static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
669 if ((host->blocks == 0))
670 bcm2835_finish_data(host);
673 static void bcm2835_block_irq(struct bcm2835_host *host)
675 if (WARN_ON(!host->data)) {
676 bcm2835_dumpregs(host);
680 WARN_ON(!host->blocks);
681 if ((--host->blocks == 0))
682 bcm2835_finish_data(host);
684 bcm2835_transfer_pio(host);
687 static irqreturn_t bcm2835_irq(int irq, void *dev_id)
689 irqreturn_t result = IRQ_NONE;
690 struct bcm2835_host *host = dev_id;
693 intmask = readl(host->ioaddr + SDHSTS);
695 writel(SDHSTS_BUSY_IRPT |
699 host->ioaddr + SDHSTS);
701 if (intmask & SDHSTS_BLOCK_IRPT) {
702 bcm2835_check_data_error(host, intmask);
703 host->irq_block = true;
704 result = IRQ_WAKE_THREAD;
707 if (intmask & SDHSTS_BUSY_IRPT) {
708 if (!bcm2835_check_cmd_error(host, intmask)) {
709 host->irq_busy = true;
710 result = IRQ_WAKE_THREAD;
712 result = IRQ_HANDLED;
716 /* There is no true data interrupt status bit, so it is
717 * necessary to qualify the data flag with the interrupt
720 if ((intmask & SDHSTS_DATA_FLAG) &&
721 (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
722 bcm2835_data_irq(host, intmask);
723 host->irq_data = true;
724 result = IRQ_WAKE_THREAD;
730 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
732 struct bcm2835_host *host = dev_id;
734 if (host->irq_block) {
735 host->irq_block = false;
736 bcm2835_block_irq(host);
739 if (host->irq_busy) {
740 host->irq_busy = false;
741 bcm2835_busy_irq(host);
744 if (host->irq_data) {
745 host->irq_data = false;
746 bcm2835_data_threaded_irq(host);
752 static void bcm2835_irq_poll(struct bcm2835_host *host)
757 intmask = readl(host->ioaddr + SDHSTS);
758 if (intmask & (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT |
759 SDHSTS_SDIO_IRPT | SDHSTS_DATA_FLAG)) {
760 bcm2835_irq(0, host);
761 bcm2835_threaded_irq(0, host);
767 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
771 /* The SDCDIV register has 11 bits, and holds (div - 2). But
772 * in data mode the max is 50MHz wihout a minimum, and only
773 * the bottom 3 bits are used. Since the switch over is
774 * automatic (unless we have marked the card as slow...),
775 * chosen values have to make sense in both modes. Ident mode
776 * must be 100-400KHz, so can range check the requested
777 * clock. CMD15 must be used to return to data mode, so this
780 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
781 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
783 * 623->400KHz/27.8MHz
784 * reset value (507)->491159/50MHz
786 * BUT, the 3-bit clock divisor in data mode is too small if
787 * the core clock is higher than 250MHz, so instead use the
788 * SLOW_CARD configuration bit to force the use of the ident
789 * clock divisor at all times.
792 if (clock < 100000) {
793 /* Can't stop the clock, but make it as slow as possible
796 host->cdiv = SDCDIV_MAX_CDIV;
797 writel(host->cdiv, host->ioaddr + SDCDIV);
801 div = host->max_clk / clock;
804 if ((host->max_clk / div) > clock)
808 if (div > SDCDIV_MAX_CDIV)
809 div = SDCDIV_MAX_CDIV;
811 clock = host->max_clk / (div + 2);
812 host->mmc->clock = clock;
814 /* Calibrate some delays */
816 host->ns_per_fifo_word = (1000000000 / clock) *
817 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
820 writel(host->cdiv, host->ioaddr + SDCDIV);
822 /* Set the timeout to 500ms */
823 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
826 static inline int is_power_of_2(u64 x)
828 return !(x & (x - 1));
831 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
832 struct mmc_data *data)
834 struct bcm2835_host *host = dev_get_priv(dev);
838 if (data && !is_power_of_2(data->blocksize)) {
839 printf("unsupported block size (%d bytes)\n", data->blocksize);
845 edm = readl(host->ioaddr + SDEDM);
846 fsm = edm & SDEDM_FSM_MASK;
848 if ((fsm != SDEDM_FSM_IDENTMODE) &&
849 (fsm != SDEDM_FSM_DATAMODE) &&
850 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
851 printf("previous command (%d) not complete (EDM %08x)\n",
852 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
853 bcm2835_dumpregs(host);
862 ret = bcm2835_send_command(host, cmd, data);
863 if (!ret && !host->use_busy)
864 ret = bcm2835_finish_command(host);
867 /* Wait for completion of busy signal or data transfer */
868 while (host->use_busy || host->data)
869 bcm2835_irq_poll(host);
874 static int bcm2835_set_ios(struct udevice *dev)
876 struct bcm2835_host *host = dev_get_priv(dev);
877 struct mmc *mmc = mmc_get_mmc_dev(dev);
879 if (!mmc->clock || mmc->clock != host->clock) {
880 bcm2835_set_clock(host, mmc->clock);
881 host->clock = mmc->clock;
885 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
886 if (mmc->bus_width == 4)
887 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
889 host->hcfg |= SDHCFG_WIDE_INT_BUS;
891 /* Disable clever clock switching, to cope with fast core clocks */
892 host->hcfg |= SDHCFG_SLOW_CARD;
894 writel(host->hcfg, host->ioaddr + SDHCFG);
899 static void bcm2835_add_host(struct bcm2835_host *host)
901 struct mmc_config *cfg = &host->plat->cfg;
903 cfg->f_max = host->max_clk;
904 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
907 dev_dbg(dev, "f_max %d, f_min %d\n",
908 cfg->f_max, cfg->f_min);
910 /* host controller capabilities */
911 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
913 /* report supported voltage ranges */
914 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
916 /* Set interrupt enables */
917 host->hcfg = SDHCFG_BUSY_IRPT_EN;
919 bcm2835_reset_internal(host);
922 static int bcm2835_probe(struct udevice *dev)
924 struct bcm2835_plat *plat = dev_get_platdata(dev);
925 struct bcm2835_host *host = dev_get_priv(dev);
926 struct mmc *mmc = mmc_get_mmc_dev(dev);
927 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
932 upriv->mmc = &plat->mmc;
933 plat->cfg.name = dev->name;
935 host->phys_addr = devfdt_get_addr(dev);
936 if (host->phys_addr == FDT_ADDR_T_NONE)
939 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
943 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
945 bcm2835_add_host(host);
947 dev_dbg(dev, "%s -> OK\n", __func__);
952 static const struct udevice_id bcm2835_match[] = {
953 { .compatible = "brcm,bcm2835-sdhost" },
957 static const struct dm_mmc_ops bcm2835_ops = {
958 .send_cmd = bcm2835_send_cmd,
959 .set_ios = bcm2835_set_ios,
962 static int bcm2835_bind(struct udevice *dev)
964 struct bcm2835_plat *plat = dev_get_platdata(dev);
966 return mmc_bind(dev, &plat->mmc, &plat->cfg);
969 U_BOOT_DRIVER(bcm2835_sdhost) = {
970 .name = "bcm2835-sdhost",
972 .of_match = bcm2835_match,
973 .bind = bcm2835_bind,
974 .probe = bcm2835_probe,
975 .priv_auto_alloc_size = sizeof(struct bcm2835_host),
976 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),