]> git.sur5r.net Git - u-boot/blob - drivers/mmc/bfin_sdh.c
Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash
[u-boot] / drivers / mmc / bfin_sdh.c
1 /*
2  * Driver for Blackfin on-chip SDH controller
3  *
4  * Copyright (c) 2008-2009 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2 or later.
7  */
8
9 #include <common.h>
10 #include <malloc.h>
11 #include <part.h>
12 #include <mmc.h>
13
14 #include <asm/io.h>
15 #include <asm/errno.h>
16 #include <asm/byteorder.h>
17 #include <asm/blackfin.h>
18 #include <asm/portmux.h>
19 #include <asm/mach-common/bits/sdh.h>
20 #include <asm/mach-common/bits/dma.h>
21
22 #if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
23 # define bfin_read_SDH_PWR_CTL          bfin_read_RSI_PWR_CONTROL
24 # define bfin_write_SDH_PWR_CTL         bfin_write_RSI_PWR_CONTROL
25 # define bfin_read_SDH_CLK_CTL          bfin_read_RSI_CLK_CONTROL
26 # define bfin_write_SDH_CLK_CTL         bfin_write_RSI_CLK_CONTROL
27 # define bfin_write_SDH_ARGUMENT        bfin_write_RSI_ARGUMENT
28 # define bfin_write_SDH_COMMAND         bfin_write_RSI_COMMAND
29 # define bfin_read_SDH_RESPONSE0        bfin_read_RSI_RESPONSE0
30 # define bfin_read_SDH_RESPONSE1        bfin_read_RSI_RESPONSE1
31 # define bfin_read_SDH_RESPONSE2        bfin_read_RSI_RESPONSE2
32 # define bfin_read_SDH_RESPONSE3        bfin_read_RSI_RESPONSE3
33 # define bfin_write_SDH_DATA_TIMER      bfin_write_RSI_DATA_TIMER
34 # define bfin_write_SDH_DATA_LGTH       bfin_write_RSI_DATA_LGTH
35 # define bfin_read_SDH_DATA_CTL         bfin_read_RSI_DATA_CONTROL
36 # define bfin_write_SDH_DATA_CTL        bfin_write_RSI_DATA_CONTROL
37 # define bfin_read_SDH_STATUS           bfin_read_RSI_STATUS
38 # define bfin_write_SDH_STATUS_CLR      bfin_write_RSI_STATUSCL
39 # define bfin_read_SDH_CFG              bfin_read_RSI_CONFIG
40 # define bfin_write_SDH_CFG             bfin_write_RSI_CONFIG
41 # define bfin_write_DMA_START_ADDR      bfin_write_DMA4_START_ADDR
42 # define bfin_write_DMA_X_COUNT         bfin_write_DMA4_X_COUNT
43 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA4_X_MODIFY
44 # define bfin_write_DMA_CONFIG          bfin_write_DMA4_CONFIG
45 # define PORTMUX_PINS \
46         { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
47 #elif defined(__ADSPBF54x__)
48 # define bfin_write_DMA_START_ADDR      bfin_write_DMA22_START_ADDR
49 # define bfin_write_DMA_X_COUNT         bfin_write_DMA22_X_COUNT
50 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA22_X_MODIFY
51 # define bfin_write_DMA_CONFIG          bfin_write_DMA22_CONFIG
52 # define PORTMUX_PINS \
53         { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
54 #else
55 # error no support for this proc yet
56 #endif
57
58 static int
59 sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
60 {
61         unsigned int status, timeout;
62         int cmd = mmc_cmd->cmdidx;
63         int flags = mmc_cmd->resp_type;
64         int arg = mmc_cmd->cmdarg;
65         int ret;
66         u16 sdh_cmd;
67
68         sdh_cmd = cmd | CMD_E;
69         if (flags & MMC_RSP_PRESENT)
70                 sdh_cmd |= CMD_RSP;
71         if (flags & MMC_RSP_136)
72                 sdh_cmd |= CMD_L_RSP;
73
74         bfin_write_SDH_ARGUMENT(arg);
75         bfin_write_SDH_COMMAND(sdh_cmd);
76
77         /* wait for a while */
78         timeout = 0;
79         do {
80                 if (++timeout > 1000000) {
81                         status = CMD_TIME_OUT;
82                         break;
83                 }
84                 udelay(1);
85                 status = bfin_read_SDH_STATUS();
86         } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
87                 CMD_CRC_FAIL)));
88
89         if (flags & MMC_RSP_PRESENT) {
90                 mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
91                 if (flags & MMC_RSP_136) {
92                         mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
93                         mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
94                         mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
95                 }
96         }
97
98         if (status & CMD_TIME_OUT)
99                 ret = TIMEOUT;
100         else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
101                 ret = COMM_ERR;
102         else
103                 ret = 0;
104
105         bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
106                                 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
107
108         return ret;
109 }
110
111 /* set data for single block transfer */
112 static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
113 {
114         u16 data_ctl = 0;
115         u16 dma_cfg = 0;
116         int ret = 0;
117         unsigned long data_size = data->blocksize * data->blocks;
118
119         /* Don't support write yet. */
120         if (data->flags & MMC_DATA_WRITE)
121                 return UNUSABLE_ERR;
122         data_ctl |= ((ffs(data_size) - 1) << 4);
123         data_ctl |= DTX_DIR;
124         bfin_write_SDH_DATA_CTL(data_ctl);
125         dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
126
127         bfin_write_SDH_DATA_TIMER(-1);
128
129         blackfin_dcache_flush_invalidate_range(data->dest,
130                         data->dest + data_size);
131         /* configure DMA */
132         bfin_write_DMA_START_ADDR(data->dest);
133         bfin_write_DMA_X_COUNT(data_size / 4);
134         bfin_write_DMA_X_MODIFY(4);
135         bfin_write_DMA_CONFIG(dma_cfg);
136         bfin_write_SDH_DATA_LGTH(data_size);
137         /* kick off transfer */
138         bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
139
140         return ret;
141 }
142
143
144 static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
145                 struct mmc_data *data)
146 {
147         u32 status;
148         int ret = 0;
149
150         ret = sdh_send_cmd(mmc, cmd);
151         if (ret) {
152                 printf("sending CMD%d failed\n", cmd->cmdidx);
153                 return ret;
154         }
155         if (data) {
156                 ret = sdh_setup_data(mmc, data);
157                 do {
158                         udelay(1);
159                         status = bfin_read_SDH_STATUS();
160                 } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
161
162                 if (status & DAT_TIME_OUT) {
163                         bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
164                         ret |= TIMEOUT;
165                 } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
166                         bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
167                         ret |= COMM_ERR;
168                 } else
169                         bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
170
171                 if (ret) {
172                         printf("tranfering data failed\n");
173                         return ret;
174                 }
175         }
176         return 0;
177 }
178
179 static void sdh_set_clk(unsigned long clk)
180 {
181         unsigned long sys_clk;
182         unsigned long clk_div;
183         u16 clk_ctl = 0;
184
185         clk_ctl = bfin_read_SDH_CLK_CTL();
186         if (clk) {
187                 /* setting SD_CLK */
188                 sys_clk = get_sclk();
189                 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
190                 if (sys_clk % (2 * clk) == 0)
191                         clk_div = sys_clk / (2 * clk) - 1;
192                 else
193                         clk_div = sys_clk / (2 * clk);
194
195                 if (clk_div > 0xff)
196                         clk_div = 0xff;
197                 clk_ctl |= (clk_div & 0xff);
198                 clk_ctl |= CLK_E;
199                 bfin_write_SDH_CLK_CTL(clk_ctl);
200         } else
201                 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
202 }
203
204 static void bfin_sdh_set_ios(struct mmc *mmc)
205 {
206         u16 cfg = 0;
207         u16 clk_ctl = 0;
208
209         if (mmc->bus_width == 4) {
210                 cfg = bfin_read_SDH_CFG();
211                 cfg &= ~0x80;
212                 cfg |= 0x40;
213                 bfin_write_SDH_CFG(cfg);
214                 clk_ctl |= WIDE_BUS;
215         }
216         bfin_write_SDH_CLK_CTL(clk_ctl);
217         sdh_set_clk(mmc->clock);
218 }
219
220 static int bfin_sdh_init(struct mmc *mmc)
221 {
222         const unsigned short pins[] = PORTMUX_PINS;
223         u16 pwr_ctl = 0;
224
225         /* Initialize sdh controller */
226         peripheral_request_list(pins, "bfin_sdh");
227 #if defined(__ADSPBF54x__)
228         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
229 #endif
230         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
231         /* Disable card detect pin */
232         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
233
234         pwr_ctl |= ROD_CTL;
235         pwr_ctl |= PWR_ON;
236         bfin_write_SDH_PWR_CTL(pwr_ctl);
237         return 0;
238 }
239
240
241 int bfin_mmc_init(bd_t *bis)
242 {
243         struct mmc *mmc = NULL;
244
245         mmc = malloc(sizeof(struct mmc));
246
247         if (!mmc)
248                 return -ENOMEM;
249         sprintf(mmc->name, "Blackfin SDH");
250         mmc->send_cmd = bfin_sdh_request;
251         mmc->set_ios = bfin_sdh_set_ios;
252         mmc->init = bfin_sdh_init;
253         mmc->getcd = NULL;
254         mmc->host_caps = MMC_MODE_4BIT;
255
256         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
257         mmc->f_max = get_sclk();
258         mmc->f_min = mmc->f_max >> 9;
259
260         mmc->b_max = 0;
261
262         mmc_register(mmc);
263
264         return 0;
265 }