2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-generic/errno.h>
18 #define PAGE_SIZE 4096
20 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
22 unsigned long timeout = 1000;
25 dwmci_writel(host, DWMCI_CTRL, value);
28 ctrl = dwmci_readl(host, DWMCI_CTRL);
29 if (!(ctrl & DWMCI_RESET_ALL))
35 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
36 u32 desc0, u32 desc1, u32 desc2)
38 struct dwmci_idmac *desc = idmac;
43 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
46 static void dwmci_prepare_data(struct dwmci_host *host,
47 struct mmc_data *data,
48 struct dwmci_idmac *cur_idmac,
52 unsigned int i = 0, flags, cnt, blk_cnt;
53 ulong data_start, data_end;
56 blk_cnt = data->blocks;
58 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
60 data_start = (ulong)cur_idmac;
61 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
64 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
65 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
67 flags |= DWMCI_IDMAC_LD;
68 cnt = data->blocksize * blk_cnt;
70 cnt = data->blocksize * 8;
72 dwmci_set_idma_desc(cur_idmac, flags, cnt,
73 (ulong)bounce_buffer + (i * PAGE_SIZE));
82 data_end = (ulong)cur_idmac;
83 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
85 ctrl = dwmci_readl(host, DWMCI_CTRL);
86 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
87 dwmci_writel(host, DWMCI_CTRL, ctrl);
89 ctrl = dwmci_readl(host, DWMCI_BMOD);
90 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
91 dwmci_writel(host, DWMCI_BMOD, ctrl);
93 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
94 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
97 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
100 u32 timeout = 240000;
101 u32 mask, size, i, len = 0;
103 ulong start = get_timer(0);
104 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
105 RX_WMARK_SHIFT) + 1) * 2;
107 size = data->blocksize * data->blocks / 4;
108 if (data->flags == MMC_DATA_READ)
109 buf = (unsigned int *)data->dest;
111 buf = (unsigned int *)data->src;
114 mask = dwmci_readl(host, DWMCI_RINTSTS);
115 /* Error during data transfer. */
116 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
117 debug("%s: DATA ERROR!\n", __func__);
122 if (host->fifo_mode && size) {
123 if (data->flags == MMC_DATA_READ) {
124 if ((dwmci_readl(host, DWMCI_RINTSTS) &
125 DWMCI_INTMSK_RXDR)) {
126 len = dwmci_readl(host, DWMCI_STATUS);
127 len = (len >> DWMCI_FIFO_SHIFT) &
129 for (i = 0; i < len; i++)
131 dwmci_readl(host, DWMCI_DATA);
132 dwmci_writel(host, DWMCI_RINTSTS,
136 if ((dwmci_readl(host, DWMCI_RINTSTS) &
137 DWMCI_INTMSK_TXDR)) {
138 len = dwmci_readl(host, DWMCI_STATUS);
139 len = fifo_depth - ((len >>
142 for (i = 0; i < len; i++)
143 dwmci_writel(host, DWMCI_DATA,
145 dwmci_writel(host, DWMCI_RINTSTS,
149 size = size > len ? (size - len) : 0;
152 /* Data arrived correctly. */
153 if (mask & DWMCI_INTMSK_DTO) {
158 /* Check for timeout. */
159 if (get_timer(start) > timeout) {
160 debug("%s: Timeout waiting for data!\n",
167 dwmci_writel(host, DWMCI_RINTSTS, mask);
172 static int dwmci_set_transfer_mode(struct dwmci_host *host,
173 struct mmc_data *data)
177 mode = DWMCI_CMD_DATA_EXP;
178 if (data->flags & MMC_DATA_WRITE)
179 mode |= DWMCI_CMD_RW;
184 #ifdef CONFIG_DM_MMC_OPS
185 int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
186 struct mmc_data *data)
188 struct mmc *mmc = mmc_get_mmc_dev(dev);
190 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
191 struct mmc_data *data)
194 struct dwmci_host *host = mmc->priv;
195 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
196 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
197 int ret = 0, flags = 0, i;
198 unsigned int timeout = 100000;
201 ulong start = get_timer(0);
202 struct bounce_buffer bbstate;
204 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
205 if (get_timer(start) > timeout) {
206 debug("%s: Timeout on data busy\n", __func__);
211 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
214 if (host->fifo_mode) {
215 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
216 dwmci_writel(host, DWMCI_BYTCNT,
217 data->blocksize * data->blocks);
218 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
220 if (data->flags == MMC_DATA_READ) {
221 bounce_buffer_start(&bbstate, (void*)data->dest,
223 data->blocks, GEN_BB_WRITE);
225 bounce_buffer_start(&bbstate, (void*)data->src,
227 data->blocks, GEN_BB_READ);
229 dwmci_prepare_data(host, data, cur_idmac,
230 bbstate.bounce_buffer);
234 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
237 flags = dwmci_set_transfer_mode(host, data);
239 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
242 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
243 flags |= DWMCI_CMD_ABORT_STOP;
245 flags |= DWMCI_CMD_PRV_DAT_WAIT;
247 if (cmd->resp_type & MMC_RSP_PRESENT) {
248 flags |= DWMCI_CMD_RESP_EXP;
249 if (cmd->resp_type & MMC_RSP_136)
250 flags |= DWMCI_CMD_RESP_LENGTH;
253 if (cmd->resp_type & MMC_RSP_CRC)
254 flags |= DWMCI_CMD_CHECK_CRC;
256 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
258 debug("Sending CMD%d\n",cmd->cmdidx);
260 dwmci_writel(host, DWMCI_CMD, flags);
262 for (i = 0; i < retry; i++) {
263 mask = dwmci_readl(host, DWMCI_RINTSTS);
264 if (mask & DWMCI_INTMSK_CDONE) {
266 dwmci_writel(host, DWMCI_RINTSTS, mask);
272 debug("%s: Timeout.\n", __func__);
276 if (mask & DWMCI_INTMSK_RTO) {
278 * Timeout here is not necessarily fatal. (e)MMC cards
279 * will splat here when they receive CMD55 as they do
280 * not support this command and that is exactly the way
281 * to tell them apart from SD cards. Thus, this output
282 * below shall be debug(). eMMC cards also do not favor
283 * CMD8, please keep that in mind.
285 debug("%s: Response Timeout.\n", __func__);
287 } else if (mask & DWMCI_INTMSK_RE) {
288 debug("%s: Response Error.\n", __func__);
293 if (cmd->resp_type & MMC_RSP_PRESENT) {
294 if (cmd->resp_type & MMC_RSP_136) {
295 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
296 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
297 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
298 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
300 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
305 ret = dwmci_data_transfer(host, data);
307 /* only dma mode need it */
308 if (!host->fifo_mode) {
309 ctrl = dwmci_readl(host, DWMCI_CTRL);
310 ctrl &= ~(DWMCI_DMA_EN);
311 dwmci_writel(host, DWMCI_CTRL, ctrl);
312 bounce_buffer_stop(&bbstate);
321 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
327 if ((freq == host->clock) || (freq == 0))
330 * If host->get_mmc_clk isn't defined,
331 * then assume that host->bus_hz is source clock value.
332 * host->bus_hz should be set by user.
334 if (host->get_mmc_clk)
335 sclk = host->get_mmc_clk(host, freq);
336 else if (host->bus_hz)
339 debug("%s: Didn't get source clock value.\n", __func__);
344 div = 0; /* bypass mode */
346 div = DIV_ROUND_UP(sclk, 2 * freq);
348 dwmci_writel(host, DWMCI_CLKENA, 0);
349 dwmci_writel(host, DWMCI_CLKSRC, 0);
351 dwmci_writel(host, DWMCI_CLKDIV, div);
352 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
353 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
356 status = dwmci_readl(host, DWMCI_CMD);
358 debug("%s: Timeout!\n", __func__);
361 } while (status & DWMCI_CMD_START);
363 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
364 DWMCI_CLKEN_LOW_PWR);
366 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
367 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
371 status = dwmci_readl(host, DWMCI_CMD);
373 debug("%s: Timeout!\n", __func__);
376 } while (status & DWMCI_CMD_START);
383 #ifdef CONFIG_DM_MMC_OPS
384 int dwmci_set_ios(struct udevice *dev)
386 struct mmc *mmc = mmc_get_mmc_dev(dev);
388 static void dwmci_set_ios(struct mmc *mmc)
391 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
394 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
396 dwmci_setup_bus(host, mmc->clock);
397 switch (mmc->bus_width) {
399 ctype = DWMCI_CTYPE_8BIT;
402 ctype = DWMCI_CTYPE_4BIT;
405 ctype = DWMCI_CTYPE_1BIT;
409 dwmci_writel(host, DWMCI_CTYPE, ctype);
411 regs = dwmci_readl(host, DWMCI_UHS_REG);
413 regs |= DWMCI_DDR_MODE;
415 regs &= ~DWMCI_DDR_MODE;
417 dwmci_writel(host, DWMCI_UHS_REG, regs);
421 #ifdef CONFIG_DM_MMC_OPS
426 static int dwmci_init(struct mmc *mmc)
428 struct dwmci_host *host = mmc->priv;
430 if (host->board_init)
431 host->board_init(host);
433 dwmci_writel(host, DWMCI_PWREN, 1);
435 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
436 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
440 /* Enumerate at 400KHz */
441 dwmci_setup_bus(host, mmc->cfg->f_min);
443 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
444 dwmci_writel(host, DWMCI_INTMASK, 0);
446 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
448 dwmci_writel(host, DWMCI_IDINTEN, 0);
449 dwmci_writel(host, DWMCI_BMOD, 1);
451 if (!host->fifoth_val) {
454 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
455 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
456 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
457 TX_WMARK(fifo_size / 2);
459 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
461 dwmci_writel(host, DWMCI_CLKENA, 0);
462 dwmci_writel(host, DWMCI_CLKSRC, 0);
467 #ifdef CONFIG_DM_MMC_OPS
468 int dwmci_probe(struct udevice *dev)
470 struct mmc *mmc = mmc_get_mmc_dev(dev);
472 return dwmci_init(mmc);
475 const struct dm_mmc_ops dm_dwmci_ops = {
476 .send_cmd = dwmci_send_cmd,
477 .set_ios = dwmci_set_ios,
481 static const struct mmc_ops dwmci_ops = {
482 .send_cmd = dwmci_send_cmd,
483 .set_ios = dwmci_set_ios,
488 void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
489 uint caps, u32 max_clk, u32 min_clk)
492 #ifndef CONFIG_DM_MMC_OPS
493 cfg->ops = &dwmci_ops;
495 cfg->f_min = min_clk;
496 cfg->f_max = max_clk;
498 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
500 cfg->host_caps = caps;
503 cfg->host_caps |= MMC_MODE_8BIT;
504 cfg->host_caps &= ~MMC_MODE_4BIT;
506 cfg->host_caps |= MMC_MODE_4BIT;
507 cfg->host_caps &= ~MMC_MODE_8BIT;
509 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
511 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
515 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
517 return mmc_bind(dev, mmc, cfg);
520 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
522 dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
525 host->mmc = mmc_create(&host->cfg, host);
526 if (host->mmc == NULL)