2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 #include <asm-generic/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 uint mixctrl; /* For USDHC */
55 char reserved1[4]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddr; /* ADMA system address register */
62 uint clktunectrlstatus;
68 uint hostver; /* Host controller version register */
69 char reserved5[4]; /* reserved */
70 uint dmaerraddr; /* DMA error address register */
71 char reserved6[4]; /* reserved */
72 uint dmaerrattr; /* DMA error attribute register */
73 char reserved7[4]; /* reserved */
74 uint hostcapblt2; /* Host controller capabilities register 2 */
75 char reserved8[8]; /* reserved */
76 uint tcr; /* Tuning control register */
77 char reserved9[28]; /* reserved */
78 uint sddirctl; /* SD direction control register */
79 char reserved10[712];/* reserved */
80 uint scr; /* eSDHC control register */
84 * struct fsl_esdhc_priv
86 * @esdhc_regs: registers of the sdhc controller
87 * @sdhc_clk: Current clk of the sdhc controller
88 * @bus_width: bus width, 1bit, 4bit or 8bit
91 * Following is used when Driver Model is enabled for MMC
92 * @dev: pointer for the device
93 * @non_removable: 0: removable; 1: non-removable
94 * @wp_enable: 1: enable checking wp; 0: no check
95 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
96 * @cd_gpio: gpio for card detection
97 * @wp_gpio: gpio for write protection
99 struct fsl_esdhc_priv {
100 struct fsl_esdhc *esdhc_regs;
101 unsigned int sdhc_clk;
102 unsigned int bus_width;
103 struct mmc_config cfg;
109 #ifdef CONFIG_DM_GPIO
110 struct gpio_desc cd_gpio;
111 struct gpio_desc wp_gpio;
115 /* Return the XFERTYP flags for a given command and data packet */
116 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
121 xfertyp |= XFERTYP_DPSEL;
122 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
123 xfertyp |= XFERTYP_DMAEN;
125 if (data->blocks > 1) {
126 xfertyp |= XFERTYP_MSBSEL;
127 xfertyp |= XFERTYP_BCEN;
128 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
129 xfertyp |= XFERTYP_AC12EN;
133 if (data->flags & MMC_DATA_READ)
134 xfertyp |= XFERTYP_DTDSEL;
137 if (cmd->resp_type & MMC_RSP_CRC)
138 xfertyp |= XFERTYP_CCCEN;
139 if (cmd->resp_type & MMC_RSP_OPCODE)
140 xfertyp |= XFERTYP_CICEN;
141 if (cmd->resp_type & MMC_RSP_136)
142 xfertyp |= XFERTYP_RSPTYP_136;
143 else if (cmd->resp_type & MMC_RSP_BUSY)
144 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
145 else if (cmd->resp_type & MMC_RSP_PRESENT)
146 xfertyp |= XFERTYP_RSPTYP_48;
148 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
149 xfertyp |= XFERTYP_CMDTYP_ABORT;
151 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
154 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
156 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
159 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
161 struct fsl_esdhc_priv *priv = mmc->priv;
162 struct fsl_esdhc *regs = priv->esdhc_regs;
170 if (data->flags & MMC_DATA_READ) {
171 blocks = data->blocks;
174 timeout = PIO_TIMEOUT;
175 size = data->blocksize;
176 irqstat = esdhc_read32(®s->irqstat);
177 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
180 printf("\nData Read Failed in PIO Mode.");
183 while (size && (!(irqstat & IRQSTAT_TC))) {
184 udelay(100); /* Wait before last byte transfer complete */
185 irqstat = esdhc_read32(®s->irqstat);
186 databuf = in_le32(®s->datport);
187 *((uint *)buffer) = databuf;
194 blocks = data->blocks;
195 buffer = (char *)data->src;
197 timeout = PIO_TIMEOUT;
198 size = data->blocksize;
199 irqstat = esdhc_read32(®s->irqstat);
200 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
203 printf("\nData Write Failed in PIO Mode.");
206 while (size && (!(irqstat & IRQSTAT_TC))) {
207 udelay(100); /* Wait before last byte transfer complete */
208 databuf = *((uint *)buffer);
211 irqstat = esdhc_read32(®s->irqstat);
212 out_le32(®s->datport, databuf);
220 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
223 struct fsl_esdhc_priv *priv = mmc->priv;
224 struct fsl_esdhc *regs = priv->esdhc_regs;
225 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
230 wml_value = data->blocksize/4;
232 if (data->flags & MMC_DATA_READ) {
233 if (wml_value > WML_RD_WML_MAX)
234 wml_value = WML_RD_WML_MAX_VAL;
236 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
237 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
238 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
239 addr = virt_to_phys((void *)(data->dest));
240 if (upper_32_bits(addr))
241 printf("Error found for upper 32 bits\n");
243 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
245 esdhc_write32(®s->dsaddr, (u32)data->dest);
249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
250 flush_dcache_range((ulong)data->src,
251 (ulong)data->src+data->blocks
254 if (wml_value > WML_WR_WML_MAX)
255 wml_value = WML_WR_WML_MAX_VAL;
256 if (priv->wp_enable) {
257 if ((esdhc_read32(®s->prsstat) &
258 PRSSTAT_WPSPL) == 0) {
259 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
264 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
266 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
267 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
268 addr = virt_to_phys((void *)(data->src));
269 if (upper_32_bits(addr))
270 printf("Error found for upper 32 bits\n");
272 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
274 esdhc_write32(®s->dsaddr, (u32)data->src);
279 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
281 /* Calculate the timeout period for data transactions */
283 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
284 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
285 * So, Number of SD Clock cycles for 0.25sec should be minimum
286 * (SD Clock/sec * 0.25 sec) SD Clock cycles
287 * = (mmc->clock * 1/4) SD Clock cycles
289 * => (2^(timeout+13)) >= mmc->clock * 1/4
290 * Taking log2 both the sides
291 * => timeout + 13 >= log2(mmc->clock/4)
292 * Rounding up to next power of 2
293 * => timeout + 13 = log2(mmc->clock/4) + 1
294 * => timeout + 13 = fls(mmc->clock/4)
296 * However, the MMC spec "It is strongly recommended for hosts to
297 * implement more than 500ms timeout value even if the card
298 * indicates the 250ms maximum busy length." Even the previous
299 * value of 300ms is known to be insufficient for some cards.
301 * => timeout + 13 = fls(mmc->clock/2)
303 timeout = fls(mmc->clock/2);
312 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
313 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
317 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
320 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
325 static void check_and_invalidate_dcache_range
326 (struct mmc_cmd *cmd,
327 struct mmc_data *data) {
330 unsigned size = roundup(ARCH_DMA_MINALIGN,
331 data->blocks*data->blocksize);
332 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
335 addr = virt_to_phys((void *)(data->dest));
336 if (upper_32_bits(addr))
337 printf("Error found for upper 32 bits\n");
339 start = lower_32_bits(addr);
341 start = (unsigned)data->dest;
344 invalidate_dcache_range(start, end);
348 * Sends a command out on the bus. Takes the mmc pointer,
349 * a command pointer, and an optional data pointer.
352 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
357 struct fsl_esdhc_priv *priv = mmc->priv;
358 struct fsl_esdhc *regs = priv->esdhc_regs;
360 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
361 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
365 esdhc_write32(®s->irqstat, -1);
369 /* Wait for the bus to be idle */
370 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
371 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
374 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
377 /* Wait at least 8 SD clock cycles before the next command */
379 * Note: This is way more than 8 cycles, but 1ms seems to
380 * resolve timing issues with some cards
384 /* Set up for a data transfer if we have one */
386 err = esdhc_setup_data(mmc, data);
390 if (data->flags & MMC_DATA_READ)
391 check_and_invalidate_dcache_range(cmd, data);
394 /* Figure out the transfer arguments */
395 xfertyp = esdhc_xfertyp(cmd, data);
398 esdhc_write32(®s->irqsigen, 0);
400 /* Send the command */
401 esdhc_write32(®s->cmdarg, cmd->cmdarg);
402 #if defined(CONFIG_FSL_USDHC)
403 esdhc_write32(®s->mixctrl,
404 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
405 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
406 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
408 esdhc_write32(®s->xfertyp, xfertyp);
411 /* Wait for the command to complete */
412 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
415 irqstat = esdhc_read32(®s->irqstat);
417 if (irqstat & CMD_ERR) {
422 if (irqstat & IRQSTAT_CTOE) {
427 /* Switch voltage to 1.8V if CMD11 succeeded */
428 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
429 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
431 printf("Run CMD11 1.8V switch\n");
432 /* Sleep for 5 ms - max time for card to switch to 1.8V */
436 /* Workaround for ESDHC errata ENGcm03648 */
437 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
440 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
441 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
448 printf("Timeout waiting for DAT0 to go high!\n");
454 /* Copy the response to the response buffer */
455 if (cmd->resp_type & MMC_RSP_136) {
456 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
458 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
459 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
460 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
461 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
462 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
463 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
464 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
465 cmd->response[3] = (cmdrsp0 << 8);
467 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
469 /* Wait until all of the blocks are transferred */
471 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
472 esdhc_pio_read_write(mmc, data);
475 irqstat = esdhc_read32(®s->irqstat);
477 if (irqstat & IRQSTAT_DTOE) {
482 if (irqstat & DATA_ERR) {
486 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
489 * Need invalidate the dcache here again to avoid any
490 * cache-fill during the DMA operations such as the
491 * speculative pre-fetching etc.
493 if (data->flags & MMC_DATA_READ)
494 check_and_invalidate_dcache_range(cmd, data);
499 /* Reset CMD and DATA portions on error */
501 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
503 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
507 esdhc_write32(®s->sysctl,
508 esdhc_read32(®s->sysctl) |
510 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
514 /* If this was CMD11, then notify that power cycle is needed */
515 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
516 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
519 esdhc_write32(®s->irqstat, -1);
524 static void set_sysctl(struct mmc *mmc, uint clock)
532 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
533 struct fsl_esdhc_priv *priv = mmc->priv;
534 struct fsl_esdhc *regs = priv->esdhc_regs;
535 int sdhc_clk = priv->sdhc_clk;
538 if (clock < mmc->cfg->f_min)
539 clock = mmc->cfg->f_min;
541 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
544 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
550 clk = (pre_div << 8) | (div << 4);
552 #ifdef CONFIG_FSL_USDHC
553 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
555 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
558 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
562 #ifdef CONFIG_FSL_USDHC
563 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
565 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
570 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
571 static void esdhc_clock_control(struct mmc *mmc, bool enable)
573 struct fsl_esdhc_priv *priv = mmc->priv;
574 struct fsl_esdhc *regs = priv->esdhc_regs;
578 value = esdhc_read32(®s->sysctl);
581 value |= SYSCTL_CKEN;
583 value &= ~SYSCTL_CKEN;
585 esdhc_write32(®s->sysctl, value);
588 value = PRSSTAT_SDSTB;
589 while (!(esdhc_read32(®s->prsstat) & value)) {
591 printf("fsl_esdhc: Internal clock never stabilised.\n");
600 static int esdhc_set_ios(struct mmc *mmc)
602 struct fsl_esdhc_priv *priv = mmc->priv;
603 struct fsl_esdhc *regs = priv->esdhc_regs;
605 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
606 /* Select to use peripheral clock */
607 esdhc_clock_control(mmc, false);
608 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
609 esdhc_clock_control(mmc, true);
611 /* Set the clock speed */
612 set_sysctl(mmc, mmc->clock);
614 /* Set the bus width */
615 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
617 if (mmc->bus_width == 4)
618 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
619 else if (mmc->bus_width == 8)
620 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
625 static int esdhc_init(struct mmc *mmc)
627 struct fsl_esdhc_priv *priv = mmc->priv;
628 struct fsl_esdhc *regs = priv->esdhc_regs;
631 /* Reset the entire host controller */
632 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
634 /* Wait until the controller is available */
635 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
638 #if defined(CONFIG_FSL_USDHC)
639 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
640 esdhc_write32(®s->mmcboot, 0x0);
641 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
642 esdhc_write32(®s->mixctrl, 0x0);
643 esdhc_write32(®s->clktunectrlstatus, 0x0);
645 /* Put VEND_SPEC to default value */
646 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
648 /* Disable DLL_CTRL delay line */
649 esdhc_write32(®s->dllctrl, 0x0);
653 /* Enable cache snooping */
654 esdhc_write32(®s->scr, 0x00000040);
657 #ifndef CONFIG_FSL_USDHC
658 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
660 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
663 /* Set the initial clock speed */
664 mmc_set_clock(mmc, 400000);
666 /* Disable the BRR and BWR bits in IRQSTAT */
667 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
669 /* Put the PROCTL reg back to the default */
670 esdhc_write32(®s->proctl, PROCTL_INIT);
672 /* Set timout to the maximum value */
673 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
675 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
676 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
679 if (priv->vs18_enable)
680 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
685 static int esdhc_getcd(struct mmc *mmc)
687 struct fsl_esdhc_priv *priv = mmc->priv;
688 struct fsl_esdhc *regs = priv->esdhc_regs;
691 #ifdef CONFIG_ESDHC_DETECT_QUIRK
692 if (CONFIG_ESDHC_DETECT_QUIRK)
697 if (priv->non_removable)
699 #ifdef CONFIG_DM_GPIO
700 if (dm_gpio_is_valid(&priv->cd_gpio))
701 return dm_gpio_get_value(&priv->cd_gpio);
705 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
711 static void esdhc_reset(struct fsl_esdhc *regs)
713 unsigned long timeout = 100; /* wait max 100 ms */
715 /* reset the controller */
716 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
718 /* hardware clears the bit when it is done */
719 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
722 printf("MMC/SD: Reset never completed.\n");
725 static const struct mmc_ops esdhc_ops = {
726 .send_cmd = esdhc_send_cmd,
727 .set_ios = esdhc_set_ios,
729 .getcd = esdhc_getcd,
732 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
734 struct fsl_esdhc *regs;
736 u32 caps, voltage_caps;
741 regs = priv->esdhc_regs;
743 /* First reset the eSDHC controller */
746 #ifndef CONFIG_FSL_USDHC
747 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
748 | SYSCTL_IPGEN | SYSCTL_CKEN);
750 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
751 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
754 if (priv->vs18_enable)
755 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
757 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
758 memset(&priv->cfg, 0, sizeof(priv->cfg));
761 caps = esdhc_read32(®s->hostcapblt);
763 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
764 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
765 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
768 /* T4240 host controller capabilities register should have VS33 bit */
769 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
770 caps = caps | ESDHC_HOSTCAPBLT_VS33;
773 if (caps & ESDHC_HOSTCAPBLT_VS18)
774 voltage_caps |= MMC_VDD_165_195;
775 if (caps & ESDHC_HOSTCAPBLT_VS30)
776 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
777 if (caps & ESDHC_HOSTCAPBLT_VS33)
778 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
780 priv->cfg.name = "FSL_SDHC";
781 priv->cfg.ops = &esdhc_ops;
782 #ifdef CONFIG_SYS_SD_VOLTAGE
783 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
785 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
787 if ((priv->cfg.voltages & voltage_caps) == 0) {
788 printf("voltage not supported by controller\n");
792 if (priv->bus_width == 8)
793 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
794 else if (priv->bus_width == 4)
795 priv->cfg.host_caps = MMC_MODE_4BIT;
797 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
798 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
799 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
802 if (priv->bus_width > 0) {
803 if (priv->bus_width < 8)
804 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
805 if (priv->bus_width < 4)
806 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
809 if (caps & ESDHC_HOSTCAPBLT_HSS)
810 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
812 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
813 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
814 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
817 priv->cfg.f_min = 400000;
818 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
820 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
822 mmc = mmc_create(&priv->cfg, priv);
831 #ifndef CONFIG_DM_MMC
832 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
833 struct fsl_esdhc_priv *priv)
838 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
839 priv->bus_width = cfg->max_bus_width;
840 priv->sdhc_clk = cfg->sdhc_clk;
841 priv->wp_enable = cfg->wp_enable;
842 priv->vs18_enable = cfg->vs18_enable;
847 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
849 struct fsl_esdhc_priv *priv;
855 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
859 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
861 debug("%s xlate failure\n", __func__);
866 ret = fsl_esdhc_init(priv);
868 debug("%s init failure\n", __func__);
876 int fsl_esdhc_mmc_init(bd_t *bis)
878 struct fsl_esdhc_cfg *cfg;
880 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
881 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
882 cfg->sdhc_clk = gd->arch.sdhc_clk;
883 return fsl_esdhc_initialize(bis, cfg);
887 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
888 void mmc_adapter_card_type_ident(void)
893 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
894 gd->arch.sdhc_adapter = card_id;
897 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
898 value = QIXIS_READ(brdcfg[5]);
899 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
900 QIXIS_WRITE(brdcfg[5], value);
902 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
903 value = QIXIS_READ(pwr_ctl[1]);
904 value |= QIXIS_EVDD_BY_SDHC_VS;
905 QIXIS_WRITE(pwr_ctl[1], value);
907 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
908 value = QIXIS_READ(brdcfg[5]);
909 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
910 QIXIS_WRITE(brdcfg[5], value);
912 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
914 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
916 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
918 case QIXIS_ESDHC_NO_ADAPTER:
926 #ifdef CONFIG_OF_LIBFDT
927 __weak int esdhc_status_fixup(void *blob, const char *compat)
929 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
930 if (!hwconfig("esdhc")) {
931 do_fixup_by_compat(blob, compat, "status", "disabled",
932 sizeof("disabled"), 1);
936 do_fixup_by_compat(blob, compat, "status", "okay",
941 void fdt_fixup_esdhc(void *blob, bd_t *bd)
943 const char *compat = "fsl,esdhc";
945 if (esdhc_status_fixup(blob, compat))
948 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
949 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
950 gd->arch.sdhc_clk, 1);
952 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
953 gd->arch.sdhc_clk, 1);
955 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
956 do_fixup_by_compat_u32(blob, compat, "adapter-type",
957 (u32)(gd->arch.sdhc_adapter), 1);
963 #include <asm/arch/clock.h>
964 __weak void init_clk_usdhc(u32 index)
968 static int fsl_esdhc_probe(struct udevice *dev)
970 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
971 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
972 const void *fdt = gd->fdt_blob;
973 int node = dev_of_offset(dev);
978 addr = devfdt_get_addr(dev);
979 if (addr == FDT_ADDR_T_NONE)
982 priv->esdhc_regs = (struct fsl_esdhc *)addr;
985 val = fdtdec_get_int(fdt, node, "bus-width", -1);
993 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
994 priv->non_removable = 1;
996 priv->non_removable = 0;
997 #ifdef CONFIG_DM_GPIO
998 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
999 0, &priv->cd_gpio, GPIOD_IS_IN);
1003 priv->wp_enable = 1;
1005 #ifdef CONFIG_DM_GPIO
1006 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
1007 &priv->wp_gpio, GPIOD_IS_IN);
1009 priv->wp_enable = 0;
1013 * Because lack of clk driver, if SDHC clk is not enabled,
1014 * need to enable it first before this driver is invoked.
1016 * we use MXC_ESDHC_CLK to get clk freq.
1017 * If one would like to make this function work,
1018 * the aliases should be provided in dts as this:
1026 * Then if your board only supports mmc2 and mmc3, but we can
1027 * correctly get the seq as 2 and 3, then let mxc_get_clock
1031 init_clk_usdhc(dev->seq);
1033 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1034 if (priv->sdhc_clk <= 0) {
1035 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1039 ret = fsl_esdhc_init(priv);
1041 dev_err(dev, "fsl_esdhc_init failure\n");
1045 upriv->mmc = priv->mmc;
1046 priv->mmc->dev = dev;
1051 static const struct udevice_id fsl_esdhc_ids[] = {
1052 { .compatible = "fsl,imx6ul-usdhc", },
1053 { .compatible = "fsl,imx6sx-usdhc", },
1054 { .compatible = "fsl,imx6sl-usdhc", },
1055 { .compatible = "fsl,imx6q-usdhc", },
1056 { .compatible = "fsl,imx7d-usdhc", },
1057 { .compatible = "fsl,imx7ulp-usdhc", },
1058 { .compatible = "fsl,esdhc", },
1062 U_BOOT_DRIVER(fsl_esdhc) = {
1063 .name = "fsl-esdhc-mmc",
1065 .of_match = fsl_esdhc_ids,
1066 .probe = fsl_esdhc_probe,
1067 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),