2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 uint dsaddr; /* SDMA system address register */
35 uint blkattr; /* Block attributes register */
36 uint cmdarg; /* Command argument register */
37 uint xfertyp; /* Transfer type register */
38 uint cmdrsp0; /* Command response 0 register */
39 uint cmdrsp1; /* Command response 1 register */
40 uint cmdrsp2; /* Command response 2 register */
41 uint cmdrsp3; /* Command response 3 register */
42 uint datport; /* Buffer data port register */
43 uint prsstat; /* Present state register */
44 uint proctl; /* Protocol control register */
45 uint sysctl; /* System Control Register */
46 uint irqstat; /* Interrupt status register */
47 uint irqstaten; /* Interrupt status enable register */
48 uint irqsigen; /* Interrupt signal enable register */
49 uint autoc12err; /* Auto CMD error status register */
50 uint hostcapblt; /* Host controller capabilities register */
51 uint wml; /* Watermark level register */
52 uint mixctrl; /* For USDHC */
53 char reserved1[4]; /* reserved */
54 uint fevt; /* Force event register */
55 uint admaes; /* ADMA error status register */
56 uint adsaddr; /* ADMA system address register */
57 char reserved2[100]; /* reserved */
58 uint vendorspec; /* Vendor Specific register */
59 char reserved3[56]; /* reserved */
60 uint hostver; /* Host controller version register */
61 char reserved4[4]; /* reserved */
62 uint dmaerraddr; /* DMA error address register */
63 char reserved5[4]; /* reserved */
64 uint dmaerrattr; /* DMA error attribute register */
65 char reserved6[4]; /* reserved */
66 uint hostcapblt2; /* Host controller capabilities register 2 */
67 char reserved7[8]; /* reserved */
68 uint tcr; /* Tuning control register */
69 char reserved8[28]; /* reserved */
70 uint sddirctl; /* SD direction control register */
71 char reserved9[712]; /* reserved */
72 uint scr; /* eSDHC control register */
75 /* Return the XFERTYP flags for a given command and data packet */
76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
81 xfertyp |= XFERTYP_DPSEL;
82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
83 xfertyp |= XFERTYP_DMAEN;
85 if (data->blocks > 1) {
86 xfertyp |= XFERTYP_MSBSEL;
87 xfertyp |= XFERTYP_BCEN;
88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
89 xfertyp |= XFERTYP_AC12EN;
93 if (data->flags & MMC_DATA_READ)
94 xfertyp |= XFERTYP_DTDSEL;
97 if (cmd->resp_type & MMC_RSP_CRC)
98 xfertyp |= XFERTYP_CCCEN;
99 if (cmd->resp_type & MMC_RSP_OPCODE)
100 xfertyp |= XFERTYP_CICEN;
101 if (cmd->resp_type & MMC_RSP_136)
102 xfertyp |= XFERTYP_RSPTYP_136;
103 else if (cmd->resp_type & MMC_RSP_BUSY)
104 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
105 else if (cmd->resp_type & MMC_RSP_PRESENT)
106 xfertyp |= XFERTYP_RSPTYP_48;
108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
109 defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
110 defined(CONFIG_PPC_T4160)
111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
112 xfertyp |= XFERTYP_CMDTYP_ABORT;
114 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
117 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
119 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
122 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
124 struct fsl_esdhc_cfg *cfg = mmc->priv;
125 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
133 if (data->flags & MMC_DATA_READ) {
134 blocks = data->blocks;
137 timeout = PIO_TIMEOUT;
138 size = data->blocksize;
139 irqstat = esdhc_read32(®s->irqstat);
140 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
143 printf("\nData Read Failed in PIO Mode.");
146 while (size && (!(irqstat & IRQSTAT_TC))) {
147 udelay(100); /* Wait before last byte transfer complete */
148 irqstat = esdhc_read32(®s->irqstat);
149 databuf = in_le32(®s->datport);
150 *((uint *)buffer) = databuf;
157 blocks = data->blocks;
158 buffer = (char *)data->src;
160 timeout = PIO_TIMEOUT;
161 size = data->blocksize;
162 irqstat = esdhc_read32(®s->irqstat);
163 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
166 printf("\nData Write Failed in PIO Mode.");
169 while (size && (!(irqstat & IRQSTAT_TC))) {
170 udelay(100); /* Wait before last byte transfer complete */
171 databuf = *((uint *)buffer);
174 irqstat = esdhc_read32(®s->irqstat);
175 out_le32(®s->datport, databuf);
183 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
186 struct fsl_esdhc_cfg *cfg = mmc->priv;
187 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
188 #ifdef CONFIG_FSL_LAYERSCAPE
193 wml_value = data->blocksize/4;
195 if (data->flags & MMC_DATA_READ) {
196 if (wml_value > WML_RD_WML_MAX)
197 wml_value = WML_RD_WML_MAX_VAL;
199 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
200 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
201 #ifdef CONFIG_FSL_LAYERSCAPE
202 addr = virt_to_phys((void *)(data->dest));
203 if (upper_32_bits(addr))
204 printf("Error found for upper 32 bits\n");
206 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
208 esdhc_write32(®s->dsaddr, (u32)data->dest);
212 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
213 flush_dcache_range((ulong)data->src,
214 (ulong)data->src+data->blocks
217 if (wml_value > WML_WR_WML_MAX)
218 wml_value = WML_WR_WML_MAX_VAL;
219 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
220 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
224 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
226 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
227 #ifdef CONFIG_FSL_LAYERSCAPE
228 addr = virt_to_phys((void *)(data->src));
229 if (upper_32_bits(addr))
230 printf("Error found for upper 32 bits\n");
232 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
234 esdhc_write32(®s->dsaddr, (u32)data->src);
239 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
241 /* Calculate the timeout period for data transactions */
243 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
244 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
245 * So, Number of SD Clock cycles for 0.25sec should be minimum
246 * (SD Clock/sec * 0.25 sec) SD Clock cycles
247 * = (mmc->clock * 1/4) SD Clock cycles
249 * => (2^(timeout+13)) >= mmc->clock * 1/4
250 * Taking log2 both the sides
251 * => timeout + 13 >= log2(mmc->clock/4)
252 * Rounding up to next power of 2
253 * => timeout + 13 = log2(mmc->clock/4) + 1
254 * => timeout + 13 = fls(mmc->clock/4)
256 timeout = fls(mmc->clock/4);
265 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
266 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
270 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
273 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
278 static void check_and_invalidate_dcache_range
279 (struct mmc_cmd *cmd,
280 struct mmc_data *data) {
281 #ifdef CONFIG_FSL_LAYERSCAPE
284 unsigned start = (unsigned)data->dest ;
286 unsigned size = roundup(ARCH_DMA_MINALIGN,
287 data->blocks*data->blocksize);
288 unsigned end = start+size ;
289 #ifdef CONFIG_FSL_LAYERSCAPE
292 addr = virt_to_phys((void *)(data->dest));
293 if (upper_32_bits(addr))
294 printf("Error found for upper 32 bits\n");
296 start = lower_32_bits(addr);
298 invalidate_dcache_range(start, end);
302 * Sends a command out on the bus. Takes the mmc pointer,
303 * a command pointer, and an optional data pointer.
306 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
311 struct fsl_esdhc_cfg *cfg = mmc->priv;
312 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
314 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
315 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
319 esdhc_write32(®s->irqstat, -1);
323 /* Wait for the bus to be idle */
324 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
325 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
328 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
331 /* Wait at least 8 SD clock cycles before the next command */
333 * Note: This is way more than 8 cycles, but 1ms seems to
334 * resolve timing issues with some cards
338 /* Set up for a data transfer if we have one */
340 err = esdhc_setup_data(mmc, data);
344 if (data->flags & MMC_DATA_READ)
345 check_and_invalidate_dcache_range(cmd, data);
348 /* Figure out the transfer arguments */
349 xfertyp = esdhc_xfertyp(cmd, data);
352 esdhc_write32(®s->irqsigen, 0);
354 /* Send the command */
355 esdhc_write32(®s->cmdarg, cmd->cmdarg);
356 #if defined(CONFIG_FSL_USDHC)
357 esdhc_write32(®s->mixctrl,
358 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
359 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
360 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
362 esdhc_write32(®s->xfertyp, xfertyp);
365 /* Wait for the command to complete */
366 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
369 irqstat = esdhc_read32(®s->irqstat);
371 if (irqstat & CMD_ERR) {
376 if (irqstat & IRQSTAT_CTOE) {
381 /* Switch voltage to 1.8V if CMD11 succeeded */
382 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
383 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
385 printf("Run CMD11 1.8V switch\n");
386 /* Sleep for 5 ms - max time for card to switch to 1.8V */
390 /* Workaround for ESDHC errata ENGcm03648 */
391 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
394 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
395 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
402 printf("Timeout waiting for DAT0 to go high!\n");
408 /* Copy the response to the response buffer */
409 if (cmd->resp_type & MMC_RSP_136) {
410 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
412 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
413 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
414 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
415 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
416 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
417 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
418 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
419 cmd->response[3] = (cmdrsp0 << 8);
421 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
423 /* Wait until all of the blocks are transferred */
425 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
426 esdhc_pio_read_write(mmc, data);
429 irqstat = esdhc_read32(®s->irqstat);
431 if (irqstat & IRQSTAT_DTOE) {
436 if (irqstat & DATA_ERR) {
440 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
443 * Need invalidate the dcache here again to avoid any
444 * cache-fill during the DMA operations such as the
445 * speculative pre-fetching etc.
447 if (data->flags & MMC_DATA_READ)
448 check_and_invalidate_dcache_range(cmd, data);
453 /* Reset CMD and DATA portions on error */
455 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
457 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
461 esdhc_write32(®s->sysctl,
462 esdhc_read32(®s->sysctl) |
464 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
468 /* If this was CMD11, then notify that power cycle is needed */
469 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
470 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
473 esdhc_write32(®s->irqstat, -1);
478 static void set_sysctl(struct mmc *mmc, uint clock)
481 struct fsl_esdhc_cfg *cfg = mmc->priv;
482 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
483 int sdhc_clk = cfg->sdhc_clk;
486 if (clock < mmc->cfg->f_min)
487 clock = mmc->cfg->f_min;
489 if (sdhc_clk / 16 > clock) {
490 for (pre_div = 2; pre_div < 256; pre_div *= 2)
491 if ((sdhc_clk / pre_div) <= (clock * 16))
496 for (div = 1; div <= 16; div++)
497 if ((sdhc_clk / (div * pre_div)) <= clock)
500 pre_div >>= mmc->ddr_mode ? 2 : 1;
503 clk = (pre_div << 8) | (div << 4);
505 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
507 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
511 clk = SYSCTL_PEREN | SYSCTL_CKEN;
513 esdhc_setbits32(®s->sysctl, clk);
516 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
517 static void esdhc_clock_control(struct mmc *mmc, bool enable)
519 struct fsl_esdhc_cfg *cfg = mmc->priv;
520 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
524 value = esdhc_read32(®s->sysctl);
527 value |= SYSCTL_CKEN;
529 value &= ~SYSCTL_CKEN;
531 esdhc_write32(®s->sysctl, value);
534 value = PRSSTAT_SDSTB;
535 while (!(esdhc_read32(®s->prsstat) & value)) {
537 printf("fsl_esdhc: Internal clock never stabilised.\n");
546 static void esdhc_set_ios(struct mmc *mmc)
548 struct fsl_esdhc_cfg *cfg = mmc->priv;
549 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
551 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
552 /* Select to use peripheral clock */
553 esdhc_clock_control(mmc, false);
554 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
555 esdhc_clock_control(mmc, true);
557 /* Set the clock speed */
558 set_sysctl(mmc, mmc->clock);
560 /* Set the bus width */
561 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
563 if (mmc->bus_width == 4)
564 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
565 else if (mmc->bus_width == 8)
566 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
570 static int esdhc_init(struct mmc *mmc)
572 struct fsl_esdhc_cfg *cfg = mmc->priv;
573 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
576 /* Reset the entire host controller */
577 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
579 /* Wait until the controller is available */
580 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
584 /* Enable cache snooping */
585 esdhc_write32(®s->scr, 0x00000040);
588 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
590 /* Set the initial clock speed */
591 mmc_set_clock(mmc, 400000);
593 /* Disable the BRR and BWR bits in IRQSTAT */
594 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
596 /* Put the PROCTL reg back to the default */
597 esdhc_write32(®s->proctl, PROCTL_INIT);
599 /* Set timout to the maximum value */
600 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
602 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
603 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
609 static int esdhc_getcd(struct mmc *mmc)
611 struct fsl_esdhc_cfg *cfg = mmc->priv;
612 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
615 #ifdef CONFIG_ESDHC_DETECT_QUIRK
616 if (CONFIG_ESDHC_DETECT_QUIRK)
619 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
625 static void esdhc_reset(struct fsl_esdhc *regs)
627 unsigned long timeout = 100; /* wait max 100 ms */
629 /* reset the controller */
630 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
632 /* hardware clears the bit when it is done */
633 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
636 printf("MMC/SD: Reset never completed.\n");
639 static const struct mmc_ops esdhc_ops = {
640 .send_cmd = esdhc_send_cmd,
641 .set_ios = esdhc_set_ios,
643 .getcd = esdhc_getcd,
646 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
648 struct fsl_esdhc *regs;
650 u32 caps, voltage_caps;
655 regs = (struct fsl_esdhc *)cfg->esdhc_base;
657 /* First reset the eSDHC controller */
660 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
661 | SYSCTL_IPGEN | SYSCTL_CKEN);
663 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
664 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
667 caps = esdhc_read32(®s->hostcapblt);
669 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
670 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
671 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
674 /* T4240 host controller capabilities register should have VS33 bit */
675 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
676 caps = caps | ESDHC_HOSTCAPBLT_VS33;
679 if (caps & ESDHC_HOSTCAPBLT_VS18)
680 voltage_caps |= MMC_VDD_165_195;
681 if (caps & ESDHC_HOSTCAPBLT_VS30)
682 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
683 if (caps & ESDHC_HOSTCAPBLT_VS33)
684 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
686 cfg->cfg.name = "FSL_SDHC";
687 cfg->cfg.ops = &esdhc_ops;
688 #ifdef CONFIG_SYS_SD_VOLTAGE
689 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
691 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
693 if ((cfg->cfg.voltages & voltage_caps) == 0) {
694 printf("voltage not supported by controller\n");
698 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
699 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
700 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
703 if (cfg->max_bus_width > 0) {
704 if (cfg->max_bus_width < 8)
705 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
706 if (cfg->max_bus_width < 4)
707 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
710 if (caps & ESDHC_HOSTCAPBLT_HSS)
711 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
713 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
714 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
715 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
718 cfg->cfg.f_min = 400000;
719 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
721 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
723 mmc = mmc_create(&cfg->cfg, cfg);
730 int fsl_esdhc_mmc_init(bd_t *bis)
732 struct fsl_esdhc_cfg *cfg;
734 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
735 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
736 cfg->sdhc_clk = gd->arch.sdhc_clk;
737 return fsl_esdhc_initialize(bis, cfg);
740 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
741 void mmc_adapter_card_type_ident(void)
746 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
747 gd->arch.sdhc_adapter = card_id;
750 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
751 value = QIXIS_READ(brdcfg[5]);
752 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
753 QIXIS_WRITE(brdcfg[5], value);
755 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
756 value = QIXIS_READ(pwr_ctl[1]);
757 value |= QIXIS_EVDD_BY_SDHC_VS;
758 QIXIS_WRITE(pwr_ctl[1], value);
760 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
761 value = QIXIS_READ(brdcfg[5]);
762 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
763 QIXIS_WRITE(brdcfg[5], value);
765 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
767 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
769 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
771 case QIXIS_ESDHC_NO_ADAPTER:
779 #ifdef CONFIG_OF_LIBFDT
780 void fdt_fixup_esdhc(void *blob, bd_t *bd)
782 const char *compat = "fsl,esdhc";
784 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
785 if (!hwconfig("esdhc")) {
786 do_fixup_by_compat(blob, compat, "status", "disabled",
792 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
793 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
794 gd->arch.sdhc_clk, 1);
796 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
797 gd->arch.sdhc_clk, 1);
799 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
800 do_fixup_by_compat_u32(blob, compat, "adapter-type",
801 (u32)(gd->arch.sdhc_adapter), 1);
803 do_fixup_by_compat(blob, compat, "status", "okay",