2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 #include <asm-generic/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 uint mixctrl; /* For USDHC */
55 char reserved1[4]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddr; /* ADMA system address register */
62 uint clktunectrlstatus;
68 uint hostver; /* Host controller version register */
69 char reserved5[4]; /* reserved */
70 uint dmaerraddr; /* DMA error address register */
71 char reserved6[4]; /* reserved */
72 uint dmaerrattr; /* DMA error attribute register */
73 char reserved7[4]; /* reserved */
74 uint hostcapblt2; /* Host controller capabilities register 2 */
75 char reserved8[8]; /* reserved */
76 uint tcr; /* Tuning control register */
77 char reserved9[28]; /* reserved */
78 uint sddirctl; /* SD direction control register */
79 char reserved10[712];/* reserved */
80 uint scr; /* eSDHC control register */
84 * struct fsl_esdhc_priv
86 * @esdhc_regs: registers of the sdhc controller
87 * @sdhc_clk: Current clk of the sdhc controller
88 * @bus_width: bus width, 1bit, 4bit or 8bit
91 * Following is used when Driver Model is enabled for MMC
92 * @dev: pointer for the device
93 * @non_removable: 0: removable; 1: non-removable
94 * @cd_gpio: gpio for card detection
96 struct fsl_esdhc_priv {
97 struct fsl_esdhc *esdhc_regs;
98 unsigned int sdhc_clk;
99 unsigned int bus_width;
100 struct mmc_config cfg;
104 struct gpio_desc cd_gpio;
107 /* Return the XFERTYP flags for a given command and data packet */
108 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
113 xfertyp |= XFERTYP_DPSEL;
114 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
115 xfertyp |= XFERTYP_DMAEN;
117 if (data->blocks > 1) {
118 xfertyp |= XFERTYP_MSBSEL;
119 xfertyp |= XFERTYP_BCEN;
120 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
121 xfertyp |= XFERTYP_AC12EN;
125 if (data->flags & MMC_DATA_READ)
126 xfertyp |= XFERTYP_DTDSEL;
129 if (cmd->resp_type & MMC_RSP_CRC)
130 xfertyp |= XFERTYP_CCCEN;
131 if (cmd->resp_type & MMC_RSP_OPCODE)
132 xfertyp |= XFERTYP_CICEN;
133 if (cmd->resp_type & MMC_RSP_136)
134 xfertyp |= XFERTYP_RSPTYP_136;
135 else if (cmd->resp_type & MMC_RSP_BUSY)
136 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
137 else if (cmd->resp_type & MMC_RSP_PRESENT)
138 xfertyp |= XFERTYP_RSPTYP_48;
140 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
141 xfertyp |= XFERTYP_CMDTYP_ABORT;
143 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
146 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
148 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
151 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
153 struct fsl_esdhc_priv *priv = mmc->priv;
154 struct fsl_esdhc *regs = priv->esdhc_regs;
162 if (data->flags & MMC_DATA_READ) {
163 blocks = data->blocks;
166 timeout = PIO_TIMEOUT;
167 size = data->blocksize;
168 irqstat = esdhc_read32(®s->irqstat);
169 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
172 printf("\nData Read Failed in PIO Mode.");
175 while (size && (!(irqstat & IRQSTAT_TC))) {
176 udelay(100); /* Wait before last byte transfer complete */
177 irqstat = esdhc_read32(®s->irqstat);
178 databuf = in_le32(®s->datport);
179 *((uint *)buffer) = databuf;
186 blocks = data->blocks;
187 buffer = (char *)data->src;
189 timeout = PIO_TIMEOUT;
190 size = data->blocksize;
191 irqstat = esdhc_read32(®s->irqstat);
192 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
195 printf("\nData Write Failed in PIO Mode.");
198 while (size && (!(irqstat & IRQSTAT_TC))) {
199 udelay(100); /* Wait before last byte transfer complete */
200 databuf = *((uint *)buffer);
203 irqstat = esdhc_read32(®s->irqstat);
204 out_le32(®s->datport, databuf);
212 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
215 struct fsl_esdhc_priv *priv = mmc->priv;
216 struct fsl_esdhc *regs = priv->esdhc_regs;
217 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
222 wml_value = data->blocksize/4;
224 if (data->flags & MMC_DATA_READ) {
225 if (wml_value > WML_RD_WML_MAX)
226 wml_value = WML_RD_WML_MAX_VAL;
228 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
229 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
230 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
231 addr = virt_to_phys((void *)(data->dest));
232 if (upper_32_bits(addr))
233 printf("Error found for upper 32 bits\n");
235 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
237 esdhc_write32(®s->dsaddr, (u32)data->dest);
241 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
242 flush_dcache_range((ulong)data->src,
243 (ulong)data->src+data->blocks
246 if (wml_value > WML_WR_WML_MAX)
247 wml_value = WML_WR_WML_MAX_VAL;
248 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
249 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
253 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
255 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
256 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
257 addr = virt_to_phys((void *)(data->src));
258 if (upper_32_bits(addr))
259 printf("Error found for upper 32 bits\n");
261 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
263 esdhc_write32(®s->dsaddr, (u32)data->src);
268 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
270 /* Calculate the timeout period for data transactions */
272 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
273 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
274 * So, Number of SD Clock cycles for 0.25sec should be minimum
275 * (SD Clock/sec * 0.25 sec) SD Clock cycles
276 * = (mmc->clock * 1/4) SD Clock cycles
278 * => (2^(timeout+13)) >= mmc->clock * 1/4
279 * Taking log2 both the sides
280 * => timeout + 13 >= log2(mmc->clock/4)
281 * Rounding up to next power of 2
282 * => timeout + 13 = log2(mmc->clock/4) + 1
283 * => timeout + 13 = fls(mmc->clock/4)
285 * However, the MMC spec "It is strongly recommended for hosts to
286 * implement more than 500ms timeout value even if the card
287 * indicates the 250ms maximum busy length." Even the previous
288 * value of 300ms is known to be insufficient for some cards.
290 * => timeout + 13 = fls(mmc->clock/2)
292 timeout = fls(mmc->clock/2);
301 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
302 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
306 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
309 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
314 static void check_and_invalidate_dcache_range
315 (struct mmc_cmd *cmd,
316 struct mmc_data *data) {
319 unsigned size = roundup(ARCH_DMA_MINALIGN,
320 data->blocks*data->blocksize);
321 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
324 addr = virt_to_phys((void *)(data->dest));
325 if (upper_32_bits(addr))
326 printf("Error found for upper 32 bits\n");
328 start = lower_32_bits(addr);
330 start = (unsigned)data->dest;
333 invalidate_dcache_range(start, end);
337 * Sends a command out on the bus. Takes the mmc pointer,
338 * a command pointer, and an optional data pointer.
341 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
346 struct fsl_esdhc_priv *priv = mmc->priv;
347 struct fsl_esdhc *regs = priv->esdhc_regs;
349 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
350 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
354 esdhc_write32(®s->irqstat, -1);
358 /* Wait for the bus to be idle */
359 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
360 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
363 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
366 /* Wait at least 8 SD clock cycles before the next command */
368 * Note: This is way more than 8 cycles, but 1ms seems to
369 * resolve timing issues with some cards
373 /* Set up for a data transfer if we have one */
375 err = esdhc_setup_data(mmc, data);
379 if (data->flags & MMC_DATA_READ)
380 check_and_invalidate_dcache_range(cmd, data);
383 /* Figure out the transfer arguments */
384 xfertyp = esdhc_xfertyp(cmd, data);
387 esdhc_write32(®s->irqsigen, 0);
389 /* Send the command */
390 esdhc_write32(®s->cmdarg, cmd->cmdarg);
391 #if defined(CONFIG_FSL_USDHC)
392 esdhc_write32(®s->mixctrl,
393 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
394 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
395 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
397 esdhc_write32(®s->xfertyp, xfertyp);
400 /* Wait for the command to complete */
401 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
404 irqstat = esdhc_read32(®s->irqstat);
406 if (irqstat & CMD_ERR) {
411 if (irqstat & IRQSTAT_CTOE) {
416 /* Switch voltage to 1.8V if CMD11 succeeded */
417 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
418 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
420 printf("Run CMD11 1.8V switch\n");
421 /* Sleep for 5 ms - max time for card to switch to 1.8V */
425 /* Workaround for ESDHC errata ENGcm03648 */
426 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
429 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
430 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
437 printf("Timeout waiting for DAT0 to go high!\n");
443 /* Copy the response to the response buffer */
444 if (cmd->resp_type & MMC_RSP_136) {
445 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
447 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
448 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
449 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
450 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
451 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
452 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
453 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
454 cmd->response[3] = (cmdrsp0 << 8);
456 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
458 /* Wait until all of the blocks are transferred */
460 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
461 esdhc_pio_read_write(mmc, data);
464 irqstat = esdhc_read32(®s->irqstat);
466 if (irqstat & IRQSTAT_DTOE) {
471 if (irqstat & DATA_ERR) {
475 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
478 * Need invalidate the dcache here again to avoid any
479 * cache-fill during the DMA operations such as the
480 * speculative pre-fetching etc.
482 if (data->flags & MMC_DATA_READ)
483 check_and_invalidate_dcache_range(cmd, data);
488 /* Reset CMD and DATA portions on error */
490 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
492 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
496 esdhc_write32(®s->sysctl,
497 esdhc_read32(®s->sysctl) |
499 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
503 /* If this was CMD11, then notify that power cycle is needed */
504 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
505 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
508 esdhc_write32(®s->irqstat, -1);
513 static void set_sysctl(struct mmc *mmc, uint clock)
516 struct fsl_esdhc_priv *priv = mmc->priv;
517 struct fsl_esdhc *regs = priv->esdhc_regs;
518 int sdhc_clk = priv->sdhc_clk;
521 if (clock < mmc->cfg->f_min)
522 clock = mmc->cfg->f_min;
524 if (sdhc_clk / 16 > clock) {
525 for (pre_div = 2; pre_div < 256; pre_div *= 2)
526 if ((sdhc_clk / pre_div) <= (clock * 16))
531 for (div = 1; div <= 16; div++)
532 if ((sdhc_clk / (div * pre_div)) <= clock)
535 pre_div >>= mmc->ddr_mode ? 2 : 1;
538 clk = (pre_div << 8) | (div << 4);
540 #ifdef CONFIG_FSL_USDHC
541 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
543 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
546 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
550 #ifdef CONFIG_FSL_USDHC
551 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
553 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
558 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
559 static void esdhc_clock_control(struct mmc *mmc, bool enable)
561 struct fsl_esdhc_priv *priv = mmc->priv;
562 struct fsl_esdhc *regs = priv->esdhc_regs;
566 value = esdhc_read32(®s->sysctl);
569 value |= SYSCTL_CKEN;
571 value &= ~SYSCTL_CKEN;
573 esdhc_write32(®s->sysctl, value);
576 value = PRSSTAT_SDSTB;
577 while (!(esdhc_read32(®s->prsstat) & value)) {
579 printf("fsl_esdhc: Internal clock never stabilised.\n");
588 static void esdhc_set_ios(struct mmc *mmc)
590 struct fsl_esdhc_priv *priv = mmc->priv;
591 struct fsl_esdhc *regs = priv->esdhc_regs;
593 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
594 /* Select to use peripheral clock */
595 esdhc_clock_control(mmc, false);
596 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
597 esdhc_clock_control(mmc, true);
599 /* Set the clock speed */
600 set_sysctl(mmc, mmc->clock);
602 /* Set the bus width */
603 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
605 if (mmc->bus_width == 4)
606 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
607 else if (mmc->bus_width == 8)
608 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
612 static int esdhc_init(struct mmc *mmc)
614 struct fsl_esdhc_priv *priv = mmc->priv;
615 struct fsl_esdhc *regs = priv->esdhc_regs;
618 /* Reset the entire host controller */
619 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
621 /* Wait until the controller is available */
622 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
625 #if defined(CONFIG_FSL_USDHC)
626 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
627 esdhc_write32(®s->mmcboot, 0x0);
628 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
629 esdhc_write32(®s->mixctrl, 0x0);
630 esdhc_write32(®s->clktunectrlstatus, 0x0);
632 /* Put VEND_SPEC to default value */
633 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
635 /* Disable DLL_CTRL delay line */
636 esdhc_write32(®s->dllctrl, 0x0);
640 /* Enable cache snooping */
641 esdhc_write32(®s->scr, 0x00000040);
644 #ifndef CONFIG_FSL_USDHC
645 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
647 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
650 /* Set the initial clock speed */
651 mmc_set_clock(mmc, 400000);
653 /* Disable the BRR and BWR bits in IRQSTAT */
654 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
656 /* Put the PROCTL reg back to the default */
657 esdhc_write32(®s->proctl, PROCTL_INIT);
659 /* Set timout to the maximum value */
660 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
662 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
663 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
669 static int esdhc_getcd(struct mmc *mmc)
671 struct fsl_esdhc_priv *priv = mmc->priv;
672 struct fsl_esdhc *regs = priv->esdhc_regs;
675 #ifdef CONFIG_ESDHC_DETECT_QUIRK
676 if (CONFIG_ESDHC_DETECT_QUIRK)
681 if (priv->non_removable)
684 if (dm_gpio_is_valid(&priv->cd_gpio))
685 return dm_gpio_get_value(&priv->cd_gpio);
688 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
694 static void esdhc_reset(struct fsl_esdhc *regs)
696 unsigned long timeout = 100; /* wait max 100 ms */
698 /* reset the controller */
699 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
701 /* hardware clears the bit when it is done */
702 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
705 printf("MMC/SD: Reset never completed.\n");
708 static const struct mmc_ops esdhc_ops = {
709 .send_cmd = esdhc_send_cmd,
710 .set_ios = esdhc_set_ios,
712 .getcd = esdhc_getcd,
715 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
716 struct fsl_esdhc_priv *priv)
721 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
722 priv->bus_width = cfg->max_bus_width;
723 priv->sdhc_clk = cfg->sdhc_clk;
728 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
730 struct fsl_esdhc *regs;
732 u32 caps, voltage_caps;
737 regs = priv->esdhc_regs;
739 /* First reset the eSDHC controller */
742 #ifndef CONFIG_FSL_USDHC
743 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
744 | SYSCTL_IPGEN | SYSCTL_CKEN);
746 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
747 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
750 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
751 memset(&priv->cfg, 0, sizeof(priv->cfg));
754 caps = esdhc_read32(®s->hostcapblt);
756 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
757 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
758 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
761 /* T4240 host controller capabilities register should have VS33 bit */
762 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
763 caps = caps | ESDHC_HOSTCAPBLT_VS33;
766 if (caps & ESDHC_HOSTCAPBLT_VS18)
767 voltage_caps |= MMC_VDD_165_195;
768 if (caps & ESDHC_HOSTCAPBLT_VS30)
769 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
770 if (caps & ESDHC_HOSTCAPBLT_VS33)
771 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
773 priv->cfg.name = "FSL_SDHC";
774 priv->cfg.ops = &esdhc_ops;
775 #ifdef CONFIG_SYS_SD_VOLTAGE
776 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
778 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
780 if ((priv->cfg.voltages & voltage_caps) == 0) {
781 printf("voltage not supported by controller\n");
785 if (priv->bus_width == 8)
786 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
787 else if (priv->bus_width == 4)
788 priv->cfg.host_caps = MMC_MODE_4BIT;
790 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
791 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
792 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
795 if (priv->bus_width > 0) {
796 if (priv->bus_width < 8)
797 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
798 if (priv->bus_width < 4)
799 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
802 if (caps & ESDHC_HOSTCAPBLT_HSS)
803 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
805 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
806 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
807 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
810 priv->cfg.f_min = 400000;
811 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
813 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
815 mmc = mmc_create(&priv->cfg, priv);
824 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
826 struct fsl_esdhc_priv *priv;
832 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
836 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
838 debug("%s xlate failure\n", __func__);
843 ret = fsl_esdhc_init(priv);
845 debug("%s init failure\n", __func__);
853 int fsl_esdhc_mmc_init(bd_t *bis)
855 struct fsl_esdhc_cfg *cfg;
857 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
858 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
859 cfg->sdhc_clk = gd->arch.sdhc_clk;
860 return fsl_esdhc_initialize(bis, cfg);
863 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
864 void mmc_adapter_card_type_ident(void)
869 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
870 gd->arch.sdhc_adapter = card_id;
873 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
874 value = QIXIS_READ(brdcfg[5]);
875 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
876 QIXIS_WRITE(brdcfg[5], value);
878 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
879 value = QIXIS_READ(pwr_ctl[1]);
880 value |= QIXIS_EVDD_BY_SDHC_VS;
881 QIXIS_WRITE(pwr_ctl[1], value);
883 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
884 value = QIXIS_READ(brdcfg[5]);
885 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
886 QIXIS_WRITE(brdcfg[5], value);
888 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
890 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
892 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
894 case QIXIS_ESDHC_NO_ADAPTER:
902 #ifdef CONFIG_OF_LIBFDT
903 void fdt_fixup_esdhc(void *blob, bd_t *bd)
905 const char *compat = "fsl,esdhc";
907 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
908 if (!hwconfig("esdhc")) {
909 do_fixup_by_compat(blob, compat, "status", "disabled",
915 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
916 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
917 gd->arch.sdhc_clk, 1);
919 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
920 gd->arch.sdhc_clk, 1);
922 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
923 do_fixup_by_compat_u32(blob, compat, "adapter-type",
924 (u32)(gd->arch.sdhc_adapter), 1);
926 do_fixup_by_compat(blob, compat, "status", "okay",
932 #include <asm/arch/clock.h>
933 static int fsl_esdhc_probe(struct udevice *dev)
935 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
936 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
937 const void *fdt = gd->fdt_blob;
938 int node = dev->of_offset;
943 addr = dev_get_addr(dev);
944 if (addr == FDT_ADDR_T_NONE)
947 priv->esdhc_regs = (struct fsl_esdhc *)addr;
950 val = fdtdec_get_int(fdt, node, "bus-width", -1);
958 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
959 priv->non_removable = 1;
961 priv->non_removable = 0;
962 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
963 &priv->cd_gpio, GPIOD_IS_IN);
968 * Because lack of clk driver, if SDHC clk is not enabled,
969 * need to enable it first before this driver is invoked.
971 * we use MXC_ESDHC_CLK to get clk freq.
972 * If one would like to make this function work,
973 * the aliases should be provided in dts as this:
981 * Then if your board only supports mmc2 and mmc3, but we can
982 * correctly get the seq as 2 and 3, then let mxc_get_clock
985 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
986 if (priv->sdhc_clk <= 0) {
987 dev_err(dev, "Unable to get clk for %s\n", dev->name);
991 ret = fsl_esdhc_init(priv);
993 dev_err(dev, "fsl_esdhc_init failure\n");
997 upriv->mmc = priv->mmc;
1002 static const struct udevice_id fsl_esdhc_ids[] = {
1003 { .compatible = "fsl,imx6ul-usdhc", },
1004 { .compatible = "fsl,imx6sx-usdhc", },
1005 { .compatible = "fsl,imx6sl-usdhc", },
1006 { .compatible = "fsl,imx6q-usdhc", },
1007 { .compatible = "fsl,imx7d-usdhc", },
1011 U_BOOT_DRIVER(fsl_esdhc) = {
1012 .name = "fsl-esdhc-mmc",
1014 .of_match = fsl_esdhc_ids,
1015 .probe = fsl_esdhc_probe,
1016 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),