2 * Faraday MMC/SD Host Controller
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
7 * This file is released under the terms of GPL v2 and any later version.
8 * See the file COPYING in the root directory of the source tree for details.
17 #include <asm/errno.h>
18 #include <asm/byteorder.h>
19 #include <faraday/ftsdc010.h>
21 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
22 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
24 struct ftsdc010_chip {
26 uint32_t wprot; /* write protected (locked) */
27 uint32_t rate; /* actual SD clock in Hz */
28 uint32_t sclk; /* FTSDC010 source clock in Hz */
29 uint32_t fifo; /* fifo depth in bytes */
33 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
35 struct ftsdc010_chip *chip = mmc->priv;
36 struct ftsdc010_mmc __iomem *regs = chip->regs;
39 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
40 uint32_t arg = mmc_cmd->cmdarg;
41 uint32_t flags = mmc_cmd->resp_type;
43 cmd |= FTSDC010_CMD_CMD_EN;
46 cmd |= FTSDC010_CMD_APP_CMD;
50 if (flags & MMC_RSP_PRESENT)
51 cmd |= FTSDC010_CMD_NEED_RSP;
53 if (flags & MMC_RSP_136)
54 cmd |= FTSDC010_CMD_LONG_RSP;
56 writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
58 writel(arg, ®s->argu);
59 writel(cmd, ®s->cmd);
61 if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
62 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
63 if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) {
64 writel(FTSDC010_STATUS_CMD_SEND, ®s->clr);
71 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
72 st = readl(®s->status);
73 writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr);
74 if (st & FTSDC010_STATUS_RSP_MASK)
77 if (st & FTSDC010_STATUS_RSP_CRC_OK) {
78 if (flags & MMC_RSP_136) {
79 mmc_cmd->response[0] = readl(®s->rsp3);
80 mmc_cmd->response[1] = readl(®s->rsp2);
81 mmc_cmd->response[2] = readl(®s->rsp1);
82 mmc_cmd->response[3] = readl(®s->rsp0);
84 mmc_cmd->response[0] = readl(®s->rsp0);
88 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
94 debug("ftsdc010: cmd timeout (op code=%d)\n",
96 } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
103 static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
105 struct ftsdc010_chip *chip = mmc->priv;
106 struct ftsdc010_mmc __iomem *regs = chip->regs;
109 for (div = 0; div < 0x7f; ++div) {
110 if (rate >= chip->sclk / (2 * (div + 1)))
113 chip->rate = chip->sclk / (2 * (div + 1));
115 writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr);
118 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD);
120 if (chip->rate > 25000000)
121 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
123 clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
127 static inline int ftsdc010_is_ro(struct mmc *mmc)
129 struct ftsdc010_chip *chip = mmc->priv;
130 const uint8_t *csd = (const uint8_t *)mmc->csd;
132 return chip->wprot || (csd[1] & 0x30);
135 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
140 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
141 st = readl(®s->status);
144 writel(st & mask, ®s->clr);
150 debug("ftsdc010: wait st(0x%x) timeout\n", mask);
159 static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
160 struct mmc_data *data)
162 int ret = UNUSABLE_ERR;
164 struct ftsdc010_chip *chip = mmc->priv;
165 struct ftsdc010_mmc __iomem *regs = chip->regs;
167 if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
168 printf("ftsdc010: the card is write protected!\n");
175 len = data->blocksize * data->blocks;
177 /* 1. data disable + fifo reset */
179 #ifdef CONFIG_FTSDC010_SDIO
180 dcr |= FTSDC010_DCR_FIFO_RST;
182 writel(dcr, ®s->dcr);
184 /* 2. clear status register */
185 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
186 | FTSDC010_STATUS_FIFO_ORUN, ®s->clr);
188 /* 3. data timeout (1 sec) */
189 writel(chip->rate, ®s->dtr);
191 /* 4. data length (bytes) */
192 writel(len, ®s->dlr);
195 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
196 if (data->flags & MMC_DATA_WRITE)
197 dcr |= FTSDC010_DCR_DATA_WRITE;
198 writel(dcr, ®s->dcr);
201 ret = ftsdc010_send_cmd(mmc, cmd);
203 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
210 if (data->flags & MMC_DATA_WRITE) {
211 const uint8_t *buf = (const uint8_t *)data->src;
216 /* wait for tx ready */
217 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
221 /* write bytes to ftsdc010 */
222 for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
223 writel(*(uint32_t *)buf, ®s->dwr);
232 uint8_t *buf = (uint8_t *)data->dest;
237 /* wait for rx ready */
238 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
242 /* fetch bytes from ftsdc010 */
243 for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
244 *(uint32_t *)buf = readl(®s->dwr);
255 ret = ftsdc010_wait(regs,
256 FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR);
262 static void ftsdc010_set_ios(struct mmc *mmc)
264 struct ftsdc010_chip *chip = mmc->priv;
265 struct ftsdc010_mmc __iomem *regs = chip->regs;
267 ftsdc010_clkset(mmc, mmc->clock);
269 clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK);
270 switch (mmc->bus_width) {
272 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT);
275 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT);
278 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT);
283 static int ftsdc010_init(struct mmc *mmc)
285 struct ftsdc010_chip *chip = mmc->priv;
286 struct ftsdc010_mmc __iomem *regs = chip->regs;
289 if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT)
292 if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) {
293 printf("ftsdc010: write protected\n");
297 chip->fifo = (readl(®s->feature) & 0xff) << 2;
300 writel(FTSDC010_CMD_SDC_RST, ®s->cmd);
301 for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
302 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST)
306 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) {
307 printf("ftsdc010: reset failed\n");
311 /* 2. enter low speed mode (400k card detection) */
312 ftsdc010_clkset(mmc, 400000);
314 /* 3. interrupt disabled */
315 writel(0, ®s->int_mask);
320 int ftsdc010_mmc_init(int devid)
323 struct ftsdc010_chip *chip;
324 struct ftsdc010_mmc __iomem *regs;
325 #ifdef CONFIG_FTSDC010_BASE_LIST
326 uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
328 if (devid < 0 || devid >= ARRAY_SIZE(base_list))
330 regs = (void __iomem *)base_list[devid];
332 regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
335 mmc = malloc(sizeof(struct mmc));
338 memset(mmc, 0, sizeof(struct mmc));
340 chip = malloc(sizeof(struct ftsdc010_chip));
345 memset(chip, 0, sizeof(struct ftsdc010_chip));
350 sprintf(mmc->name, "ftsdc010");
351 mmc->send_cmd = ftsdc010_request;
352 mmc->set_ios = ftsdc010_set_ios;
353 mmc->init = ftsdc010_init;
355 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
356 switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) {
357 case FTSDC010_BWR_CAPS_4BIT:
358 mmc->host_caps |= MMC_MODE_4BIT;
360 case FTSDC010_BWR_CAPS_8BIT:
361 mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
367 #ifdef CONFIG_SYS_CLK_FREQ
368 chip->sclk = CONFIG_SYS_CLK_FREQ;
370 chip->sclk = clk_get_rate("SDC");
373 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
374 mmc->f_max = chip->sclk / 2;
375 mmc->f_min = chip->sclk / 0x100;
376 mmc->block_dev.part_type = PART_TYPE_DOS;