2 * Faraday MMC/SD Host Controller
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/errno.h>
17 #include <asm/byteorder.h>
18 #include <faraday/ftsdc010.h>
20 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
21 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
23 struct ftsdc010_chip {
25 uint32_t wprot; /* write protected (locked) */
26 uint32_t rate; /* actual SD clock in Hz */
27 uint32_t sclk; /* FTSDC010 source clock in Hz */
28 uint32_t fifo; /* fifo depth in bytes */
32 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
34 struct ftsdc010_chip *chip = mmc->priv;
35 struct ftsdc010_mmc __iomem *regs = chip->regs;
38 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
39 uint32_t arg = mmc_cmd->cmdarg;
40 uint32_t flags = mmc_cmd->resp_type;
42 cmd |= FTSDC010_CMD_CMD_EN;
45 cmd |= FTSDC010_CMD_APP_CMD;
49 if (flags & MMC_RSP_PRESENT)
50 cmd |= FTSDC010_CMD_NEED_RSP;
52 if (flags & MMC_RSP_136)
53 cmd |= FTSDC010_CMD_LONG_RSP;
55 writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
57 writel(arg, ®s->argu);
58 writel(cmd, ®s->cmd);
60 if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
61 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
62 if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) {
63 writel(FTSDC010_STATUS_CMD_SEND, ®s->clr);
70 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
71 st = readl(®s->status);
72 writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr);
73 if (st & FTSDC010_STATUS_RSP_MASK)
76 if (st & FTSDC010_STATUS_RSP_CRC_OK) {
77 if (flags & MMC_RSP_136) {
78 mmc_cmd->response[0] = readl(®s->rsp3);
79 mmc_cmd->response[1] = readl(®s->rsp2);
80 mmc_cmd->response[2] = readl(®s->rsp1);
81 mmc_cmd->response[3] = readl(®s->rsp0);
83 mmc_cmd->response[0] = readl(®s->rsp0);
87 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
93 debug("ftsdc010: cmd timeout (op code=%d)\n",
95 } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
102 static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
104 struct ftsdc010_chip *chip = mmc->priv;
105 struct ftsdc010_mmc __iomem *regs = chip->regs;
108 for (div = 0; div < 0x7f; ++div) {
109 if (rate >= chip->sclk / (2 * (div + 1)))
112 chip->rate = chip->sclk / (2 * (div + 1));
114 writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr);
117 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD);
119 if (chip->rate > 25000000)
120 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
122 clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
126 static inline int ftsdc010_is_ro(struct mmc *mmc)
128 struct ftsdc010_chip *chip = mmc->priv;
129 const uint8_t *csd = (const uint8_t *)mmc->csd;
131 return chip->wprot || (csd[1] & 0x30);
134 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
139 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
140 st = readl(®s->status);
143 writel(st & mask, ®s->clr);
149 debug("ftsdc010: wait st(0x%x) timeout\n", mask);
158 static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
159 struct mmc_data *data)
161 int ret = UNUSABLE_ERR;
163 struct ftsdc010_chip *chip = mmc->priv;
164 struct ftsdc010_mmc __iomem *regs = chip->regs;
166 if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
167 printf("ftsdc010: the card is write protected!\n");
174 len = data->blocksize * data->blocks;
176 /* 1. data disable + fifo reset */
177 writel(FTSDC010_DCR_FIFO_RST, ®s->dcr);
179 /* 2. clear status register */
180 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
181 | FTSDC010_STATUS_FIFO_ORUN, ®s->clr);
183 /* 3. data timeout (1 sec) */
184 writel(chip->rate, ®s->dtr);
186 /* 4. data length (bytes) */
187 writel(len, ®s->dlr);
190 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
191 if (data->flags & MMC_DATA_WRITE)
192 dcr |= FTSDC010_DCR_DATA_WRITE;
193 writel(dcr, ®s->dcr);
196 ret = ftsdc010_send_cmd(mmc, cmd);
198 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
205 if (data->flags & MMC_DATA_WRITE) {
206 const uint8_t *buf = (const uint8_t *)data->src;
211 /* wait for tx ready */
212 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
216 /* write bytes to ftsdc010 */
217 for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
218 writel(*(uint32_t *)buf, ®s->dwr);
227 uint8_t *buf = (uint8_t *)data->dest;
232 /* wait for rx ready */
233 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
237 /* fetch bytes from ftsdc010 */
238 for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
239 *(uint32_t *)buf = readl(®s->dwr);
250 ret = ftsdc010_wait(regs,
251 FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR);
257 static void ftsdc010_set_ios(struct mmc *mmc)
259 struct ftsdc010_chip *chip = mmc->priv;
260 struct ftsdc010_mmc __iomem *regs = chip->regs;
262 ftsdc010_clkset(mmc, mmc->clock);
264 clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK);
265 switch (mmc->bus_width) {
267 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT);
270 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT);
273 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT);
278 static int ftsdc010_init(struct mmc *mmc)
280 struct ftsdc010_chip *chip = mmc->priv;
281 struct ftsdc010_mmc __iomem *regs = chip->regs;
284 if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT)
287 if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) {
288 printf("ftsdc010: write protected\n");
292 chip->fifo = (readl(®s->feature) & 0xff) << 2;
295 writel(FTSDC010_CMD_SDC_RST, ®s->cmd);
296 for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
297 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST)
301 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) {
302 printf("ftsdc010: reset failed\n");
306 /* 2. enter low speed mode (400k card detection) */
307 ftsdc010_clkset(mmc, 400000);
309 /* 3. interrupt disabled */
310 writel(0, ®s->int_mask);
315 int ftsdc010_mmc_init(int devid)
318 struct ftsdc010_chip *chip;
319 struct ftsdc010_mmc __iomem *regs;
320 #ifdef CONFIG_FTSDC010_BASE_LIST
321 uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
323 if (devid < 0 || devid >= ARRAY_SIZE(base_list))
325 regs = (void __iomem *)base_list[devid];
327 regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
330 mmc = malloc(sizeof(struct mmc));
333 memset(mmc, 0, sizeof(struct mmc));
335 chip = malloc(sizeof(struct ftsdc010_chip));
340 memset(chip, 0, sizeof(struct ftsdc010_chip));
345 sprintf(mmc->name, "ftsdc010");
346 mmc->send_cmd = ftsdc010_request;
347 mmc->set_ios = ftsdc010_set_ios;
348 mmc->init = ftsdc010_init;
350 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
351 switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) {
352 case FTSDC010_BWR_CAPS_4BIT:
353 mmc->host_caps |= MMC_MODE_4BIT;
355 case FTSDC010_BWR_CAPS_8BIT:
356 mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
362 #ifdef CONFIG_SYS_CLK_FREQ
363 chip->sclk = CONFIG_SYS_CLK_FREQ;
365 chip->sclk = clk_get_rate("SDC");
368 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
369 mmc->f_max = chip->sclk / 2;
370 mmc->f_min = chip->sclk / 0x100;
371 mmc->block_dev.part_type = PART_TYPE_DOS;