3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
7 * Copyright (C) 2004-2006 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
18 #include <asm/byteorder.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/hardware.h>
21 #include "atmel_mci.h"
23 #ifndef CONFIG_SYS_MMC_CLK_OD
24 # define CONFIG_SYS_MMC_CLK_OD 150000
27 #define MMC_DEFAULT_BLKLEN 512
29 #if defined(CONFIG_ATMEL_MCI_PORTB)
35 struct atmel_mci_priv {
36 struct mmc_config cfg;
37 struct atmel_mci *mci;
38 unsigned int initialized:1;
41 /* Read Atmel MCI IP version */
42 static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
44 return readl(&mci->version) & 0x00000fff;
48 * Print command and status:
50 * - always when DEBUG is defined
53 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
55 debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
56 cmdr, cmdr & 0x3F, arg, status, msg);
59 /* Setup for MCI Clock and Block Size */
60 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
62 struct atmel_mci_priv *priv = mmc->priv;
63 atmel_mci_t *mci = priv->mci;
64 u32 bus_hz = get_mci_clk_rate();
66 unsigned int version = atmel_mci_get_version(mci);
70 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
73 if (version >= 0x500) {
74 clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
81 debug("mci: setting clock %u Hz, block size %u\n",
82 bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
84 /* find clkdiv yielding a rate <= than requested */
85 for (clkdiv = 0; clkdiv < 255; clkdiv++) {
86 if ((bus_hz / (clkdiv + 1) / 2) <= hz)
89 debug("mci: setting clock %u Hz, block size %u\n",
90 (bus_hz / (clkdiv + 1)) / 2, blklen);
97 mr = MMCI_BF(CLKDIV, clkdiv);
99 /* MCI IP version >= 0x200 has R/WPROOF */
100 if (version >= 0x200)
101 mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
104 * MCI IP version >= 0x500 use bit 16 as clkodd.
105 * MCI IP version < 0x500 use upper 16 bits for blklen.
107 if (version >= 0x500)
108 mr |= MMCI_BF(CLKODD, clkodd);
110 mr |= MMCI_BF(BLKLEN, blklen);
112 writel(mr, &mci->mr);
114 /* MCI IP version >= 0x200 has blkr */
115 if (version >= 0x200)
116 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
118 if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
119 writel(MMCI_BIT(HSMODE), &mci->cfg);
123 priv->initialized = 1;
126 /* Return the CMDR with flags for a given command and data packet */
127 static u32 mci_encode_cmd(
128 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
132 /* Default Flags for Errors */
133 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
134 MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
136 /* Default Flags for the Command */
137 cmdr |= MMCI_BIT(MAXLAT);
140 cmdr |= MMCI_BF(TRCMD, 1);
141 if (data->blocks > 1)
142 cmdr |= MMCI_BF(TRTYP, 1);
143 if (data->flags & MMC_DATA_READ)
144 cmdr |= MMCI_BIT(TRDIR);
147 if (cmd->resp_type & MMC_RSP_CRC)
148 *error_flags |= MMCI_BIT(RCRCE);
149 if (cmd->resp_type & MMC_RSP_136)
150 cmdr |= MMCI_BF(RSPTYP, 2);
151 else if (cmd->resp_type & MMC_RSP_BUSY)
152 cmdr |= MMCI_BF(RSPTYP, 3);
153 else if (cmd->resp_type & MMC_RSP_PRESENT)
154 cmdr |= MMCI_BF(RSPTYP, 1);
156 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
159 /* Entered into function pointer in mci_send_cmd */
160 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
165 status = readl(&mci->sr);
166 if (status & (error_flags | MMCI_BIT(OVRE)))
168 } while (!(status & MMCI_BIT(RXRDY)));
170 if (status & MMCI_BIT(RXRDY)) {
171 *data = readl(&mci->rdr);
178 /* Entered into function pointer in mci_send_cmd */
179 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
184 status = readl(&mci->sr);
185 if (status & (error_flags | MMCI_BIT(UNRE)))
187 } while (!(status & MMCI_BIT(TXRDY)));
189 if (status & MMCI_BIT(TXRDY)) {
190 writel(*data, &mci->tdr);
198 * Entered into mmc structure during driver init
200 * Sends a command out on the bus and deals with the block data.
201 * Takes the mmc pointer, a command pointer, and an optional data pointer.
204 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
206 struct atmel_mci_priv *priv = mmc->priv;
207 atmel_mci_t *mci = priv->mci;
212 if (!priv->initialized) {
213 puts ("MCI not initialized!\n");
217 /* Figure out the transfer arguments */
218 cmdr = mci_encode_cmd(cmd, data, &error_flags);
220 /* For multi blocks read/write, set the block register */
221 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
222 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
223 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
226 /* Send the command */
227 writel(cmd->cmdarg, &mci->argr);
228 writel(cmdr, &mci->cmdr);
231 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
234 /* Wait for the command to complete */
235 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
237 if ((status & error_flags) & MMCI_BIT(RTOE)) {
238 dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
240 } else if (status & error_flags) {
241 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
245 /* Copy the response to the response buffer */
246 if (cmd->resp_type & MMC_RSP_136) {
247 cmd->response[0] = readl(&mci->rspr);
248 cmd->response[1] = readl(&mci->rspr1);
249 cmd->response[2] = readl(&mci->rspr2);
250 cmd->response[3] = readl(&mci->rspr3);
252 cmd->response[0] = readl(&mci->rspr);
254 /* transfer all of the blocks */
256 u32 word_count, block_count;
258 u32 sys_blocksize, dummy, i;
260 (atmel_mci_t *mci, u32* data, u32 error_flags);
262 if (data->flags & MMC_DATA_READ) {
263 mci_data_op = mci_data_read;
264 sys_blocksize = mmc->read_bl_len;
265 ioptr = (u32*)data->dest;
267 mci_data_op = mci_data_write;
268 sys_blocksize = mmc->write_bl_len;
269 ioptr = (u32*)data->src;
273 for (block_count = 0;
274 block_count < data->blocks && !status;
278 status = mci_data_op(mci, ioptr, error_flags);
281 } while (!status && word_count < (data->blocksize/4));
283 if (data->flags & MMC_DATA_READ)
285 u32 cnt = word_count * 4;
286 printf("Read Data:\n");
287 print_buffer(0, data->dest + cnt * block_count,
292 if (!status && word_count < (sys_blocksize / 4))
293 printf("filling rest of block...\n");
295 /* fill the rest of a full block */
296 while (!status && word_count < (sys_blocksize / 4)) {
297 status = mci_data_op(mci, &dummy,
302 dump_cmd(cmdr, cmd->cmdarg, status,
303 "Data Transfer Failed");
308 /* Wait for Transfer End */
311 status = readl(&mci->sr);
313 if (status & error_flags) {
314 dump_cmd(cmdr, cmd->cmdarg, status,
319 } while ((status & MMCI_BIT(DTIP)) && i < 10000);
320 if (status & MMCI_BIT(DTIP)) {
321 dump_cmd(cmdr, cmd->cmdarg, status,
322 "XFER DTIP never unset, ignoring");
329 /* Entered into mmc structure during driver init */
330 static void mci_set_ios(struct mmc *mmc)
332 struct atmel_mci_priv *priv = mmc->priv;
333 atmel_mci_t *mci = priv->mci;
334 int bus_width = mmc->bus_width;
335 unsigned int version = atmel_mci_get_version(mci);
338 /* Set the clock speed */
339 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
342 * set the bus width and select slot for this interface
343 * there is no capability for multiple slots on the same interface yet
345 if ((version & 0xf00) >= 0x300) {
358 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
360 busw = (bus_width == 4) ? 1 : 0;
362 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
366 /* Entered into mmc structure during driver init */
367 static int mci_init(struct mmc *mmc)
369 struct atmel_mci_priv *priv = mmc->priv;
370 atmel_mci_t *mci = priv->mci;
372 /* Initialize controller */
373 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
374 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
375 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
376 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
378 /* This delay can be optimized, but stick with max value */
379 writel(0x7f, &mci->dtor);
380 /* Disable Interrupts */
381 writel(~0UL, &mci->idr);
383 /* Set default clocks and blocklen */
384 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
389 static const struct mmc_ops atmel_mci_ops = {
390 .send_cmd = mci_send_cmd,
391 .set_ios = mci_set_ios,
396 * This is the only exported function
398 * Call it with the MCI register base address
400 int atmel_mci_init(void *regs)
403 struct mmc_config *cfg;
404 struct atmel_mci_priv *priv;
405 unsigned int version;
407 priv = calloc(1, sizeof(*priv));
414 cfg->ops = &atmel_mci_ops;
416 priv->mci = (struct atmel_mci *)regs;
417 priv->initialized = 0;
419 /* need to be able to pass these in on a board by board basis */
420 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
421 version = atmel_mci_get_version(priv->mci);
422 if ((version & 0xf00) >= 0x300) {
423 cfg->host_caps = MMC_MODE_8BIT;
424 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
427 cfg->host_caps |= MMC_MODE_4BIT;
430 * min and max frequencies determined by
431 * max and min of clock divider
433 cfg->f_min = get_mci_clk_rate() / (2*256);
434 cfg->f_max = get_mci_clk_rate() / (2*1);
436 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
438 mmc = mmc_create(cfg, priv);
444 /* NOTE: possibly leaking the priv structure */