git.sur5r.net Git - u-boot/blob - drivers/mmc/matsushita-common.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <fdtdec.h>
  11 #include <mmc.h>
  12 #include <dm.h>
  13 #include <linux/compat.h>
  14 #include <linux/dma-direction.h>
  15 #include <linux/io.h>
  16 #include <linux/sizes.h>
  17 #include <power/regulator.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "matsushita-common.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
  25 {
  26         return readq(priv->regbase + (reg << 1));
  27 }
  28
  29 static void matsu_sd_writeq(struct matsu_sd_priv *priv,
  30                                u64 val, unsigned int reg)
  31 {
  32         writeq(val, priv->regbase + (reg << 1));
  33 }
  34
  35 static u16 matsu_sd_readw(struct matsu_sd_priv *priv, unsigned int reg)
  36 {
  37         return readw(priv->regbase + (reg >> 1));
  38 }
  39
  40 static void matsu_sd_writew(struct matsu_sd_priv *priv,
  41                                u16 val, unsigned int reg)
  42 {
  43         writew(val, priv->regbase + (reg >> 1));
  44 }
  45
  46 static u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
  47 {
  48         u32 val;
  49
  50         if (priv->caps & MATSU_SD_CAP_64BIT)
  51                 return readl(priv->regbase + (reg << 1));
  52         else if (priv->caps & MATSU_SD_CAP_16BIT) {
  53                 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
  54                 if ((reg == MATSU_SD_RSP10) || (reg == MATSU_SD_RSP32) ||
  55                     (reg == MATSU_SD_RSP54) || (reg == MATSU_SD_RSP76)) {
  56                         val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
  57                 }
  58                 return val;
  59         } else
  60                 return readl(priv->regbase + reg);
  61 }
  62
  63 static void matsu_sd_writel(struct matsu_sd_priv *priv,
  64                                u32 val, unsigned int reg)
  65 {
  66         if (priv->caps & MATSU_SD_CAP_64BIT)
  67                 writel(val, priv->regbase + (reg << 1));
  68         if (priv->caps & MATSU_SD_CAP_16BIT) {
  69                 writew(val & 0xffff, priv->regbase + (reg >> 1));
  70                 if (val >> 16)
  71                         writew(val >> 16, priv->regbase + (reg >> 1) + 2);
  72         } else
  73                 writel(val, priv->regbase + reg);
  74 }
  75
  76 static dma_addr_t __dma_map_single(void *ptr, size_t size,
  77                                    enum dma_data_direction dir)
  78 {
  79         unsigned long addr = (unsigned long)ptr;
  80
  81         if (dir == DMA_FROM_DEVICE)
  82                 invalidate_dcache_range(addr, addr + size);
  83         else
  84                 flush_dcache_range(addr, addr + size);
  85
  86         return addr;
  87 }
  88
  89 static void __dma_unmap_single(dma_addr_t addr, size_t size,
  90                                enum dma_data_direction dir)
  91 {
  92         if (dir != DMA_TO_DEVICE)
  93                 invalidate_dcache_range(addr, addr + size);
  94 }
  95
  96 static int matsu_sd_check_error(struct udevice *dev)
  97 {
  98         struct matsu_sd_priv *priv = dev_get_priv(dev);
  99         u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
 100
 101         if (info2 & MATSU_SD_INFO2_ERR_RTO) {
 102                 /*
 103                  * TIMEOUT must be returned for unsupported command.  Do not
 104                  * display error log since this might be a part of sequence to
 105                  * distinguish between SD and MMC.
 106                  */
 107                 return -ETIMEDOUT;
 108         }
 109
 110         if (info2 & MATSU_SD_INFO2_ERR_TO) {
 111                 dev_err(dev, "timeout error\n");
 112                 return -ETIMEDOUT;
 113         }
 114
 115         if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
 116                      MATSU_SD_INFO2_ERR_IDX)) {
 117                 dev_err(dev, "communication out of sync\n");
 118                 return -EILSEQ;
 119         }
 120
 121         if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
 122                      MATSU_SD_INFO2_ERR_ILW)) {
 123                 dev_err(dev, "illegal access\n");
 124                 return -EIO;
 125         }
 126
 127         return 0;
 128 }
 129
 130 static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 131                                     u32 flag)
 132 {
 133         struct matsu_sd_priv *priv = dev_get_priv(dev);
 134         long wait = 1000000;
 135         int ret;
 136
 137         while (!(matsu_sd_readl(priv, reg) & flag)) {
 138                 if (wait-- < 0) {
 139                         dev_err(dev, "timeout\n");
 140                         return -ETIMEDOUT;
 141                 }
 142
 143                 ret = matsu_sd_check_error(dev);
 144                 if (ret)
 145                         return ret;
 146
 147                 udelay(1);
 148         }
 149
 150         return 0;
 151 }
 152
 153 #define matsu_pio_read_fifo(__width, __suffix)                          \
 154 static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv,   \
 155                                           char *pbuf, uint blksz)       \
 156 {                                                                       \
 157         u##__width *buf = (u##__width *)pbuf;                           \
 158         int i;                                                          \
 159                                                                         \
 160         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 161                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 162                         *buf++ = matsu_sd_read##__suffix(priv,          \
 163                                                          MATSU_SD_BUF); \
 164                 }                                                       \
 165         } else {                                                        \
 166                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 167                         u##__width data;                                \
 168                         data = matsu_sd_read##__suffix(priv,            \
 169                                                        MATSU_SD_BUF);   \
 170                         put_unaligned(data, buf++);                     \
 171                 }                                                       \
 172         }                                                               \
 173 }
 174
 175 matsu_pio_read_fifo(64, q)
 176 matsu_pio_read_fifo(32, l)
 177 matsu_pio_read_fifo(16, w)
 178
 179 static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
 180                                           uint blocksize)
 181 {
 182         struct matsu_sd_priv *priv = dev_get_priv(dev);
 183         int ret;
 184
 185         /* wait until the buffer is filled with data */
 186         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 187                                        MATSU_SD_INFO2_BRE);
 188         if (ret)
 189                 return ret;
 190
 191         /*
 192          * Clear the status flag _before_ read the buffer out because
 193          * MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
 194          */
 195         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 196
 197         if (priv->caps & MATSU_SD_CAP_64BIT)
 198                 matsu_pio_read_fifo_64(priv, pbuf, blocksize);
 199         else if (priv->caps & MATSU_SD_CAP_16BIT)
 200                 matsu_pio_read_fifo_16(priv, pbuf, blocksize);
 201         else
 202                 matsu_pio_read_fifo_32(priv, pbuf, blocksize);
 203
 204         return 0;
 205 }
 206
 207 #define matsu_pio_write_fifo(__width, __suffix)                         \
 208 static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv,  \
 209                                            const char *pbuf, uint blksz)\
 210 {                                                                       \
 211         const u##__width *buf = (const u##__width *)pbuf;               \
 212         int i;                                                          \
 213                                                                         \
 214         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 215                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 216                         matsu_sd_write##__suffix(priv, *buf++,          \
 217                                                  MATSU_SD_BUF);         \
 218                 }                                                       \
 219         } else {                                                        \
 220                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 221                         u##__width data = get_unaligned(buf++);         \
 222                         matsu_sd_write##__suffix(priv, data,            \
 223                                                  MATSU_SD_BUF);         \
 224                 }                                                       \
 225         }                                                               \
 226 }
 227
 228 matsu_pio_write_fifo(64, q)
 229 matsu_pio_write_fifo(32, l)
 230 matsu_pio_write_fifo(16, w)
 231
 232 static int matsu_sd_pio_write_one_block(struct udevice *dev,
 233                                            const char *pbuf, uint blocksize)
 234 {
 235         struct matsu_sd_priv *priv = dev_get_priv(dev);
 236         int ret;
 237
 238         /* wait until the buffer becomes empty */
 239         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 240                                     MATSU_SD_INFO2_BWE);
 241         if (ret)
 242                 return ret;
 243
 244         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 245
 246         if (priv->caps & MATSU_SD_CAP_64BIT)
 247                 matsu_pio_write_fifo_64(priv, pbuf, blocksize);
 248         else if (priv->caps & MATSU_SD_CAP_16BIT)
 249                 matsu_pio_write_fifo_16(priv, pbuf, blocksize);
 250         else
 251                 matsu_pio_write_fifo_32(priv, pbuf, blocksize);
 252
 253         return 0;
 254 }
 255
 256 static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
 257 {
 258         const char *src = data->src;
 259         char *dest = data->dest;
 260         int i, ret;
 261
 262         for (i = 0; i < data->blocks; i++) {
 263                 if (data->flags & MMC_DATA_READ)
 264                         ret = matsu_sd_pio_read_one_block(dev, dest,
 265                                                              data->blocksize);
 266                 else
 267                         ret = matsu_sd_pio_write_one_block(dev, src,
 268                                                               data->blocksize);
 269                 if (ret)
 270                         return ret;
 271
 272                 if (data->flags & MMC_DATA_READ)
 273                         dest += data->blocksize;
 274                 else
 275                         src += data->blocksize;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
 282                                   dma_addr_t dma_addr)
 283 {
 284         u32 tmp;
 285
 286         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
 287         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
 288
 289         /* enable DMA */
 290         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 291         tmp |= MATSU_SD_EXTMODE_DMA_EN;
 292         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 293
 294         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
 295
 296         /* suppress the warning "right shift count >= width of type" */
 297         dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 298
 299         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
 300
 301         matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
 302 }
 303
 304 static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 305                                         unsigned int blocks)
 306 {
 307         struct matsu_sd_priv *priv = dev_get_priv(dev);
 308         long wait = 1000000 + 10 * blocks;
 309
 310         while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
 311                 if (wait-- < 0) {
 312                         dev_err(dev, "timeout during DMA\n");
 313                         return -ETIMEDOUT;
 314                 }
 315
 316                 udelay(10);
 317         }
 318
 319         if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
 320                 dev_err(dev, "error during DMA\n");
 321                 return -EIO;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 328 {
 329         struct matsu_sd_priv *priv = dev_get_priv(dev);
 330         size_t len = data->blocks * data->blocksize;
 331         void *buf;
 332         enum dma_data_direction dir;
 333         dma_addr_t dma_addr;
 334         u32 poll_flag, tmp;
 335         int ret;
 336
 337         tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 338
 339         if (data->flags & MMC_DATA_READ) {
 340                 buf = data->dest;
 341                 dir = DMA_FROM_DEVICE;
 342                 /*
 343                  * The DMA READ completion flag position differs on Socionext
 344                  * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
 345                  * bit 17 is a hardware bug and forbidden. It is bit 17 on
 346                  * Renesas SoCs and bit 20 does not work on them.
 347                  */
 348                 poll_flag = (priv->caps & MATSU_SD_CAP_RCAR) ?
 349                             MATSU_SD_DMA_INFO1_END_RD :
 350                             MATSU_SD_DMA_INFO1_END_RD2;
 351                 tmp |= MATSU_SD_DMA_MODE_DIR_RD;
 352         } else {
 353                 buf = (void *)data->src;
 354                 dir = DMA_TO_DEVICE;
 355                 poll_flag = MATSU_SD_DMA_INFO1_END_WR;
 356                 tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
 357         }
 358
 359         matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 360
 361         dma_addr = __dma_map_single(buf, len, dir);
 362
 363         matsu_sd_dma_start(priv, dma_addr);
 364
 365         ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
 366
 367         __dma_unmap_single(dma_addr, len, dir);
 368
 369         return ret;
 370 }
 371
 372 /* check if the address is DMA'able */
 373 static bool matsu_sd_addr_is_dmaable(unsigned long addr)
 374 {
 375         if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
 376                 return false;
 377
 378 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
 379         defined(CONFIG_SPL_BUILD)
 380         /*
 381          * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
 382          * of L2, which is unreachable from the DMA engine.
 383          */
 384         if (addr < CONFIG_SPL_STACK)
 385                 return false;
 386 #endif
 387
 388         return true;
 389 }
 390
 391 int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 392                       struct mmc_data *data)
 393 {
 394         struct matsu_sd_priv *priv = dev_get_priv(dev);
 395         int ret;
 396         u32 tmp;
 397
 398         if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
 399                 dev_err(dev, "command busy\n");
 400                 return -EBUSY;
 401         }
 402
 403         /* clear all status flags */
 404         matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
 405         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 406
 407         /* disable DMA once */
 408         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 409         tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
 410         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 411
 412         matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
 413
 414         tmp = cmd->cmdidx;
 415
 416         if (data) {
 417                 matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
 418                 matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
 419
 420                 /* Do not send CMD12 automatically */
 421                 tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
 422
 423                 if (data->blocks > 1)
 424                         tmp |= MATSU_SD_CMD_MULTI;
 425
 426                 if (data->flags & MMC_DATA_READ)
 427                         tmp |= MATSU_SD_CMD_RD;
 428         }
 429
 430         /*
 431          * Do not use the response type auto-detection on this hardware.
 432          * CMD8, for example, has different response types on SD and eMMC,
 433          * while this controller always assumes the response type for SD.
 434          * Set the response type manually.
 435          */
 436         switch (cmd->resp_type) {
 437         case MMC_RSP_NONE:
 438                 tmp |= MATSU_SD_CMD_RSP_NONE;
 439                 break;
 440         case MMC_RSP_R1:
 441                 tmp |= MATSU_SD_CMD_RSP_R1;
 442                 break;
 443         case MMC_RSP_R1b:
 444                 tmp |= MATSU_SD_CMD_RSP_R1B;
 445                 break;
 446         case MMC_RSP_R2:
 447                 tmp |= MATSU_SD_CMD_RSP_R2;
 448                 break;
 449         case MMC_RSP_R3:
 450                 tmp |= MATSU_SD_CMD_RSP_R3;
 451                 break;
 452         default:
 453                 dev_err(dev, "unknown response type\n");
 454                 return -EINVAL;
 455         }
 456
 457         dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 458                 cmd->cmdidx, tmp, cmd->cmdarg);
 459         matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
 460
 461         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 462                                        MATSU_SD_INFO1_RSP);
 463         if (ret)
 464                 return ret;
 465
 466         if (cmd->resp_type & MMC_RSP_136) {
 467                 u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
 468                 u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
 469                 u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
 470                 u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
 471
 472                 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 473                                    ((rsp_103_72  & 0xff000000) >> 24);
 474                 cmd->response[1] = ((rsp_103_72  & 0x00ffffff) << 8) |
 475                                    ((rsp_71_40   & 0xff000000) >> 24);
 476                 cmd->response[2] = ((rsp_71_40   & 0x00ffffff) << 8) |
 477                                    ((rsp_39_8    & 0xff000000) >> 24);
 478                 cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 479         } else {
 480                 /* bit 39-8 */
 481                 cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
 482         }
 483
 484         if (data) {
 485                 /* use DMA if the HW supports it and the buffer is aligned */
 486                 if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
 487                     matsu_sd_addr_is_dmaable((long)data->src))
 488                         ret = matsu_sd_dma_xfer(dev, data);
 489                 else
 490                         ret = matsu_sd_pio_xfer(dev, data);
 491
 492                 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 493                                                MATSU_SD_INFO1_CMP);
 494                 if (ret)
 495                         return ret;
 496         }
 497
 498         return ret;
 499 }
 500
 501 static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
 502                                      struct mmc *mmc)
 503 {
 504         u32 val, tmp;
 505
 506         switch (mmc->bus_width) {
 507         case 1:
 508                 val = MATSU_SD_OPTION_WIDTH_1;
 509                 break;
 510         case 4:
 511                 val = MATSU_SD_OPTION_WIDTH_4;
 512                 break;
 513         case 8:
 514                 val = MATSU_SD_OPTION_WIDTH_8;
 515                 break;
 516         default:
 517                 return -EINVAL;
 518         }
 519
 520         tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
 521         tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
 522         tmp |= val;
 523         matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
 524
 525         return 0;
 526 }
 527
 528 static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
 529                                      struct mmc *mmc)
 530 {
 531         u32 tmp;
 532
 533         tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
 534         if (mmc->ddr_mode)
 535                 tmp |= MATSU_SD_IF_MODE_DDR;
 536         else
 537                 tmp &= ~MATSU_SD_IF_MODE_DDR;
 538         matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
 539 }
 540
 541 static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
 542                                      struct mmc *mmc)
 543 {
 544         unsigned int divisor;
 545         u32 val, tmp;
 546
 547         if (!mmc->clock)
 548                 return;
 549
 550         divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
 551
 552         if (divisor <= 1)
 553                 val = (priv->caps & MATSU_SD_CAP_RCAR) ?
 554                       MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1;
 555         else if (divisor <= 2)
 556                 val = MATSU_SD_CLKCTL_DIV2;
 557         else if (divisor <= 4)
 558                 val = MATSU_SD_CLKCTL_DIV4;
 559         else if (divisor <= 8)
 560                 val = MATSU_SD_CLKCTL_DIV8;
 561         else if (divisor <= 16)
 562                 val = MATSU_SD_CLKCTL_DIV16;
 563         else if (divisor <= 32)
 564                 val = MATSU_SD_CLKCTL_DIV32;
 565         else if (divisor <= 64)
 566                 val = MATSU_SD_CLKCTL_DIV64;
 567         else if (divisor <= 128)
 568                 val = MATSU_SD_CLKCTL_DIV128;
 569         else if (divisor <= 256)
 570                 val = MATSU_SD_CLKCTL_DIV256;
 571         else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
 572                 val = MATSU_SD_CLKCTL_DIV512;
 573         else
 574                 val = MATSU_SD_CLKCTL_DIV1024;
 575
 576         tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
 577         if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
 578             (tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
 579                 return;
 580
 581         /* stop the clock before changing its rate to avoid a glitch signal */
 582         tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
 583         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 584
 585         tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
 586         tmp |= val | MATSU_SD_CLKCTL_OFFEN;
 587         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 588
 589         tmp |= MATSU_SD_CLKCTL_SCLKEN;
 590         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 591
 592         udelay(1000);
 593 }
 594
 595 int matsu_sd_set_ios(struct udevice *dev)
 596 {
 597         struct matsu_sd_priv *priv = dev_get_priv(dev);
 598         struct mmc *mmc = mmc_get_mmc_dev(dev);
 599         int ret;
 600
 601         dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
 602                 mmc->clock, mmc->ddr_mode, mmc->bus_width);
 603
 604         ret = matsu_sd_set_bus_width(priv, mmc);
 605         if (ret)
 606                 return ret;
 607         matsu_sd_set_ddr_mode(priv, mmc);
 608         matsu_sd_set_clk_rate(priv, mmc);
 609
 610         return 0;
 611 }
 612
 613 int matsu_sd_get_cd(struct udevice *dev)
 614 {
 615         struct matsu_sd_priv *priv = dev_get_priv(dev);
 616
 617         if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
 618                 return 1;
 619
 620         return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
 621                   MATSU_SD_INFO1_CD);
 622 }
 623
 624 static void matsu_sd_host_init(struct matsu_sd_priv *priv)
 625 {
 626         u32 tmp;
 627
 628         /* soft reset of the host */
 629         tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
 630         tmp &= ~MATSU_SD_SOFT_RST_RSTX;
 631         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 632         tmp |= MATSU_SD_SOFT_RST_RSTX;
 633         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 634
 635         /* FIXME: implement eMMC hw_reset */
 636
 637         matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
 638
 639         /*
 640          * Connected to 32bit AXI.
 641          * This register dropped backward compatibility at version 0x10.
 642          * Write an appropriate value depending on the IP version.
 643          */
 644         if (priv->version >= 0x10)
 645                 matsu_sd_writel(priv, 0x101, MATSU_SD_HOST_MODE);
 646         else if (priv->caps & MATSU_SD_CAP_16BIT)
 647                 matsu_sd_writel(priv, 0x1, MATSU_SD_HOST_MODE);
 648         else
 649                 matsu_sd_writel(priv, 0x0, MATSU_SD_HOST_MODE);
 650
 651         if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
 652                 tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 653                 tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
 654                 matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 655         }
 656 }
 657
 658 int matsu_sd_bind(struct udevice *dev)
 659 {
 660         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 661
 662         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 663 }
 664
 665 int matsu_sd_probe(struct udevice *dev, u32 quirks)
 666 {
 667         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 668         struct matsu_sd_priv *priv = dev_get_priv(dev);
 669         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 670         fdt_addr_t base;
 671         struct clk clk;
 672         int ret;
 673 #ifdef CONFIG_DM_REGULATOR
 674         struct udevice *vqmmc_dev;
 675 #endif
 676
 677         base = devfdt_get_addr(dev);
 678         if (base == FDT_ADDR_T_NONE)
 679                 return -EINVAL;
 680
 681         priv->regbase = devm_ioremap(dev, base, SZ_2K);
 682         if (!priv->regbase)
 683                 return -ENOMEM;
 684
 685 #ifdef CONFIG_DM_REGULATOR
 686         ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
 687         if (!ret) {
 688                 /* Set the regulator to 3.3V until we support 1.8V modes */
 689                 regulator_set_value(vqmmc_dev, 3300000);
 690                 regulator_set_enable(vqmmc_dev, true);
 691         }
 692 #endif
 693
 694         ret = clk_get_by_index(dev, 0, &clk);
 695         if (ret < 0) {
 696                 dev_err(dev, "failed to get host clock\n");
 697                 return ret;
 698         }
 699
 700         /* set to max rate */
 701         priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 702         if (IS_ERR_VALUE(priv->mclk)) {
 703                 dev_err(dev, "failed to set rate for host clock\n");
 704                 clk_free(&clk);
 705                 return priv->mclk;
 706         }
 707
 708         ret = clk_enable(&clk);
 709         clk_free(&clk);
 710         if (ret) {
 711                 dev_err(dev, "failed to enable host clock\n");
 712                 return ret;
 713         }
 714
 715         ret = mmc_of_parse(dev, &plat->cfg);
 716         if (ret < 0) {
 717                 dev_err(dev, "failed to parse host caps\n");
 718                 return ret;
 719         }
 720
 721         plat->cfg.name = dev->name;
 722         plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 723
 724         if (quirks) {
 725                 priv->caps = quirks;
 726         } else {
 727                 priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
 728                                                         MATSU_SD_VERSION_IP;
 729                 dev_dbg(dev, "version %x\n", priv->version);
 730                 if (priv->version >= 0x10) {
 731                         priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
 732                         priv->caps |= MATSU_SD_CAP_DIV1024;
 733                 }
 734         }
 735
 736         if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 737                              NULL))
 738                 priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
 739
 740         matsu_sd_host_init(priv);
 741
 742         plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 743         plat->cfg.f_min = priv->mclk /
 744                         (priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
 745         plat->cfg.f_max = priv->mclk;
 746         plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
 747
 748         upriv->mmc = &plat->mmc;
 749
 750         return 0;
 751 }