2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compat.h>
14 #include <linux/dma-direction.h>
16 #include <linux/sizes.h>
17 #include <power/regulator.h>
18 #include <asm/unaligned.h>
20 #include "matsushita-common.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
26 return readq(priv->regbase + (reg << 1));
29 static void matsu_sd_writeq(struct matsu_sd_priv *priv,
30 u64 val, unsigned int reg)
32 writeq(val, priv->regbase + (reg << 1));
35 static u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
37 if (priv->caps & MATSU_SD_CAP_64BIT)
38 return readl(priv->regbase + (reg << 1));
40 return readl(priv->regbase + reg);
43 static void matsu_sd_writel(struct matsu_sd_priv *priv,
44 u32 val, unsigned int reg)
46 if (priv->caps & MATSU_SD_CAP_64BIT)
47 writel(val, priv->regbase + (reg << 1));
49 writel(val, priv->regbase + reg);
52 static dma_addr_t __dma_map_single(void *ptr, size_t size,
53 enum dma_data_direction dir)
55 unsigned long addr = (unsigned long)ptr;
57 if (dir == DMA_FROM_DEVICE)
58 invalidate_dcache_range(addr, addr + size);
60 flush_dcache_range(addr, addr + size);
65 static void __dma_unmap_single(dma_addr_t addr, size_t size,
66 enum dma_data_direction dir)
68 if (dir != DMA_TO_DEVICE)
69 invalidate_dcache_range(addr, addr + size);
72 static int matsu_sd_check_error(struct udevice *dev)
74 struct matsu_sd_priv *priv = dev_get_priv(dev);
75 u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
77 if (info2 & MATSU_SD_INFO2_ERR_RTO) {
79 * TIMEOUT must be returned for unsupported command. Do not
80 * display error log since this might be a part of sequence to
81 * distinguish between SD and MMC.
86 if (info2 & MATSU_SD_INFO2_ERR_TO) {
87 dev_err(dev, "timeout error\n");
91 if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
92 MATSU_SD_INFO2_ERR_IDX)) {
93 dev_err(dev, "communication out of sync\n");
97 if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
98 MATSU_SD_INFO2_ERR_ILW)) {
99 dev_err(dev, "illegal access\n");
106 static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
109 struct matsu_sd_priv *priv = dev_get_priv(dev);
113 while (!(matsu_sd_readl(priv, reg) & flag)) {
115 dev_err(dev, "timeout\n");
119 ret = matsu_sd_check_error(dev);
129 #define matsu_pio_read_fifo(__width, __suffix) \
130 static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv, \
131 char *pbuf, uint blksz) \
133 u##__width *buf = (u##__width *)pbuf; \
136 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
137 for (i = 0; i < blksz / ((__width) / 8); i++) { \
138 *buf++ = matsu_sd_read##__suffix(priv, \
142 for (i = 0; i < blksz / ((__width) / 8); i++) { \
144 data = matsu_sd_read##__suffix(priv, \
146 put_unaligned(data, buf++); \
151 matsu_pio_read_fifo(64, q)
152 matsu_pio_read_fifo(32, l)
154 static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
157 struct matsu_sd_priv *priv = dev_get_priv(dev);
160 /* wait until the buffer is filled with data */
161 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
167 * Clear the status flag _before_ read the buffer out because
168 * MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
170 matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
172 if (priv->caps & MATSU_SD_CAP_64BIT)
173 matsu_pio_read_fifo_64(priv, pbuf, blocksize);
175 matsu_pio_read_fifo_32(priv, pbuf, blocksize);
180 #define matsu_pio_write_fifo(__width, __suffix) \
181 static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv, \
182 const char *pbuf, uint blksz)\
184 const u##__width *buf = (const u##__width *)pbuf; \
187 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
188 for (i = 0; i < blksz / ((__width) / 8); i++) { \
189 matsu_sd_write##__suffix(priv, *buf++, \
193 for (i = 0; i < blksz / ((__width) / 8); i++) { \
194 u##__width data = get_unaligned(buf++); \
195 matsu_sd_write##__suffix(priv, data, \
201 matsu_pio_write_fifo(64, q)
202 matsu_pio_write_fifo(32, l)
204 static int matsu_sd_pio_write_one_block(struct udevice *dev,
205 const char *pbuf, uint blocksize)
207 struct matsu_sd_priv *priv = dev_get_priv(dev);
210 /* wait until the buffer becomes empty */
211 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
216 matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
218 if (priv->caps & MATSU_SD_CAP_64BIT)
219 matsu_pio_write_fifo_64(priv, pbuf, blocksize);
221 matsu_pio_write_fifo_32(priv, pbuf, blocksize);
226 static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
228 const char *src = data->src;
229 char *dest = data->dest;
232 for (i = 0; i < data->blocks; i++) {
233 if (data->flags & MMC_DATA_READ)
234 ret = matsu_sd_pio_read_one_block(dev, dest,
237 ret = matsu_sd_pio_write_one_block(dev, src,
242 if (data->flags & MMC_DATA_READ)
243 dest += data->blocksize;
245 src += data->blocksize;
251 static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
256 matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
257 matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
260 tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
261 tmp |= MATSU_SD_EXTMODE_DMA_EN;
262 matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
264 matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
266 /* suppress the warning "right shift count >= width of type" */
267 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
269 matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
271 matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
274 static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
277 struct matsu_sd_priv *priv = dev_get_priv(dev);
278 long wait = 1000000 + 10 * blocks;
280 while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
282 dev_err(dev, "timeout during DMA\n");
289 if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
290 dev_err(dev, "error during DMA\n");
297 static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
299 struct matsu_sd_priv *priv = dev_get_priv(dev);
300 size_t len = data->blocks * data->blocksize;
302 enum dma_data_direction dir;
307 tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
309 if (data->flags & MMC_DATA_READ) {
311 dir = DMA_FROM_DEVICE;
312 poll_flag = MATSU_SD_DMA_INFO1_END_RD2;
313 tmp |= MATSU_SD_DMA_MODE_DIR_RD;
315 buf = (void *)data->src;
317 poll_flag = MATSU_SD_DMA_INFO1_END_WR;
318 tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
321 matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
323 dma_addr = __dma_map_single(buf, len, dir);
325 matsu_sd_dma_start(priv, dma_addr);
327 ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
329 __dma_unmap_single(dma_addr, len, dir);
334 /* check if the address is DMA'able */
335 static bool matsu_sd_addr_is_dmaable(unsigned long addr)
337 if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
340 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
341 defined(CONFIG_SPL_BUILD)
343 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
344 * of L2, which is unreachable from the DMA engine.
346 if (addr < CONFIG_SPL_STACK)
353 int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
354 struct mmc_data *data)
356 struct matsu_sd_priv *priv = dev_get_priv(dev);
360 if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
361 dev_err(dev, "command busy\n");
365 /* clear all status flags */
366 matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
367 matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
369 /* disable DMA once */
370 tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
371 tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
372 matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
374 matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
379 matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
380 matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
382 /* Do not send CMD12 automatically */
383 tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
385 if (data->blocks > 1)
386 tmp |= MATSU_SD_CMD_MULTI;
388 if (data->flags & MMC_DATA_READ)
389 tmp |= MATSU_SD_CMD_RD;
393 * Do not use the response type auto-detection on this hardware.
394 * CMD8, for example, has different response types on SD and eMMC,
395 * while this controller always assumes the response type for SD.
396 * Set the response type manually.
398 switch (cmd->resp_type) {
400 tmp |= MATSU_SD_CMD_RSP_NONE;
403 tmp |= MATSU_SD_CMD_RSP_R1;
406 tmp |= MATSU_SD_CMD_RSP_R1B;
409 tmp |= MATSU_SD_CMD_RSP_R2;
412 tmp |= MATSU_SD_CMD_RSP_R3;
415 dev_err(dev, "unknown response type\n");
419 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
420 cmd->cmdidx, tmp, cmd->cmdarg);
421 matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
423 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
428 if (cmd->resp_type & MMC_RSP_136) {
429 u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
430 u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
431 u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
432 u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
434 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
435 ((rsp_103_72 & 0xff000000) >> 24);
436 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
437 ((rsp_71_40 & 0xff000000) >> 24);
438 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
439 ((rsp_39_8 & 0xff000000) >> 24);
440 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
443 cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
447 /* use DMA if the HW supports it and the buffer is aligned */
448 if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
449 matsu_sd_addr_is_dmaable((long)data->src))
450 ret = matsu_sd_dma_xfer(dev, data);
452 ret = matsu_sd_pio_xfer(dev, data);
454 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
463 static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
468 switch (mmc->bus_width) {
470 val = MATSU_SD_OPTION_WIDTH_1;
473 val = MATSU_SD_OPTION_WIDTH_4;
476 val = MATSU_SD_OPTION_WIDTH_8;
482 tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
483 tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
485 matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
490 static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
495 tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
497 tmp |= MATSU_SD_IF_MODE_DDR;
499 tmp &= ~MATSU_SD_IF_MODE_DDR;
500 matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
503 static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
506 unsigned int divisor;
512 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
515 val = MATSU_SD_CLKCTL_DIV1;
516 else if (divisor <= 2)
517 val = MATSU_SD_CLKCTL_DIV2;
518 else if (divisor <= 4)
519 val = MATSU_SD_CLKCTL_DIV4;
520 else if (divisor <= 8)
521 val = MATSU_SD_CLKCTL_DIV8;
522 else if (divisor <= 16)
523 val = MATSU_SD_CLKCTL_DIV16;
524 else if (divisor <= 32)
525 val = MATSU_SD_CLKCTL_DIV32;
526 else if (divisor <= 64)
527 val = MATSU_SD_CLKCTL_DIV64;
528 else if (divisor <= 128)
529 val = MATSU_SD_CLKCTL_DIV128;
530 else if (divisor <= 256)
531 val = MATSU_SD_CLKCTL_DIV256;
532 else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
533 val = MATSU_SD_CLKCTL_DIV512;
535 val = MATSU_SD_CLKCTL_DIV1024;
537 tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
538 if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
539 (tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
542 /* stop the clock before changing its rate to avoid a glitch signal */
543 tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
544 matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
546 tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
547 tmp |= val | MATSU_SD_CLKCTL_OFFEN;
548 matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
550 tmp |= MATSU_SD_CLKCTL_SCLKEN;
551 matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
556 int matsu_sd_set_ios(struct udevice *dev)
558 struct matsu_sd_priv *priv = dev_get_priv(dev);
559 struct mmc *mmc = mmc_get_mmc_dev(dev);
562 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
563 mmc->clock, mmc->ddr_mode, mmc->bus_width);
565 ret = matsu_sd_set_bus_width(priv, mmc);
568 matsu_sd_set_ddr_mode(priv, mmc);
569 matsu_sd_set_clk_rate(priv, mmc);
574 int matsu_sd_get_cd(struct udevice *dev)
576 struct matsu_sd_priv *priv = dev_get_priv(dev);
578 if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
581 return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
585 static void matsu_sd_host_init(struct matsu_sd_priv *priv)
589 /* soft reset of the host */
590 tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
591 tmp &= ~MATSU_SD_SOFT_RST_RSTX;
592 matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
593 tmp |= MATSU_SD_SOFT_RST_RSTX;
594 matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
596 /* FIXME: implement eMMC hw_reset */
598 matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
601 * Connected to 32bit AXI.
602 * This register dropped backward compatibility at version 0x10.
603 * Write an appropriate value depending on the IP version.
605 matsu_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
608 if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
609 tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
610 tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
611 matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
615 int matsu_sd_bind(struct udevice *dev)
617 struct matsu_sd_plat *plat = dev_get_platdata(dev);
619 return mmc_bind(dev, &plat->mmc, &plat->cfg);
622 int matsu_sd_probe(struct udevice *dev)
624 struct matsu_sd_plat *plat = dev_get_platdata(dev);
625 struct matsu_sd_priv *priv = dev_get_priv(dev);
626 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
627 const u32 quirks = dev_get_driver_data(dev);
631 #ifdef CONFIG_DM_REGULATOR
632 struct udevice *vqmmc_dev;
635 base = devfdt_get_addr(dev);
636 if (base == FDT_ADDR_T_NONE)
639 priv->regbase = devm_ioremap(dev, base, SZ_2K);
643 #ifdef CONFIG_DM_REGULATOR
644 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
646 /* Set the regulator to 3.3V until we support 1.8V modes */
647 regulator_set_value(vqmmc_dev, 3300000);
648 regulator_set_enable(vqmmc_dev, true);
652 ret = clk_get_by_index(dev, 0, &clk);
654 dev_err(dev, "failed to get host clock\n");
658 /* set to max rate */
659 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
660 if (IS_ERR_VALUE(priv->mclk)) {
661 dev_err(dev, "failed to set rate for host clock\n");
666 ret = clk_enable(&clk);
669 dev_err(dev, "failed to enable host clock\n");
673 plat->cfg.name = dev->name;
674 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
676 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
679 plat->cfg.host_caps |= MMC_MODE_8BIT;
682 plat->cfg.host_caps |= MMC_MODE_4BIT;
687 dev_err(dev, "Invalid \"bus-width\" value\n");
694 priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
696 dev_dbg(dev, "version %x\n", priv->version);
697 if (priv->version >= 0x10) {
698 priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
699 priv->caps |= MATSU_SD_CAP_DIV1024;
703 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
705 priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
707 matsu_sd_host_init(priv);
709 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
710 plat->cfg.f_min = priv->mclk /
711 (priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
712 plat->cfg.f_max = priv->mclk;
713 plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
715 upriv->mmc = &plat->mmc;