1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, Freescale Semiconductor, Inc
6 * Based vaguely on the Linux code
13 #include <dm/device-internal.h>
17 #include <power/regulator.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
25 static int mmc_power_cycle(struct mmc *mmc);
26 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
28 #if CONFIG_IS_ENABLED(MMC_TINY)
29 static struct mmc mmc_static;
30 struct mmc *find_mmc_device(int dev_num)
35 void mmc_do_preinit(void)
37 struct mmc *m = &mmc_static;
38 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
39 mmc_set_preinit(m, 1);
45 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
47 return &mmc->block_dev;
51 #if !CONFIG_IS_ENABLED(DM_MMC)
53 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
54 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
60 __weak int board_mmc_getwp(struct mmc *mmc)
65 int mmc_getwp(struct mmc *mmc)
69 wp = board_mmc_getwp(mmc);
72 if (mmc->cfg->ops->getwp)
73 wp = mmc->cfg->ops->getwp(mmc);
81 __weak int board_mmc_getcd(struct mmc *mmc)
87 #ifdef CONFIG_MMC_TRACE
88 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
90 printf("CMD_SEND:%d\n", cmd->cmdidx);
91 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
94 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
100 printf("\t\tRET\t\t\t %d\n", ret);
102 switch (cmd->resp_type) {
104 printf("\t\tMMC_RSP_NONE\n");
107 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
111 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
115 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
117 printf("\t\t \t\t 0x%08X \n",
119 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t \t\t 0x%08X \n",
124 printf("\t\t\t\t\tDUMPING DATA\n");
125 for (i = 0; i < 4; i++) {
127 printf("\t\t\t\t\t%03d - ", i*4);
128 ptr = (u8 *)&cmd->response[i];
130 for (j = 0; j < 4; j++)
131 printf("%02X ", *ptr--);
136 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
140 printf("\t\tERROR MMC rsp not supported\n");
146 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
150 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
151 printf("CURR STATE:%d\n", status);
155 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
156 const char *mmc_mode_name(enum bus_mode mode)
158 static const char *const names[] = {
159 [MMC_LEGACY] = "MMC legacy",
160 [SD_LEGACY] = "SD Legacy",
161 [MMC_HS] = "MMC High Speed (26MHz)",
162 [SD_HS] = "SD High Speed (50MHz)",
163 [UHS_SDR12] = "UHS SDR12 (25MHz)",
164 [UHS_SDR25] = "UHS SDR25 (50MHz)",
165 [UHS_SDR50] = "UHS SDR50 (100MHz)",
166 [UHS_SDR104] = "UHS SDR104 (208MHz)",
167 [UHS_DDR50] = "UHS DDR50 (50MHz)",
168 [MMC_HS_52] = "MMC High Speed (52MHz)",
169 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
170 [MMC_HS_200] = "HS200 (200MHz)",
173 if (mode >= MMC_MODES_END)
174 return "Unknown mode";
180 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
182 static const int freqs[] = {
183 [MMC_LEGACY] = 25000000,
184 [SD_LEGACY] = 25000000,
187 [MMC_HS_52] = 52000000,
188 [MMC_DDR_52] = 52000000,
189 [UHS_SDR12] = 25000000,
190 [UHS_SDR25] = 50000000,
191 [UHS_SDR50] = 100000000,
192 [UHS_DDR50] = 50000000,
193 [UHS_SDR104] = 208000000,
194 [MMC_HS_200] = 200000000,
197 if (mode == MMC_LEGACY)
198 return mmc->legacy_speed;
199 else if (mode >= MMC_MODES_END)
205 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
207 mmc->selected_mode = mode;
208 mmc->tran_speed = mmc_mode2freq(mmc, mode);
209 mmc->ddr_mode = mmc_is_mode_ddr(mode);
210 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
211 mmc->tran_speed / 1000000);
215 #if !CONFIG_IS_ENABLED(DM_MMC)
216 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
220 mmmc_trace_before_send(mmc, cmd);
221 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
222 mmmc_trace_after_send(mmc, cmd, ret);
228 int mmc_send_status(struct mmc *mmc, int timeout)
231 int err, retries = 5;
233 cmd.cmdidx = MMC_CMD_SEND_STATUS;
234 cmd.resp_type = MMC_RSP_R1;
235 if (!mmc_host_is_spi(mmc))
236 cmd.cmdarg = mmc->rca << 16;
239 err = mmc_send_cmd(mmc, &cmd, NULL);
241 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
242 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
246 if (cmd.response[0] & MMC_STATUS_MASK) {
247 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
248 pr_err("Status Error: 0x%08X\n",
253 } else if (--retries < 0)
262 mmc_trace_state(mmc, &cmd);
264 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
265 pr_err("Timeout waiting card ready\n");
273 int mmc_set_blocklen(struct mmc *mmc, int len)
281 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
282 cmd.resp_type = MMC_RSP_R1;
285 err = mmc_send_cmd(mmc, &cmd, NULL);
287 #ifdef CONFIG_MMC_QUIRKS
288 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
291 * It has been seen that SET_BLOCKLEN may fail on the first
292 * attempt, let's try a few more time
295 err = mmc_send_cmd(mmc, &cmd, NULL);
305 #ifdef MMC_SUPPORTS_TUNING
306 static const u8 tuning_blk_pattern_4bit[] = {
307 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
308 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
309 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
310 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
311 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
312 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
313 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
314 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
317 static const u8 tuning_blk_pattern_8bit[] = {
318 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
319 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
320 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
321 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
322 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
323 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
324 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
325 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
326 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
327 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
328 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
329 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
330 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
331 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
332 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
333 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
336 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
339 struct mmc_data data;
340 const u8 *tuning_block_pattern;
343 if (mmc->bus_width == 8) {
344 tuning_block_pattern = tuning_blk_pattern_8bit;
345 size = sizeof(tuning_blk_pattern_8bit);
346 } else if (mmc->bus_width == 4) {
347 tuning_block_pattern = tuning_blk_pattern_4bit;
348 size = sizeof(tuning_blk_pattern_4bit);
353 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
357 cmd.resp_type = MMC_RSP_R1;
359 data.dest = (void *)data_buf;
361 data.blocksize = size;
362 data.flags = MMC_DATA_READ;
364 err = mmc_send_cmd(mmc, &cmd, &data);
368 if (memcmp(data_buf, tuning_block_pattern, size))
375 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
379 struct mmc_data data;
382 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
384 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
386 if (mmc->high_capacity)
389 cmd.cmdarg = start * mmc->read_bl_len;
391 cmd.resp_type = MMC_RSP_R1;
394 data.blocks = blkcnt;
395 data.blocksize = mmc->read_bl_len;
396 data.flags = MMC_DATA_READ;
398 if (mmc_send_cmd(mmc, &cmd, &data))
402 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
404 cmd.resp_type = MMC_RSP_R1b;
405 if (mmc_send_cmd(mmc, &cmd, NULL)) {
406 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
407 pr_err("mmc fail to send stop cmd\n");
416 #if CONFIG_IS_ENABLED(BLK)
417 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
419 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
423 #if CONFIG_IS_ENABLED(BLK)
424 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
426 int dev_num = block_dev->devnum;
428 lbaint_t cur, blocks_todo = blkcnt;
433 struct mmc *mmc = find_mmc_device(dev_num);
437 if (CONFIG_IS_ENABLED(MMC_TINY))
438 err = mmc_switch_part(mmc, block_dev->hwpart);
440 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
445 if ((start + blkcnt) > block_dev->lba) {
446 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
447 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
448 start + blkcnt, block_dev->lba);
453 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
454 pr_debug("%s: Failed to set blocklen\n", __func__);
459 cur = (blocks_todo > mmc->cfg->b_max) ?
460 mmc->cfg->b_max : blocks_todo;
461 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
462 pr_debug("%s: Failed to read blocks\n", __func__);
467 dst += cur * mmc->read_bl_len;
468 } while (blocks_todo > 0);
473 static int mmc_go_idle(struct mmc *mmc)
480 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
482 cmd.resp_type = MMC_RSP_NONE;
484 err = mmc_send_cmd(mmc, &cmd, NULL);
494 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
495 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
501 * Send CMD11 only if the request is to switch the card to
504 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
505 return mmc_set_signal_voltage(mmc, signal_voltage);
507 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
509 cmd.resp_type = MMC_RSP_R1;
511 err = mmc_send_cmd(mmc, &cmd, NULL);
515 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
519 * The card should drive cmd and dat[0:3] low immediately
520 * after the response of cmd11, but wait 100 us to be sure
522 err = mmc_wait_dat0(mmc, 0, 100);
529 * During a signal voltage level switch, the clock must be gated
530 * for 5 ms according to the SD spec
532 mmc_set_clock(mmc, mmc->clock, true);
534 err = mmc_set_signal_voltage(mmc, signal_voltage);
538 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
540 mmc_set_clock(mmc, mmc->clock, false);
543 * Failure to switch is indicated by the card holding
544 * dat[0:3] low. Wait for at least 1 ms according to spec
546 err = mmc_wait_dat0(mmc, 1, 1000);
556 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
563 cmd.cmdidx = MMC_CMD_APP_CMD;
564 cmd.resp_type = MMC_RSP_R1;
567 err = mmc_send_cmd(mmc, &cmd, NULL);
572 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
573 cmd.resp_type = MMC_RSP_R3;
576 * Most cards do not answer if some reserved bits
577 * in the ocr are set. However, Some controller
578 * can set bit 7 (reserved for low voltages), but
579 * how to manage low voltages SD card is not yet
582 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
583 (mmc->cfg->voltages & 0xff8000);
585 if (mmc->version == SD_VERSION_2)
586 cmd.cmdarg |= OCR_HCS;
589 cmd.cmdarg |= OCR_S18R;
591 err = mmc_send_cmd(mmc, &cmd, NULL);
596 if (cmd.response[0] & OCR_BUSY)
605 if (mmc->version != SD_VERSION_2)
606 mmc->version = SD_VERSION_1_0;
608 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
609 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
610 cmd.resp_type = MMC_RSP_R3;
613 err = mmc_send_cmd(mmc, &cmd, NULL);
619 mmc->ocr = cmd.response[0];
621 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
622 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
624 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
630 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
636 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
641 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
642 cmd.resp_type = MMC_RSP_R3;
644 if (use_arg && !mmc_host_is_spi(mmc))
645 cmd.cmdarg = OCR_HCS |
646 (mmc->cfg->voltages &
647 (mmc->ocr & OCR_VOLTAGE_MASK)) |
648 (mmc->ocr & OCR_ACCESS_MODE);
650 err = mmc_send_cmd(mmc, &cmd, NULL);
653 mmc->ocr = cmd.response[0];
657 static int mmc_send_op_cond(struct mmc *mmc)
661 /* Some cards seem to need this */
664 /* Asking to the card its capabilities */
665 for (i = 0; i < 2; i++) {
666 err = mmc_send_op_cond_iter(mmc, i != 0);
670 /* exit if not busy (flag seems to be inverted) */
671 if (mmc->ocr & OCR_BUSY)
674 mmc->op_cond_pending = 1;
678 static int mmc_complete_op_cond(struct mmc *mmc)
685 mmc->op_cond_pending = 0;
686 if (!(mmc->ocr & OCR_BUSY)) {
687 /* Some cards seem to need this */
690 start = get_timer(0);
692 err = mmc_send_op_cond_iter(mmc, 1);
695 if (mmc->ocr & OCR_BUSY)
697 if (get_timer(start) > timeout)
703 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
704 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
705 cmd.resp_type = MMC_RSP_R3;
708 err = mmc_send_cmd(mmc, &cmd, NULL);
713 mmc->ocr = cmd.response[0];
716 mmc->version = MMC_VERSION_UNKNOWN;
718 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
725 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
728 struct mmc_data data;
731 /* Get the Card Status Register */
732 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
733 cmd.resp_type = MMC_RSP_R1;
736 data.dest = (char *)ext_csd;
738 data.blocksize = MMC_MAX_BLOCK_LEN;
739 data.flags = MMC_DATA_READ;
741 err = mmc_send_cmd(mmc, &cmd, &data);
746 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
753 cmd.cmdidx = MMC_CMD_SWITCH;
754 cmd.resp_type = MMC_RSP_R1b;
755 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
759 while (retries > 0) {
760 ret = mmc_send_cmd(mmc, &cmd, NULL);
762 /* Waiting for the ready status */
764 ret = mmc_send_status(mmc, timeout);
775 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
780 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
786 speed_bits = EXT_CSD_TIMING_HS;
788 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
790 speed_bits = EXT_CSD_TIMING_HS200;
794 speed_bits = EXT_CSD_TIMING_LEGACY;
799 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
804 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
805 /* Now check to see that it worked */
806 err = mmc_send_ext_csd(mmc, test_csd);
810 /* No high-speed support */
811 if (!test_csd[EXT_CSD_HS_TIMING])
818 static int mmc_get_capabilities(struct mmc *mmc)
820 u8 *ext_csd = mmc->ext_csd;
823 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
825 if (mmc_host_is_spi(mmc))
828 /* Only version 4 supports high-speed */
829 if (mmc->version < MMC_VERSION_4)
833 pr_err("No ext_csd found!\n"); /* this should enver happen */
837 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
839 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
840 mmc->cardtype = cardtype;
842 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
843 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
844 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
845 mmc->card_caps |= MMC_MODE_HS200;
848 if (cardtype & EXT_CSD_CARD_TYPE_52) {
849 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
850 mmc->card_caps |= MMC_MODE_DDR_52MHz;
851 mmc->card_caps |= MMC_MODE_HS_52MHz;
853 if (cardtype & EXT_CSD_CARD_TYPE_26)
854 mmc->card_caps |= MMC_MODE_HS;
859 static int mmc_set_capacity(struct mmc *mmc, int part_num)
863 mmc->capacity = mmc->capacity_user;
867 mmc->capacity = mmc->capacity_boot;
870 mmc->capacity = mmc->capacity_rpmb;
876 mmc->capacity = mmc->capacity_gp[part_num - 4];
882 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
887 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
888 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
893 if (part_num & PART_ACCESS_MASK)
894 forbidden = MMC_CAP(MMC_HS_200);
896 if (MMC_CAP(mmc->selected_mode) & forbidden) {
897 pr_debug("selected mode (%s) is forbidden for part %d\n",
898 mmc_mode_name(mmc->selected_mode), part_num);
900 } else if (mmc->selected_mode != mmc->best_mode) {
901 pr_debug("selected mode is not optimal\n");
906 return mmc_select_mode_and_width(mmc,
907 mmc->card_caps & ~forbidden);
912 static inline int mmc_boot_part_access_chk(struct mmc *mmc,
913 unsigned int part_num)
919 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
923 ret = mmc_boot_part_access_chk(mmc, part_num);
927 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
928 (mmc->part_config & ~PART_ACCESS_MASK)
929 | (part_num & PART_ACCESS_MASK));
932 * Set the capacity if the switch succeeded or was intended
933 * to return to representing the raw device.
935 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
936 ret = mmc_set_capacity(mmc, part_num);
937 mmc_get_blk_desc(mmc)->hwpart = part_num;
943 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
944 int mmc_hwpart_config(struct mmc *mmc,
945 const struct mmc_hwpart_conf *conf,
946 enum mmc_hwpart_conf_mode mode)
952 u32 max_enh_size_mult;
953 u32 tot_enh_size_mult = 0;
956 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
958 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
961 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
962 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
966 if (!(mmc->part_support & PART_SUPPORT)) {
967 pr_err("Card does not support partitioning\n");
971 if (!mmc->hc_wp_grp_size) {
972 pr_err("Card does not define HC WP group size\n");
976 /* check partition alignment and total enhanced size */
977 if (conf->user.enh_size) {
978 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
979 conf->user.enh_start % mmc->hc_wp_grp_size) {
980 pr_err("User data enhanced area not HC WP group "
984 part_attrs |= EXT_CSD_ENH_USR;
985 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
986 if (mmc->high_capacity) {
987 enh_start_addr = conf->user.enh_start;
989 enh_start_addr = (conf->user.enh_start << 9);
995 tot_enh_size_mult += enh_size_mult;
997 for (pidx = 0; pidx < 4; pidx++) {
998 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
999 pr_err("GP%i partition not HC WP group size "
1000 "aligned\n", pidx+1);
1003 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1004 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1005 part_attrs |= EXT_CSD_ENH_GP(pidx);
1006 tot_enh_size_mult += gp_size_mult[pidx];
1010 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1011 pr_err("Card does not support enhanced attribute\n");
1012 return -EMEDIUMTYPE;
1015 err = mmc_send_ext_csd(mmc, ext_csd);
1020 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1021 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1022 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1023 if (tot_enh_size_mult > max_enh_size_mult) {
1024 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1025 tot_enh_size_mult, max_enh_size_mult);
1026 return -EMEDIUMTYPE;
1029 /* The default value of EXT_CSD_WR_REL_SET is device
1030 * dependent, the values can only be changed if the
1031 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1032 * changed only once and before partitioning is completed. */
1033 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1034 if (conf->user.wr_rel_change) {
1035 if (conf->user.wr_rel_set)
1036 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1038 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1040 for (pidx = 0; pidx < 4; pidx++) {
1041 if (conf->gp_part[pidx].wr_rel_change) {
1042 if (conf->gp_part[pidx].wr_rel_set)
1043 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1045 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1049 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1050 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1051 puts("Card does not support host controlled partition write "
1052 "reliability settings\n");
1053 return -EMEDIUMTYPE;
1056 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1057 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1058 pr_err("Card already partitioned\n");
1062 if (mode == MMC_HWPART_CONF_CHECK)
1065 /* Partitioning requires high-capacity size definitions */
1066 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1067 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1068 EXT_CSD_ERASE_GROUP_DEF, 1);
1073 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1075 /* update erase group size to be high-capacity */
1076 mmc->erase_grp_size =
1077 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1081 /* all OK, write the configuration */
1082 for (i = 0; i < 4; i++) {
1083 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1084 EXT_CSD_ENH_START_ADDR+i,
1085 (enh_start_addr >> (i*8)) & 0xFF);
1089 for (i = 0; i < 3; i++) {
1090 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1091 EXT_CSD_ENH_SIZE_MULT+i,
1092 (enh_size_mult >> (i*8)) & 0xFF);
1096 for (pidx = 0; pidx < 4; pidx++) {
1097 for (i = 0; i < 3; i++) {
1098 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1099 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1100 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1105 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1106 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1110 if (mode == MMC_HWPART_CONF_SET)
1113 /* The WR_REL_SET is a write-once register but shall be
1114 * written before setting PART_SETTING_COMPLETED. As it is
1115 * write-once we can only write it when completing the
1117 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1118 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1119 EXT_CSD_WR_REL_SET, wr_rel_set);
1124 /* Setting PART_SETTING_COMPLETED confirms the partition
1125 * configuration but it only becomes effective after power
1126 * cycle, so we do not adjust the partition related settings
1127 * in the mmc struct. */
1129 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1130 EXT_CSD_PARTITION_SETTING,
1131 EXT_CSD_PARTITION_SETTING_COMPLETED);
1139 #if !CONFIG_IS_ENABLED(DM_MMC)
1140 int mmc_getcd(struct mmc *mmc)
1144 cd = board_mmc_getcd(mmc);
1147 if (mmc->cfg->ops->getcd)
1148 cd = mmc->cfg->ops->getcd(mmc);
1157 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1160 struct mmc_data data;
1162 /* Switch the frequency */
1163 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1164 cmd.resp_type = MMC_RSP_R1;
1165 cmd.cmdarg = (mode << 31) | 0xffffff;
1166 cmd.cmdarg &= ~(0xf << (group * 4));
1167 cmd.cmdarg |= value << (group * 4);
1169 data.dest = (char *)resp;
1170 data.blocksize = 64;
1172 data.flags = MMC_DATA_READ;
1174 return mmc_send_cmd(mmc, &cmd, &data);
1178 static int sd_get_capabilities(struct mmc *mmc)
1182 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1183 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1184 struct mmc_data data;
1186 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1190 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1192 if (mmc_host_is_spi(mmc))
1195 /* Read the SCR to find out if this card supports higher speeds */
1196 cmd.cmdidx = MMC_CMD_APP_CMD;
1197 cmd.resp_type = MMC_RSP_R1;
1198 cmd.cmdarg = mmc->rca << 16;
1200 err = mmc_send_cmd(mmc, &cmd, NULL);
1205 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1206 cmd.resp_type = MMC_RSP_R1;
1212 data.dest = (char *)scr;
1215 data.flags = MMC_DATA_READ;
1217 err = mmc_send_cmd(mmc, &cmd, &data);
1226 mmc->scr[0] = __be32_to_cpu(scr[0]);
1227 mmc->scr[1] = __be32_to_cpu(scr[1]);
1229 switch ((mmc->scr[0] >> 24) & 0xf) {
1231 mmc->version = SD_VERSION_1_0;
1234 mmc->version = SD_VERSION_1_10;
1237 mmc->version = SD_VERSION_2;
1238 if ((mmc->scr[0] >> 15) & 0x1)
1239 mmc->version = SD_VERSION_3;
1242 mmc->version = SD_VERSION_1_0;
1246 if (mmc->scr[0] & SD_DATA_4BIT)
1247 mmc->card_caps |= MMC_MODE_4BIT;
1249 /* Version 1.0 doesn't support switching */
1250 if (mmc->version == SD_VERSION_1_0)
1255 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1256 (u8 *)switch_status);
1261 /* The high-speed function is busy. Try again */
1262 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1266 /* If high-speed isn't supported, we return */
1267 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1268 mmc->card_caps |= MMC_CAP(SD_HS);
1270 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1271 /* Version before 3.0 don't support UHS modes */
1272 if (mmc->version < SD_VERSION_3)
1275 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1276 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1277 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1278 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1279 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1280 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1281 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1282 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1283 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1284 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1285 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1291 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1295 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1300 speed = UHS_SDR12_BUS_SPEED;
1303 speed = HIGH_SPEED_BUS_SPEED;
1305 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1307 speed = UHS_SDR12_BUS_SPEED;
1310 speed = UHS_SDR25_BUS_SPEED;
1313 speed = UHS_SDR50_BUS_SPEED;
1316 speed = UHS_DDR50_BUS_SPEED;
1319 speed = UHS_SDR104_BUS_SPEED;
1326 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1330 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1336 static int sd_select_bus_width(struct mmc *mmc, int w)
1341 if ((w != 4) && (w != 1))
1344 cmd.cmdidx = MMC_CMD_APP_CMD;
1345 cmd.resp_type = MMC_RSP_R1;
1346 cmd.cmdarg = mmc->rca << 16;
1348 err = mmc_send_cmd(mmc, &cmd, NULL);
1352 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1353 cmd.resp_type = MMC_RSP_R1;
1358 err = mmc_send_cmd(mmc, &cmd, NULL);
1365 #if CONFIG_IS_ENABLED(MMC_WRITE)
1366 static int sd_read_ssr(struct mmc *mmc)
1368 static const unsigned int sd_au_size[] = {
1369 0, SZ_16K / 512, SZ_32K / 512,
1370 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1371 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1372 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1373 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1378 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1379 struct mmc_data data;
1381 unsigned int au, eo, et, es;
1383 cmd.cmdidx = MMC_CMD_APP_CMD;
1384 cmd.resp_type = MMC_RSP_R1;
1385 cmd.cmdarg = mmc->rca << 16;
1387 err = mmc_send_cmd(mmc, &cmd, NULL);
1391 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1392 cmd.resp_type = MMC_RSP_R1;
1396 data.dest = (char *)ssr;
1397 data.blocksize = 64;
1399 data.flags = MMC_DATA_READ;
1401 err = mmc_send_cmd(mmc, &cmd, &data);
1409 for (i = 0; i < 16; i++)
1410 ssr[i] = be32_to_cpu(ssr[i]);
1412 au = (ssr[2] >> 12) & 0xF;
1413 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1414 mmc->ssr.au = sd_au_size[au];
1415 es = (ssr[3] >> 24) & 0xFF;
1416 es |= (ssr[2] & 0xFF) << 8;
1417 et = (ssr[3] >> 18) & 0x3F;
1419 eo = (ssr[3] >> 16) & 0x3;
1420 mmc->ssr.erase_timeout = (et * 1000) / es;
1421 mmc->ssr.erase_offset = eo * 1000;
1424 pr_debug("Invalid Allocation Unit Size.\n");
1430 /* frequency bases */
1431 /* divided by 10 to be nice to platforms without floating point */
1432 static const int fbase[] = {
1439 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1440 * to platforms without floating point.
1442 static const u8 multipliers[] = {
1461 static inline int bus_width(uint cap)
1463 if (cap == MMC_MODE_8BIT)
1465 if (cap == MMC_MODE_4BIT)
1467 if (cap == MMC_MODE_1BIT)
1469 pr_warn("invalid bus witdh capability 0x%x\n", cap);
1473 #if !CONFIG_IS_ENABLED(DM_MMC)
1474 #ifdef MMC_SUPPORTS_TUNING
1475 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1481 static void mmc_send_init_stream(struct mmc *mmc)
1485 static int mmc_set_ios(struct mmc *mmc)
1489 if (mmc->cfg->ops->set_ios)
1490 ret = mmc->cfg->ops->set_ios(mmc);
1496 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1499 if (clock > mmc->cfg->f_max)
1500 clock = mmc->cfg->f_max;
1502 if (clock < mmc->cfg->f_min)
1503 clock = mmc->cfg->f_min;
1507 mmc->clk_disable = disable;
1509 return mmc_set_ios(mmc);
1512 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1514 mmc->bus_width = width;
1516 return mmc_set_ios(mmc);
1519 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1521 * helper function to display the capabilities in a human
1522 * friendly manner. The capabilities include bus width and
1525 void mmc_dump_capabilities(const char *text, uint caps)
1529 pr_debug("%s: widths [", text);
1530 if (caps & MMC_MODE_8BIT)
1532 if (caps & MMC_MODE_4BIT)
1534 if (caps & MMC_MODE_1BIT)
1536 pr_debug("\b\b] modes [");
1537 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1538 if (MMC_CAP(mode) & caps)
1539 pr_debug("%s, ", mmc_mode_name(mode));
1540 pr_debug("\b\b]\n");
1544 struct mode_width_tuning {
1547 #ifdef MMC_SUPPORTS_TUNING
1552 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1553 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1556 case MMC_SIGNAL_VOLTAGE_000: return 0;
1557 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1558 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1559 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1564 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1568 if (mmc->signal_voltage == signal_voltage)
1571 mmc->signal_voltage = signal_voltage;
1572 err = mmc_set_ios(mmc);
1574 pr_debug("unable to set voltage (err %d)\n", err);
1579 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1585 static const struct mode_width_tuning sd_modes_by_pref[] = {
1586 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1587 #ifdef MMC_SUPPORTS_TUNING
1590 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1591 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1596 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1600 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1604 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1609 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1611 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1614 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1619 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1623 #define for_each_sd_mode_by_pref(caps, mwt) \
1624 for (mwt = sd_modes_by_pref;\
1625 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1627 if (caps & MMC_CAP(mwt->mode))
1629 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1632 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1633 const struct mode_width_tuning *mwt;
1634 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1635 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1637 bool uhs_en = false;
1642 mmc_dump_capabilities("sd card", card_caps);
1643 mmc_dump_capabilities("host", mmc->host_caps);
1646 /* Restrict card's capabilities by what the host can do */
1647 caps = card_caps & mmc->host_caps;
1652 for_each_sd_mode_by_pref(caps, mwt) {
1655 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1656 if (*w & caps & mwt->widths) {
1657 pr_debug("trying mode %s width %d (at %d MHz)\n",
1658 mmc_mode_name(mwt->mode),
1660 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1662 /* configure the bus width (card + host) */
1663 err = sd_select_bus_width(mmc, bus_width(*w));
1666 mmc_set_bus_width(mmc, bus_width(*w));
1668 /* configure the bus mode (card) */
1669 err = sd_set_card_speed(mmc, mwt->mode);
1673 /* configure the bus mode (host) */
1674 mmc_select_mode(mmc, mwt->mode);
1675 mmc_set_clock(mmc, mmc->tran_speed, false);
1677 #ifdef MMC_SUPPORTS_TUNING
1678 /* execute tuning if needed */
1679 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1680 err = mmc_execute_tuning(mmc,
1683 pr_debug("tuning failed\n");
1689 #if CONFIG_IS_ENABLED(MMC_WRITE)
1690 err = sd_read_ssr(mmc);
1692 pr_warn("unable to read ssr\n");
1698 /* revert to a safer bus speed */
1699 mmc_select_mode(mmc, SD_LEGACY);
1700 mmc_set_clock(mmc, mmc->tran_speed, false);
1705 pr_err("unable to select a mode\n");
1710 * read the compare the part of ext csd that is constant.
1711 * This can be used to check that the transfer is working
1714 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1717 const u8 *ext_csd = mmc->ext_csd;
1718 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1720 if (mmc->version < MMC_VERSION_4)
1723 err = mmc_send_ext_csd(mmc, test_csd);
1727 /* Only compare read only fields */
1728 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1729 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1730 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1731 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1732 ext_csd[EXT_CSD_REV]
1733 == test_csd[EXT_CSD_REV] &&
1734 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1735 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1736 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1737 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1743 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1744 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1745 uint32_t allowed_mask)
1751 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1752 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1753 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1754 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1757 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1758 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1759 MMC_SIGNAL_VOLTAGE_180;
1760 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1761 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1764 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1768 while (card_mask & allowed_mask) {
1769 enum mmc_voltage best_match;
1771 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1772 if (!mmc_set_signal_voltage(mmc, best_match))
1775 allowed_mask &= ~best_match;
1781 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1782 uint32_t allowed_mask)
1788 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1789 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1792 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1793 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1798 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1802 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1806 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1810 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1814 #define for_each_mmc_mode_by_pref(caps, mwt) \
1815 for (mwt = mmc_modes_by_pref;\
1816 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1818 if (caps & MMC_CAP(mwt->mode))
1820 static const struct ext_csd_bus_width {
1824 } ext_csd_bus_width[] = {
1825 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1826 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1827 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1828 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1829 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1832 #define for_each_supported_width(caps, ddr, ecbv) \
1833 for (ecbv = ext_csd_bus_width;\
1834 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1836 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1838 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1841 const struct mode_width_tuning *mwt;
1842 const struct ext_csd_bus_width *ecbw;
1845 mmc_dump_capabilities("mmc", card_caps);
1846 mmc_dump_capabilities("host", mmc->host_caps);
1849 /* Restrict card's capabilities by what the host can do */
1850 card_caps &= mmc->host_caps;
1852 /* Only version 4 of MMC supports wider bus widths */
1853 if (mmc->version < MMC_VERSION_4)
1856 if (!mmc->ext_csd) {
1857 pr_debug("No ext_csd found!\n"); /* this should enver happen */
1861 mmc_set_clock(mmc, mmc->legacy_speed, false);
1863 for_each_mmc_mode_by_pref(card_caps, mwt) {
1864 for_each_supported_width(card_caps & mwt->widths,
1865 mmc_is_mode_ddr(mwt->mode), ecbw) {
1866 enum mmc_voltage old_voltage;
1867 pr_debug("trying mode %s width %d (at %d MHz)\n",
1868 mmc_mode_name(mwt->mode),
1869 bus_width(ecbw->cap),
1870 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1871 old_voltage = mmc->signal_voltage;
1872 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1873 MMC_ALL_SIGNAL_VOLTAGE);
1877 /* configure the bus width (card + host) */
1878 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1880 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1883 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1885 /* configure the bus speed (card) */
1886 err = mmc_set_card_speed(mmc, mwt->mode);
1891 * configure the bus width AND the ddr mode (card)
1892 * The host side will be taken care of in the next step
1894 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1895 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1897 ecbw->ext_csd_bits);
1902 /* configure the bus mode (host) */
1903 mmc_select_mode(mmc, mwt->mode);
1904 mmc_set_clock(mmc, mmc->tran_speed, false);
1905 #ifdef MMC_SUPPORTS_TUNING
1907 /* execute tuning if needed */
1909 err = mmc_execute_tuning(mmc, mwt->tuning);
1911 pr_debug("tuning failed\n");
1917 /* do a transfer to check the configuration */
1918 err = mmc_read_and_compare_ext_csd(mmc);
1922 mmc_set_signal_voltage(mmc, old_voltage);
1923 /* if an error occured, revert to a safer bus mode */
1924 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1925 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1926 mmc_select_mode(mmc, MMC_LEGACY);
1927 mmc_set_bus_width(mmc, 1);
1931 pr_err("unable to select a mode\n");
1936 static int mmc_startup_v4(struct mmc *mmc)
1940 bool has_parts = false;
1941 bool part_completed;
1942 static const u32 mmc_versions[] = {
1954 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1956 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1959 /* check ext_csd version and capacity */
1960 err = mmc_send_ext_csd(mmc, ext_csd);
1964 /* store the ext csd for future reference */
1966 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
1969 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
1971 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
1974 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
1976 if (mmc->version >= MMC_VERSION_4_2) {
1978 * According to the JEDEC Standard, the value of
1979 * ext_csd's capacity is valid if the value is more
1982 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1983 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1984 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1985 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1986 capacity *= MMC_MAX_BLOCK_LEN;
1987 if ((capacity >> 20) > 2 * 1024)
1988 mmc->capacity_user = capacity;
1991 /* The partition data may be non-zero but it is only
1992 * effective if PARTITION_SETTING_COMPLETED is set in
1993 * EXT_CSD, so ignore any data if this bit is not set,
1994 * except for enabling the high-capacity group size
1995 * definition (see below).
1997 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1998 EXT_CSD_PARTITION_SETTING_COMPLETED);
2000 /* store the partition info of emmc */
2001 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2002 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2003 ext_csd[EXT_CSD_BOOT_MULT])
2004 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2005 if (part_completed &&
2006 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2007 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2009 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2011 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2013 for (i = 0; i < 4; i++) {
2014 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2015 uint mult = (ext_csd[idx + 2] << 16) +
2016 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2019 if (!part_completed)
2021 mmc->capacity_gp[i] = mult;
2022 mmc->capacity_gp[i] *=
2023 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2024 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2025 mmc->capacity_gp[i] <<= 19;
2028 #ifndef CONFIG_SPL_BUILD
2029 if (part_completed) {
2030 mmc->enh_user_size =
2031 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2032 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2033 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2034 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2035 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2036 mmc->enh_user_size <<= 19;
2037 mmc->enh_user_start =
2038 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2039 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2040 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2041 ext_csd[EXT_CSD_ENH_START_ADDR];
2042 if (mmc->high_capacity)
2043 mmc->enh_user_start <<= 9;
2048 * Host needs to enable ERASE_GRP_DEF bit if device is
2049 * partitioned. This bit will be lost every time after a reset
2050 * or power off. This will affect erase size.
2054 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2055 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2058 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2059 EXT_CSD_ERASE_GROUP_DEF, 1);
2064 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2067 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2068 #if CONFIG_IS_ENABLED(MMC_WRITE)
2069 /* Read out group size from ext_csd */
2070 mmc->erase_grp_size =
2071 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2074 * if high capacity and partition setting completed
2075 * SEC_COUNT is valid even if it is smaller than 2 GiB
2076 * JEDEC Standard JESD84-B45, 6.2.4
2078 if (mmc->high_capacity && part_completed) {
2079 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2080 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2081 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2082 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2083 capacity *= MMC_MAX_BLOCK_LEN;
2084 mmc->capacity_user = capacity;
2087 #if CONFIG_IS_ENABLED(MMC_WRITE)
2089 /* Calculate the group size from the csd value. */
2090 int erase_gsz, erase_gmul;
2092 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2093 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2094 mmc->erase_grp_size = (erase_gsz + 1)
2098 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2099 mmc->hc_wp_grp_size = 1024
2100 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2101 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2104 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2110 mmc->ext_csd = NULL;
2115 static int mmc_startup(struct mmc *mmc)
2121 struct blk_desc *bdesc;
2123 #ifdef CONFIG_MMC_SPI_CRC_ON
2124 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2125 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2126 cmd.resp_type = MMC_RSP_R1;
2128 err = mmc_send_cmd(mmc, &cmd, NULL);
2134 /* Put the Card in Identify Mode */
2135 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2136 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2137 cmd.resp_type = MMC_RSP_R2;
2140 err = mmc_send_cmd(mmc, &cmd, NULL);
2142 #ifdef CONFIG_MMC_QUIRKS
2143 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2146 * It has been seen that SEND_CID may fail on the first
2147 * attempt, let's try a few more time
2150 err = mmc_send_cmd(mmc, &cmd, NULL);
2153 } while (retries--);
2160 memcpy(mmc->cid, cmd.response, 16);
2163 * For MMC cards, set the Relative Address.
2164 * For SD cards, get the Relatvie Address.
2165 * This also puts the cards into Standby State
2167 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2168 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2169 cmd.cmdarg = mmc->rca << 16;
2170 cmd.resp_type = MMC_RSP_R6;
2172 err = mmc_send_cmd(mmc, &cmd, NULL);
2178 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2181 /* Get the Card-Specific Data */
2182 cmd.cmdidx = MMC_CMD_SEND_CSD;
2183 cmd.resp_type = MMC_RSP_R2;
2184 cmd.cmdarg = mmc->rca << 16;
2186 err = mmc_send_cmd(mmc, &cmd, NULL);
2191 mmc->csd[0] = cmd.response[0];
2192 mmc->csd[1] = cmd.response[1];
2193 mmc->csd[2] = cmd.response[2];
2194 mmc->csd[3] = cmd.response[3];
2196 if (mmc->version == MMC_VERSION_UNKNOWN) {
2197 int version = (cmd.response[0] >> 26) & 0xf;
2201 mmc->version = MMC_VERSION_1_2;
2204 mmc->version = MMC_VERSION_1_4;
2207 mmc->version = MMC_VERSION_2_2;
2210 mmc->version = MMC_VERSION_3;
2213 mmc->version = MMC_VERSION_4;
2216 mmc->version = MMC_VERSION_1_2;
2221 /* divide frequency by 10, since the mults are 10x bigger */
2222 freq = fbase[(cmd.response[0] & 0x7)];
2223 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2225 mmc->legacy_speed = freq * mult;
2226 mmc_select_mode(mmc, MMC_LEGACY);
2228 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2229 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2230 #if CONFIG_IS_ENABLED(MMC_WRITE)
2233 mmc->write_bl_len = mmc->read_bl_len;
2235 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2238 if (mmc->high_capacity) {
2239 csize = (mmc->csd[1] & 0x3f) << 16
2240 | (mmc->csd[2] & 0xffff0000) >> 16;
2243 csize = (mmc->csd[1] & 0x3ff) << 2
2244 | (mmc->csd[2] & 0xc0000000) >> 30;
2245 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2248 mmc->capacity_user = (csize + 1) << (cmult + 2);
2249 mmc->capacity_user *= mmc->read_bl_len;
2250 mmc->capacity_boot = 0;
2251 mmc->capacity_rpmb = 0;
2252 for (i = 0; i < 4; i++)
2253 mmc->capacity_gp[i] = 0;
2255 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2256 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2258 #if CONFIG_IS_ENABLED(MMC_WRITE)
2259 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2260 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2263 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2264 cmd.cmdidx = MMC_CMD_SET_DSR;
2265 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2266 cmd.resp_type = MMC_RSP_NONE;
2267 if (mmc_send_cmd(mmc, &cmd, NULL))
2268 pr_warn("MMC: SET_DSR failed\n");
2271 /* Select the card, and put it into Transfer Mode */
2272 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2273 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2274 cmd.resp_type = MMC_RSP_R1;
2275 cmd.cmdarg = mmc->rca << 16;
2276 err = mmc_send_cmd(mmc, &cmd, NULL);
2283 * For SD, its erase group is always one sector
2285 #if CONFIG_IS_ENABLED(MMC_WRITE)
2286 mmc->erase_grp_size = 1;
2288 mmc->part_config = MMCPART_NOAVAILABLE;
2290 err = mmc_startup_v4(mmc);
2294 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2299 err = sd_get_capabilities(mmc);
2302 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2304 err = mmc_get_capabilities(mmc);
2307 mmc_select_mode_and_width(mmc, mmc->card_caps);
2313 mmc->best_mode = mmc->selected_mode;
2315 /* Fix the block length for DDR mode */
2316 if (mmc->ddr_mode) {
2317 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2318 #if CONFIG_IS_ENABLED(MMC_WRITE)
2319 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2323 /* fill in device description */
2324 bdesc = mmc_get_blk_desc(mmc);
2328 bdesc->blksz = mmc->read_bl_len;
2329 bdesc->log2blksz = LOG2(bdesc->blksz);
2330 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2331 #if !defined(CONFIG_SPL_BUILD) || \
2332 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2333 !defined(CONFIG_USE_TINY_PRINTF))
2334 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2335 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2336 (mmc->cid[3] >> 16) & 0xffff);
2337 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2338 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2339 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2340 (mmc->cid[2] >> 24) & 0xff);
2341 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2342 (mmc->cid[2] >> 16) & 0xf);
2344 bdesc->vendor[0] = 0;
2345 bdesc->product[0] = 0;
2346 bdesc->revision[0] = 0;
2348 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
2355 static int mmc_send_if_cond(struct mmc *mmc)
2360 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2361 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2362 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2363 cmd.resp_type = MMC_RSP_R7;
2365 err = mmc_send_cmd(mmc, &cmd, NULL);
2370 if ((cmd.response[0] & 0xff) != 0xaa)
2373 mmc->version = SD_VERSION_2;
2378 #if !CONFIG_IS_ENABLED(DM_MMC)
2379 /* board-specific MMC power initializations. */
2380 __weak void board_mmc_power_init(void)
2385 static int mmc_power_init(struct mmc *mmc)
2387 #if CONFIG_IS_ENABLED(DM_MMC)
2388 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2391 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2394 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2396 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2397 &mmc->vqmmc_supply);
2399 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2401 #else /* !CONFIG_DM_MMC */
2403 * Driver model should use a regulator, as above, rather than calling
2404 * out to board code.
2406 board_mmc_power_init();
2412 * put the host in the initial state:
2413 * - turn on Vdd (card power supply)
2414 * - configure the bus width and clock to minimal values
2416 static void mmc_set_initial_state(struct mmc *mmc)
2420 /* First try to set 3.3V. If it fails set to 1.8V */
2421 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2423 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2425 pr_warn("mmc: failed to set signal voltage\n");
2427 mmc_select_mode(mmc, MMC_LEGACY);
2428 mmc_set_bus_width(mmc, 1);
2429 mmc_set_clock(mmc, 0, false);
2432 static int mmc_power_on(struct mmc *mmc)
2434 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2435 if (mmc->vmmc_supply) {
2436 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2439 puts("Error enabling VMMC supply\n");
2447 static int mmc_power_off(struct mmc *mmc)
2449 mmc_set_clock(mmc, 0, true);
2450 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2451 if (mmc->vmmc_supply) {
2452 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2455 pr_debug("Error disabling VMMC supply\n");
2463 static int mmc_power_cycle(struct mmc *mmc)
2467 ret = mmc_power_off(mmc);
2471 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2472 * to be on the safer side.
2475 return mmc_power_on(mmc);
2478 int mmc_start_init(struct mmc *mmc)
2481 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2485 * all hosts are capable of 1 bit bus-width and able to use the legacy
2488 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2489 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2491 #if !defined(CONFIG_MMC_BROKEN_CD)
2492 /* we pretend there's no card when init is NULL */
2493 no_card = mmc_getcd(mmc) == 0;
2497 #if !CONFIG_IS_ENABLED(DM_MMC)
2498 no_card = no_card || (mmc->cfg->ops->init == NULL);
2502 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2503 pr_err("MMC: no card present\n");
2511 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2512 mmc_adapter_card_type_ident();
2514 err = mmc_power_init(mmc);
2518 #ifdef CONFIG_MMC_QUIRKS
2519 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2520 MMC_QUIRK_RETRY_SEND_CID;
2523 err = mmc_power_cycle(mmc);
2526 * if power cycling is not supported, we should not try
2527 * to use the UHS modes, because we wouldn't be able to
2528 * recover from an error during the UHS initialization.
2530 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2532 mmc->host_caps &= ~UHS_CAPS;
2533 err = mmc_power_on(mmc);
2538 #if CONFIG_IS_ENABLED(DM_MMC)
2539 /* The device has already been probed ready for use */
2541 /* made sure it's not NULL earlier */
2542 err = mmc->cfg->ops->init(mmc);
2549 mmc_set_initial_state(mmc);
2550 mmc_send_init_stream(mmc);
2552 /* Reset the Card */
2553 err = mmc_go_idle(mmc);
2558 /* The internal partition reset to user partition(0) at every CMD0*/
2559 mmc_get_blk_desc(mmc)->hwpart = 0;
2561 /* Test for SD version 2 */
2562 err = mmc_send_if_cond(mmc);
2564 /* Now try to get the SD card's operating condition */
2565 err = sd_send_op_cond(mmc, uhs_en);
2566 if (err && uhs_en) {
2568 mmc_power_cycle(mmc);
2572 /* If the command timed out, we check for an MMC card */
2573 if (err == -ETIMEDOUT) {
2574 err = mmc_send_op_cond(mmc);
2577 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2578 pr_err("Card did not respond to voltage select!\n");
2585 mmc->init_in_progress = 1;
2590 static int mmc_complete_init(struct mmc *mmc)
2594 mmc->init_in_progress = 0;
2595 if (mmc->op_cond_pending)
2596 err = mmc_complete_op_cond(mmc);
2599 err = mmc_startup(mmc);
2607 int mmc_init(struct mmc *mmc)
2610 __maybe_unused unsigned start;
2611 #if CONFIG_IS_ENABLED(DM_MMC)
2612 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2619 start = get_timer(0);
2621 if (!mmc->init_in_progress)
2622 err = mmc_start_init(mmc);
2625 err = mmc_complete_init(mmc);
2627 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2632 int mmc_set_dsr(struct mmc *mmc, u16 val)
2638 /* CPU-specific MMC initializations */
2639 __weak int cpu_mmc_init(bd_t *bis)
2644 /* board-specific MMC initializations. */
2645 __weak int board_mmc_init(bd_t *bis)
2650 void mmc_set_preinit(struct mmc *mmc, int preinit)
2652 mmc->preinit = preinit;
2655 #if CONFIG_IS_ENABLED(DM_MMC)
2656 static int mmc_probe(bd_t *bis)
2660 struct udevice *dev;
2662 ret = uclass_get(UCLASS_MMC, &uc);
2667 * Try to add them in sequence order. Really with driver model we
2668 * should allow holes, but the current MMC list does not allow that.
2669 * So if we request 0, 1, 3 we will get 0, 1, 2.
2671 for (i = 0; ; i++) {
2672 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2676 uclass_foreach_dev(dev, uc) {
2677 ret = device_probe(dev);
2679 pr_err("%s - probe failed: %d\n", dev->name, ret);
2685 static int mmc_probe(bd_t *bis)
2687 if (board_mmc_init(bis) < 0)
2694 int mmc_initialize(bd_t *bis)
2696 static int initialized = 0;
2698 if (initialized) /* Avoid initializing mmc multiple times */
2702 #if !CONFIG_IS_ENABLED(BLK)
2703 #if !CONFIG_IS_ENABLED(MMC_TINY)
2707 ret = mmc_probe(bis);
2711 #ifndef CONFIG_SPL_BUILD
2712 print_mmc_devices(',');
2719 #ifdef CONFIG_CMD_BKOPS_ENABLE
2720 int mmc_set_bkops_enable(struct mmc *mmc)
2723 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2725 err = mmc_send_ext_csd(mmc, ext_csd);
2727 puts("Could not get ext_csd register values\n");
2731 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2732 puts("Background operations not supported on device\n");
2733 return -EMEDIUMTYPE;
2736 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2737 puts("Background operations already enabled\n");
2741 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2743 puts("Failed to enable manual background operations\n");
2747 puts("Enabled manual background operations\n");